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module aib_top_wrapper_v2s
# (
parameter DATA_WIDTH = 78,
parameter TOTAL_CHNL_NUM = 24
)
(
//================================================================================================
// Reset Inteface
input i_conf_done, // AIB adaptor hard reset
input dual_mode_select,
// reset for XCVRIF
output [TOTAL_CHNL_NUM-1:0] fs_mac_rdy, //o_rx_xcvrif_rst_n, receiving path reset
//===============================================================================================
// Configuration Interface which includes two paths
// Path directly from chip programming controller
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n,
input [16:0] i_cfg_avmm_addr, // address to be programmed
input [3:0] i_cfg_avmm_byte_en, // byte enable
input i_cfg_avmm_read, // Asserted to indicate the Cfg read access
input i_cfg_avmm_write, // Asserted to indicate the Cfg write access
input [31:0] i_cfg_avmm_wdata, // data to be programmed
output o_cfg_avmm_rdatavld,// Assert to indicate data available for Cfg read access
output [31:0] o_cfg_avmm_rdata, // data returned for Cfg read access
output o_cfg_avmm_waitreq, // asserted to indicate not ready for Cfg access
//===============================================================================================
// Data Path
// Rx Path clocks/data, from master (current chiplet) to slave (FPGA)
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_clk, // i_rx_pma_clk.Rx path clk for data receiving,
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_div2_clk, // i_rx_pma_div2_clk, Divided by 2 clock on Rx pathinput
input [TOTAL_CHNL_NUM*DATA_WIDTH-1:0] data_in , // i_rx_pma_data, Directed bump rx data sync path
input [TOTAL_CHNL_NUM-1:0] m_wr_clk, //Clock for phase compensation fifo
// Tx Path clocks/data, from slave (FPGA) to master (current chiplet)
input [TOTAL_CHNL_NUM-1:0] m_ns_rcv_clk, //i_tx_pma_clk, sent over to the other chiplet to be used for the clock
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_clk, //o_tx_transfer_clk, clock used for tx data transmission
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_div2_clk, // o_tx_transfer_div2_clk, half rate of tx data transmission clock
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_clk,
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_div2_clk,
output [TOTAL_CHNL_NUM*78-1:0] data_out, //o_tx_pma_data, Directed bump tx data sync path
input [TOTAL_CHNL_NUM-1:0] m_rd_clk, //Clock for phase compensation fifo
//=================================================================================================
// AIB open source IP enhancement. The following ports are added to
// be compliance with AIB specification 1.1
input [TOTAL_CHNL_NUM-1:0] ns_mac_rdy, //From Mac. To indicate MAC is ready to send and receive // data. use aibio49
input [TOTAL_CHNL_NUM-1:0] ns_adapter_rstn, //From Mac. To reset near site adapt reset state machine and far site sm. Not implemented currently.
output [TOTAL_CHNL_NUM*81-1:0] ms_sideband, //Status of serial shifting bit from this master chiplet to slave chiplet
output [TOTAL_CHNL_NUM*73-1:0] sl_sideband, //Status of serial shifting bit from slave chiplet to master chiplet.
output [TOTAL_CHNL_NUM-1:0] m_rxfifo_align_done,
output [TOTAL_CHNL_NUM-1:0] ms_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] ms_rx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_rx_transfer_en,
input [TOTAL_CHNL_NUM-1:0] sl_tx_dcc_dll_lock_req,
input [TOTAL_CHNL_NUM-1:0] sl_rx_dcc_dll_lock_req,
//=================================================================================================
// Inout signals for AIB ubump
inout [TOTAL_CHNL_NUM*20-1:0] iopad_tx,
inout [TOTAL_CHNL_NUM*20-1:0] iopad_rx,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_fwd_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_fwd_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_mac_rdy,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_mac_rdy,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_adapter_rstn,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_rcv_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_adapter_rstn,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_div2_clkb,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_rcv_div2_clk,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_load,
inout [TOTAL_CHNL_NUM-1:0] iopad_fs_sr_data,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_load,
inout [TOTAL_CHNL_NUM-1:0] iopad_ns_sr_data,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib45,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib46,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib47,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib50,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib51,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib52,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib58,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib60,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib61,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib62,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib63,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib64,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib66,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib67,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib68,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib69,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib70,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib71,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib72,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib73,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib74,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib75,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib76,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib77,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib78,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib79,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib80,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib81,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib88,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib89,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib90,
inout [TOTAL_CHNL_NUM-1:0] iopad_unused_aib91,
inout por, //iopad_aib_aux[85] power on from slave.
inout device_detect, //iopad_aib_aux[74] device detect to slave
//======================================================================================
// Interface with AIB control block
input m_power_on_reset,
output m_device_detect,
input m_device_detect_ovrd,
// from control block register file
// input [31:0] i_aibaux_ctrl_bus0, //1st set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus1, //2nd set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus2, //3rd set of register bits from register file
// input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User
//
input i_osc_clk, // test clock from c4 bump, may tie low for User if not used
output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator
//======================================================================================
// DFT signals
input scan_clk,
input scan_enable,
input [19:0] scan_in_ch0,
input [19:0] scan_in_ch1,
input [19:0] scan_in_ch2,
input [19:0] scan_in_ch3,
input [19:0] scan_in_ch4,
input [19:0] scan_in_ch5,
input [19:0] scan_in_ch6,
input [19:0] scan_in_ch7,
input [19:0] scan_in_ch8,
input [19:0] scan_in_ch9,
input [19:0] scan_in_ch10,
input [19:0] scan_in_ch11,
input [19:0] scan_in_ch12,
input [19:0] scan_in_ch13,
input [19:0] scan_in_ch14,
input [19:0] scan_in_ch15,
input [19:0] scan_in_ch16,
input [19:0] scan_in_ch17,
input [19:0] scan_in_ch18,
input [19:0] scan_in_ch19,
input [19:0] scan_in_ch20,
input [19:0] scan_in_ch21,
input [19:0] scan_in_ch22,
input [19:0] scan_in_ch23,
// output [TOTAL_CHNL_NUM-1:0] [19:0] scan_out,
output [19:0] scan_out_ch0,
output [19:0] scan_out_ch1,
output [19:0] scan_out_ch2,
output [19:0] scan_out_ch3,
output [19:0] scan_out_ch4,
output [19:0] scan_out_ch5,
output [19:0] scan_out_ch6,
output [19:0] scan_out_ch7,
output [19:0] scan_out_ch8,
output [19:0] scan_out_ch9,
output [19:0] scan_out_ch10,
output [19:0] scan_out_ch11,
output [19:0] scan_out_ch12,
output [19:0] scan_out_ch13,
output [19:0] scan_out_ch14,
output [19:0] scan_out_ch15,
output [19:0] scan_out_ch16,
output [19:0] scan_out_ch17,
output [19:0] scan_out_ch18,
output [19:0] scan_out_ch19,
output [19:0] scan_out_ch20,
output [19:0] scan_out_ch21,
output [19:0] scan_out_ch22,
output [19:0] scan_out_ch23,
input i_scan_clk, //ATPG Scan shifting clock from Test Pad.
input i_test_scan_en,
input i_test_scan_mode,
// input i_test_clk_1g, //1GHz free running direct accessed ATPG at speed clock.
// input i_test_clk_125m,//Divided down from i_test_clk_1g.
// input i_test_clk_250m,//Divided down from i_test_clk_1g.
// input i_test_clk_500m,//Divided down from i_test_clk_1g.
// input i_test_clk_62m, //Divided down from i_test_clk_1g.
//The divided down clock is for different clock domain at
//speed test.
//Channel ATPG signals from/to CODEC
// input [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] i_test_c3adapt_scan_in, //scan in hook from Codec
// output [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] o_test_c3adapt_scan_out, //scan out hook to Codec
//Inputs from TCB (JTAG signals)
input i_jtag_clkdr, // (from dbg_test_bscan block)Enable AIB IO boundary scan clock (clock gate control)
input i_jtag_clksel, // (from dbg_test_bscan block)Select between i_jtag_clkdr_in and functional clk
input i_jtag_intest, // (from dbg_test_bscan block)Enable in test operation
input i_jtag_mode, // (from dbg_test_bscan block)Selects between AIB BSR register or functional path
input i_jtag_rstb, // (from dbg_test_bscan block)JTAG controlleable reset the AIB IO circuitry
input i_jtag_rstb_en, // (from dbg_test_bscan block)JTAG controlleable override to reset the AIB IO circuitry
input i_jtag_tdi, // (from dbg_test_bscan block)TDI
input i_jtag_tx_scanen,// (from dbg_test_bscan block)Drives AIB IO jtag_tx_scanen_in or BSR shift control
input i_jtag_weakpdn, //(from dbg_test_bscan block)Enable AIB global pull down test.
input i_jtag_weakpu, //(from dbg_test_bscan block)Enable AIB global pull up test.
// input [2:0] i_aibdft2osc, //To AIB osc.[2] force reset [1] force enable [0] 33 MHz JTAG
// output [12:0] o_aibdft2osc, //Observability of osc and DLL/DCC status
//this signal go through C4 bump, User may muxed it out with their test signals
//output TCB
output o_jtag_tdo //last boundary scan chain output, TDO
);
wire [TOTAL_CHNL_NUM-1:0] i_rx_pma_clk;
wire [TOTAL_CHNL_NUM-1:0] i_rx_pma_div2_clk;
wire [TOTAL_CHNL_NUM*40-1:0] i_rx_pma_data;
wire [TOTAL_CHNL_NUM-1:0] i_tx_pma_clk;
wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_clk;
wire [TOTAL_CHNL_NUM-1:0] o_tx_transfer_div2_clk;
wire [TOTAL_CHNL_NUM*40-1:0] o_tx_pma_data;
wire [TOTAL_CHNL_NUM-1:0] o_rx_xcvrif_rst_n;
wire HI, LO;
assign HI = 1'b1;
assign LO = 1'b0;
//assign i_rx_pma_clk = m_ns_fwd_clk;
//assign i_rx_pma_div2_clk = m_ns_fwd_div2_clk;
//assign i_rx_pma_data = data_in;
//assign i_tx_pma_clk = m_ns_rcv_clk;
//assign m_fs_fwd_clk = o_tx_transfer_clk;
//assign m_fs_fwd_div2_clk = o_tx_transfer_div2_clk;
//assign data_out = o_tx_pma_data;
//assign fs_mac_rdy = o_rx_xcvrif_rst_n;
aib_top_v2s u_aib_top
(
.i_conf_done (i_conf_done),
.dual_mode_select (dual_mode_select),
.fs_mac_rdy (fs_mac_rdy),
.i_cfg_avmm_clk (i_cfg_avmm_clk),
.i_cfg_avmm_rst_n (i_cfg_avmm_rst_n),
.i_cfg_avmm_addr (i_cfg_avmm_addr[16:0]),
.i_cfg_avmm_byte_en (i_cfg_avmm_byte_en[3:0]),
.i_cfg_avmm_read (i_cfg_avmm_read),
.i_cfg_avmm_write (i_cfg_avmm_write),
.i_cfg_avmm_wdata (i_cfg_avmm_wdata[31:0]),
.o_cfg_avmm_rdatavld (o_cfg_avmm_rdatavld),
.o_cfg_avmm_rdata (o_cfg_avmm_rdata),
.o_cfg_avmm_waitreq (o_cfg_avmm_waitreq),
.m_ns_fwd_clk (m_ns_fwd_clk),
.m_ns_fwd_div2_clk (m_ns_fwd_div2_clk),
.m_wr_clk (m_wr_clk),
.data_in (data_in),
// .i_rx_pma_data ('0),
.m_ns_rcv_clk (m_ns_rcv_clk),
.m_fs_fwd_clk (m_fs_fwd_clk),
.m_fs_fwd_div2_clk (m_fs_fwd_div2_clk), // Not used
.m_fs_rcv_clk (m_fs_rcv_clk),
.m_fs_rcv_div2_clk (m_fs_rcv_div2_clk),
.m_rd_clk (m_rd_clk),
.data_out (data_out),
.ns_mac_rdy (ns_mac_rdy),
.ns_adapter_rstn (ns_adapter_rstn),
.ms_sideband (ms_sideband),
.sl_sideband (sl_sideband),
.m_rxfifo_align_done (m_rxfifo_align_done),
.m_power_on_reset (m_power_on_reset),
.m_device_detect (m_device_detect),
.m_device_detect_ovrd (m_device_detect_ovrd),
.ms_tx_transfer_en (ms_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.ms_rx_transfer_en (ms_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_transfer_en (sl_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_rx_transfer_en (sl_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_dcc_dll_lock_req (sl_tx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.sl_rx_dcc_dll_lock_req (sl_rx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.s0_ch0_aib( { iopad_fs_sr_data[0], iopad_fs_sr_load[0], iopad_ns_sr_data[0], iopad_ns_sr_load[0],
iopad_unused_aib91[0], iopad_unused_aib90[0], iopad_unused_aib89[0], iopad_unused_aib88[0],
iopad_fs_rcv_clk[0], iopad_fs_rcv_clkb[0], iopad_fs_sr_clk[0], iopad_fs_sr_clkb[0],
iopad_ns_sr_clk[0], iopad_ns_sr_clkb[0], iopad_unused_aib81[0], iopad_unused_aib80[0],
iopad_unused_aib79[0], iopad_unused_aib78[0], iopad_unused_aib77[0], iopad_unused_aib76[0],
iopad_unused_aib75[0], iopad_unused_aib74[0], iopad_unused_aib73[0], iopad_unused_aib72[0],
iopad_unused_aib71[0], iopad_unused_aib70[0], iopad_unused_aib69[0], iopad_unused_aib68[0],
iopad_unused_aib67[0], iopad_unused_aib66[0], iopad_ns_adapter_rstn[0], iopad_unused_aib64[0],
iopad_unused_aib63[0], iopad_unused_aib62[0], iopad_unused_aib61[0], iopad_unused_aib60[0],
iopad_ns_rcv_clkb[0], iopad_unused_aib58[0], iopad_ns_rcv_clk[0], iopad_fs_adapter_rstn[0],
iopad_fs_rcv_div2_clkb[0], iopad_fs_fwd_div2_clkb[0], iopad_fs_fwd_div2_clk[0], iopad_unused_aib52[0],
iopad_unused_aib51[0], iopad_unused_aib50[0], iopad_fs_mac_rdy[0], iopad_fs_rcv_div2_clk[0],
iopad_unused_aib47[0], iopad_unused_aib46[0], iopad_unused_aib45[0], iopad_ns_mac_rdy[0],
iopad_ns_fwd_clk[0], iopad_ns_fwd_clkb[0], iopad_fs_fwd_clk[0], iopad_fs_fwd_clkb[0],
iopad_tx[19:0], iopad_rx[19:0]}),
.s0_ch1_aib( { iopad_fs_sr_data[1], iopad_fs_sr_load[1], iopad_ns_sr_data[1], iopad_ns_sr_load[1],
iopad_unused_aib91[1], iopad_unused_aib90[1], iopad_unused_aib89[1], iopad_unused_aib88[1],
iopad_fs_rcv_clk[1], iopad_fs_rcv_clkb[1], iopad_fs_sr_clk[1], iopad_fs_sr_clkb[1],
iopad_ns_sr_clk[1], iopad_ns_sr_clkb[1], iopad_unused_aib81[1], iopad_unused_aib80[1],
iopad_unused_aib79[1], iopad_unused_aib78[1], iopad_unused_aib77[1], iopad_unused_aib76[1],
iopad_unused_aib75[1], iopad_unused_aib74[1], iopad_unused_aib73[1], iopad_unused_aib72[1],
iopad_unused_aib71[1], iopad_unused_aib70[1], iopad_unused_aib69[1], iopad_unused_aib68[1],
iopad_unused_aib67[1], iopad_unused_aib66[1], iopad_ns_adapter_rstn[1], iopad_unused_aib64[1],
iopad_unused_aib63[1], iopad_unused_aib62[1], iopad_unused_aib61[1], iopad_unused_aib60[1],
iopad_ns_rcv_clkb[1], iopad_unused_aib58[1], iopad_ns_rcv_clk[1], iopad_fs_adapter_rstn[1],
iopad_fs_rcv_div2_clkb[1], iopad_fs_fwd_div2_clkb[1], iopad_fs_fwd_div2_clk[1], iopad_unused_aib52[1],
iopad_unused_aib51[1], iopad_unused_aib50[1], iopad_fs_mac_rdy[1], iopad_fs_rcv_div2_clk[1],
iopad_unused_aib47[1], iopad_unused_aib46[1], iopad_unused_aib45[1], iopad_ns_mac_rdy[1],
iopad_ns_fwd_clk[1], iopad_ns_fwd_clkb[1], iopad_fs_fwd_clk[1], iopad_fs_fwd_clkb[1],
iopad_tx[39:20], iopad_rx[39:20]}),
.s0_ch2_aib( { iopad_fs_sr_data[2], iopad_fs_sr_load[2], iopad_ns_sr_data[2], iopad_ns_sr_load[2],
iopad_unused_aib91[2], iopad_unused_aib90[2], iopad_unused_aib89[2], iopad_unused_aib88[2],
iopad_fs_rcv_clk[2], iopad_fs_rcv_clkb[2], iopad_fs_sr_clk[2], iopad_fs_sr_clkb[2],
iopad_ns_sr_clk[2], iopad_ns_sr_clkb[2], iopad_unused_aib81[2], iopad_unused_aib80[2],
iopad_unused_aib79[2], iopad_unused_aib78[2], iopad_unused_aib77[2], iopad_unused_aib76[2],
iopad_unused_aib75[2], iopad_unused_aib74[2], iopad_unused_aib73[2], iopad_unused_aib72[2],
iopad_unused_aib71[2], iopad_unused_aib70[2], iopad_unused_aib69[2], iopad_unused_aib68[2],
iopad_unused_aib67[2], iopad_unused_aib66[2], iopad_ns_adapter_rstn[2], iopad_unused_aib64[2],
iopad_unused_aib63[2], iopad_unused_aib62[2], iopad_unused_aib61[2], iopad_unused_aib60[2],
iopad_ns_rcv_clkb[2], iopad_unused_aib58[2], iopad_ns_rcv_clk[2], iopad_fs_adapter_rstn[2],
iopad_fs_rcv_div2_clkb[2], iopad_fs_fwd_div2_clkb[2], iopad_fs_fwd_div2_clk[2], iopad_unused_aib52[2],
iopad_unused_aib51[2], iopad_unused_aib50[2], iopad_fs_mac_rdy[2], iopad_fs_rcv_div2_clk[2],
iopad_unused_aib47[2], iopad_unused_aib46[2], iopad_unused_aib45[2], iopad_ns_mac_rdy[2],
iopad_ns_fwd_clk[2], iopad_ns_fwd_clkb[2], iopad_fs_fwd_clk[2], iopad_fs_fwd_clkb[2],
iopad_tx[59:40], iopad_rx[59:40]}),
.s0_ch3_aib( { iopad_fs_sr_data[3], iopad_fs_sr_load[3], iopad_ns_sr_data[3], iopad_ns_sr_load[3],
iopad_unused_aib91[3], iopad_unused_aib90[3], iopad_unused_aib89[3], iopad_unused_aib88[3],
iopad_fs_rcv_clk[3], iopad_fs_rcv_clkb[3], iopad_fs_sr_clk[3], iopad_fs_sr_clkb[3],
iopad_ns_sr_clk[3], iopad_ns_sr_clkb[3], iopad_unused_aib81[3], iopad_unused_aib80[3],
iopad_unused_aib79[3], iopad_unused_aib78[3], iopad_unused_aib77[3], iopad_unused_aib76[3],
iopad_unused_aib75[3], iopad_unused_aib74[3], iopad_unused_aib73[3], iopad_unused_aib72[3],
iopad_unused_aib71[3], iopad_unused_aib70[3], iopad_unused_aib69[3], iopad_unused_aib68[3],
iopad_unused_aib67[3], iopad_unused_aib66[3], iopad_ns_adapter_rstn[3], iopad_unused_aib64[3],
iopad_unused_aib63[3], iopad_unused_aib62[3], iopad_unused_aib61[3], iopad_unused_aib60[3],
iopad_ns_rcv_clkb[3], iopad_unused_aib58[3], iopad_ns_rcv_clk[3], iopad_fs_adapter_rstn[3],
iopad_fs_rcv_div2_clkb[3], iopad_fs_fwd_div2_clkb[3], iopad_fs_fwd_div2_clk[3], iopad_unused_aib52[3],
iopad_unused_aib51[3], iopad_unused_aib50[3], iopad_fs_mac_rdy[3], iopad_fs_rcv_div2_clk[3],
iopad_unused_aib47[3], iopad_unused_aib46[3], iopad_unused_aib45[3], iopad_ns_mac_rdy[3],
iopad_ns_fwd_clk[3], iopad_ns_fwd_clkb[3], iopad_fs_fwd_clk[3], iopad_fs_fwd_clkb[3],
iopad_tx[79:60], iopad_rx[79:60]}),
.s0_ch4_aib( { iopad_fs_sr_data[4], iopad_fs_sr_load[4], iopad_ns_sr_data[4], iopad_ns_sr_load[4],
iopad_unused_aib91[4], iopad_unused_aib90[4], iopad_unused_aib89[4], iopad_unused_aib88[4],
iopad_fs_rcv_clk[4], iopad_fs_rcv_clkb[4], iopad_fs_sr_clk[4], iopad_fs_sr_clkb[4],
iopad_ns_sr_clk[4], iopad_ns_sr_clkb[4], iopad_unused_aib81[4], iopad_unused_aib80[4],
iopad_unused_aib79[4], iopad_unused_aib78[4], iopad_unused_aib77[4], iopad_unused_aib76[4],
iopad_unused_aib75[4], iopad_unused_aib74[4], iopad_unused_aib73[4], iopad_unused_aib72[4],
iopad_unused_aib71[4], iopad_unused_aib70[4], iopad_unused_aib69[4], iopad_unused_aib68[4],
iopad_unused_aib67[4], iopad_unused_aib66[4], iopad_ns_adapter_rstn[4], iopad_unused_aib64[4],
iopad_unused_aib63[4], iopad_unused_aib62[4], iopad_unused_aib61[4], iopad_unused_aib60[4],
iopad_ns_rcv_clkb[4], iopad_unused_aib58[4], iopad_ns_rcv_clk[4], iopad_fs_adapter_rstn[4],
iopad_fs_rcv_div2_clkb[4], iopad_fs_fwd_div2_clkb[4], iopad_fs_fwd_div2_clk[4], iopad_unused_aib52[4],
iopad_unused_aib51[4], iopad_unused_aib50[4], iopad_fs_mac_rdy[4], iopad_fs_rcv_div2_clk[4],
iopad_unused_aib47[4], iopad_unused_aib46[4], iopad_unused_aib45[4], iopad_ns_mac_rdy[4],
iopad_ns_fwd_clk[4], iopad_ns_fwd_clkb[4], iopad_fs_fwd_clk[4], iopad_fs_fwd_clkb[4],
iopad_tx[99:80], iopad_rx[99:80]}),
.s0_ch5_aib( { iopad_fs_sr_data[5], iopad_fs_sr_load[5], iopad_ns_sr_data[5], iopad_ns_sr_load[5],
iopad_unused_aib91[5], iopad_unused_aib90[5], iopad_unused_aib89[5], iopad_unused_aib88[5],
iopad_fs_rcv_clk[5], iopad_fs_rcv_clkb[5], iopad_fs_sr_clk[5], iopad_fs_sr_clkb[5],
iopad_ns_sr_clk[5], iopad_ns_sr_clkb[5], iopad_unused_aib81[5], iopad_unused_aib80[5],
iopad_unused_aib79[5], iopad_unused_aib78[5], iopad_unused_aib77[5], iopad_unused_aib76[5],
iopad_unused_aib75[5], iopad_unused_aib74[5], iopad_unused_aib73[5], iopad_unused_aib72[5],
iopad_unused_aib71[5], iopad_unused_aib70[5], iopad_unused_aib69[5], iopad_unused_aib68[5],
iopad_unused_aib67[5], iopad_unused_aib66[5], iopad_ns_adapter_rstn[5], iopad_unused_aib64[5],
iopad_unused_aib63[5], iopad_unused_aib62[5], iopad_unused_aib61[5], iopad_unused_aib60[5],
iopad_ns_rcv_clkb[5], iopad_unused_aib58[5], iopad_ns_rcv_clk[5], iopad_fs_adapter_rstn[5],
iopad_fs_rcv_div2_clkb[5], iopad_fs_fwd_div2_clkb[5], iopad_fs_fwd_div2_clk[5], iopad_unused_aib52[5],
iopad_unused_aib51[5], iopad_unused_aib50[5], iopad_fs_mac_rdy[5], iopad_fs_rcv_div2_clk[5],
iopad_unused_aib47[5], iopad_unused_aib46[5], iopad_unused_aib45[5], iopad_ns_mac_rdy[5],
iopad_ns_fwd_clk[5], iopad_ns_fwd_clkb[5], iopad_fs_fwd_clk[5], iopad_fs_fwd_clkb[5],
iopad_tx[119:100], iopad_rx[119:100]}),
.s1_ch0_aib( { iopad_fs_sr_data[6], iopad_fs_sr_load[6], iopad_ns_sr_data[6], iopad_ns_sr_load[6],
iopad_unused_aib91[6], iopad_unused_aib90[6], iopad_unused_aib89[6], iopad_unused_aib88[6],
iopad_fs_rcv_clk[6], iopad_fs_rcv_clkb[6], iopad_fs_sr_clk[6], iopad_fs_sr_clkb[6],
iopad_ns_sr_clk[6], iopad_ns_sr_clkb[6], iopad_unused_aib81[6], iopad_unused_aib80[6],
iopad_unused_aib79[6], iopad_unused_aib78[6], iopad_unused_aib77[6], iopad_unused_aib76[6],
iopad_unused_aib75[6], iopad_unused_aib74[6], iopad_unused_aib73[6], iopad_unused_aib72[6],
iopad_unused_aib71[6], iopad_unused_aib70[6], iopad_unused_aib69[6], iopad_unused_aib68[6],
iopad_unused_aib67[6], iopad_unused_aib66[6], iopad_ns_adapter_rstn[6], iopad_unused_aib64[6],
iopad_unused_aib63[6], iopad_unused_aib62[6], iopad_unused_aib61[6], iopad_unused_aib60[6],
iopad_ns_rcv_clkb[6], iopad_unused_aib58[6], iopad_ns_rcv_clk[6], iopad_fs_adapter_rstn[6],
iopad_fs_rcv_div2_clkb[6], iopad_fs_fwd_div2_clkb[6], iopad_fs_fwd_div2_clk[6], iopad_unused_aib52[6],
iopad_unused_aib51[6], iopad_unused_aib50[6], iopad_fs_mac_rdy[6], iopad_fs_rcv_div2_clk[6],
iopad_unused_aib47[6], iopad_unused_aib46[6], iopad_unused_aib45[6], iopad_ns_mac_rdy[6],
iopad_ns_fwd_clk[6], iopad_ns_fwd_clkb[6], iopad_fs_fwd_clk[6], iopad_fs_fwd_clkb[6],
iopad_tx[139:120], iopad_rx[139:120]}),
.s1_ch1_aib( { iopad_fs_sr_data[7], iopad_fs_sr_load[7], iopad_ns_sr_data[7], iopad_ns_sr_load[7],
iopad_unused_aib91[7], iopad_unused_aib90[7], iopad_unused_aib89[7], iopad_unused_aib88[7],
iopad_fs_rcv_clk[7], iopad_fs_rcv_clkb[7], iopad_fs_sr_clk[7], iopad_fs_sr_clkb[7],
iopad_ns_sr_clk[7], iopad_ns_sr_clkb[7], iopad_unused_aib81[7], iopad_unused_aib80[7],
iopad_unused_aib79[7], iopad_unused_aib78[7], iopad_unused_aib77[7], iopad_unused_aib76[7],
iopad_unused_aib75[7], iopad_unused_aib74[7], iopad_unused_aib73[7], iopad_unused_aib72[7],
iopad_unused_aib71[7], iopad_unused_aib70[7], iopad_unused_aib69[7], iopad_unused_aib68[7],
iopad_unused_aib67[7], iopad_unused_aib66[7], iopad_ns_adapter_rstn[7], iopad_unused_aib64[7],
iopad_unused_aib63[7], iopad_unused_aib62[7], iopad_unused_aib61[7], iopad_unused_aib60[7],
iopad_ns_rcv_clkb[7], iopad_unused_aib58[7], iopad_ns_rcv_clk[7], iopad_fs_adapter_rstn[7],
iopad_fs_rcv_div2_clkb[7], iopad_fs_fwd_div2_clkb[7], iopad_fs_fwd_div2_clk[7], iopad_unused_aib52[7],
iopad_unused_aib51[7], iopad_unused_aib50[7], iopad_fs_mac_rdy[7], iopad_fs_rcv_div2_clk[7],
iopad_unused_aib47[7], iopad_unused_aib46[7], iopad_unused_aib45[7], iopad_ns_mac_rdy[7],
iopad_ns_fwd_clk[7], iopad_ns_fwd_clkb[7], iopad_fs_fwd_clk[7], iopad_fs_fwd_clkb[7],
iopad_tx[159:140], iopad_rx[159:140]}),
.s1_ch2_aib( { iopad_fs_sr_data[8], iopad_fs_sr_load[8], iopad_ns_sr_data[8], iopad_ns_sr_load[8],
iopad_unused_aib91[8], iopad_unused_aib90[8], iopad_unused_aib89[8], iopad_unused_aib88[8],
iopad_fs_rcv_clk[8], iopad_fs_rcv_clkb[8], iopad_fs_sr_clk[8], iopad_fs_sr_clkb[8],
iopad_ns_sr_clk[8], iopad_ns_sr_clkb[8], iopad_unused_aib81[8], iopad_unused_aib80[8],
iopad_unused_aib79[8], iopad_unused_aib78[8], iopad_unused_aib77[8], iopad_unused_aib76[8],
iopad_unused_aib75[8], iopad_unused_aib74[8], iopad_unused_aib73[8], iopad_unused_aib72[8],
iopad_unused_aib71[8], iopad_unused_aib70[8], iopad_unused_aib69[8], iopad_unused_aib68[8],
iopad_unused_aib67[8], iopad_unused_aib66[8], iopad_ns_adapter_rstn[8], iopad_unused_aib64[8],
iopad_unused_aib63[8], iopad_unused_aib62[8], iopad_unused_aib61[8], iopad_unused_aib60[8],
iopad_ns_rcv_clkb[8], iopad_unused_aib58[8], iopad_ns_rcv_clk[8], iopad_fs_adapter_rstn[8],
iopad_fs_rcv_div2_clkb[8], iopad_fs_fwd_div2_clkb[8], iopad_fs_fwd_div2_clk[8], iopad_unused_aib52[8],
iopad_unused_aib51[8], iopad_unused_aib50[8], iopad_fs_mac_rdy[8], iopad_fs_rcv_div2_clk[8],
iopad_unused_aib47[8], iopad_unused_aib46[8], iopad_unused_aib45[8], iopad_ns_mac_rdy[8],
iopad_ns_fwd_clk[8], iopad_ns_fwd_clkb[8], iopad_fs_fwd_clk[8], iopad_fs_fwd_clkb[8],
iopad_tx[179:160], iopad_rx[179:160]}),
.s1_ch3_aib( { iopad_fs_sr_data[9], iopad_fs_sr_load[9], iopad_ns_sr_data[9], iopad_ns_sr_load[9],
iopad_unused_aib91[9], iopad_unused_aib90[9], iopad_unused_aib89[9], iopad_unused_aib88[9],
iopad_fs_rcv_clk[9], iopad_fs_rcv_clkb[9], iopad_fs_sr_clk[9], iopad_fs_sr_clkb[9],
iopad_ns_sr_clk[9], iopad_ns_sr_clkb[9], iopad_unused_aib81[9], iopad_unused_aib80[9],
iopad_unused_aib79[9], iopad_unused_aib78[9], iopad_unused_aib77[9], iopad_unused_aib76[9],
iopad_unused_aib75[9], iopad_unused_aib74[9], iopad_unused_aib73[9], iopad_unused_aib72[9],
iopad_unused_aib71[9], iopad_unused_aib70[9], iopad_unused_aib69[9], iopad_unused_aib68[9],
iopad_unused_aib67[9], iopad_unused_aib66[9], iopad_ns_adapter_rstn[9], iopad_unused_aib64[9],
iopad_unused_aib63[9], iopad_unused_aib62[9], iopad_unused_aib61[9], iopad_unused_aib60[9],
iopad_ns_rcv_clkb[9], iopad_unused_aib58[9], iopad_ns_rcv_clk[9], iopad_fs_adapter_rstn[9],
iopad_fs_rcv_div2_clkb[9], iopad_fs_fwd_div2_clkb[9], iopad_fs_fwd_div2_clk[9], iopad_unused_aib52[9],
iopad_unused_aib51[9], iopad_unused_aib50[9], iopad_fs_mac_rdy[9], iopad_fs_rcv_div2_clk[9],
iopad_unused_aib47[9], iopad_unused_aib46[9], iopad_unused_aib45[9], iopad_ns_mac_rdy[9],
iopad_ns_fwd_clk[9], iopad_ns_fwd_clkb[9], iopad_fs_fwd_clk[9], iopad_fs_fwd_clkb[9],
iopad_tx[199:180], iopad_rx[199:180]}),
.s1_ch4_aib( { iopad_fs_sr_data[10], iopad_fs_sr_load[10], iopad_ns_sr_data[10], iopad_ns_sr_load[10],
iopad_unused_aib91[10], iopad_unused_aib90[10], iopad_unused_aib89[10], iopad_unused_aib88[10],
iopad_fs_rcv_clk[10], iopad_fs_rcv_clkb[10], iopad_fs_sr_clk[10], iopad_fs_sr_clkb[10],
iopad_ns_sr_clk[10], iopad_ns_sr_clkb[10], iopad_unused_aib81[10], iopad_unused_aib80[10],
iopad_unused_aib79[10], iopad_unused_aib78[10], iopad_unused_aib77[10], iopad_unused_aib76[10],
iopad_unused_aib75[10], iopad_unused_aib74[10], iopad_unused_aib73[10], iopad_unused_aib72[10],
iopad_unused_aib71[10], iopad_unused_aib70[10], iopad_unused_aib69[10], iopad_unused_aib68[10],
iopad_unused_aib67[10], iopad_unused_aib66[10], iopad_ns_adapter_rstn[10], iopad_unused_aib64[10],
iopad_unused_aib63[10], iopad_unused_aib62[10], iopad_unused_aib61[10], iopad_unused_aib60[10],
iopad_ns_rcv_clkb[10], iopad_unused_aib58[10], iopad_ns_rcv_clk[10], iopad_fs_adapter_rstn[10],
iopad_fs_rcv_div2_clkb[10], iopad_fs_fwd_div2_clkb[10], iopad_fs_fwd_div2_clk[10], iopad_unused_aib52[10],
iopad_unused_aib51[10], iopad_unused_aib50[10], iopad_fs_mac_rdy[10], iopad_fs_rcv_div2_clk[10],
iopad_unused_aib47[10], iopad_unused_aib46[10], iopad_unused_aib45[10], iopad_ns_mac_rdy[10],
iopad_ns_fwd_clk[10], iopad_ns_fwd_clkb[10], iopad_fs_fwd_clk[10], iopad_fs_fwd_clkb[10],
iopad_tx[219:200], iopad_rx[219:200]}),
.s1_ch5_aib( { iopad_fs_sr_data[11], iopad_fs_sr_load[11], iopad_ns_sr_data[11], iopad_ns_sr_load[11],
iopad_unused_aib91[11], iopad_unused_aib90[11], iopad_unused_aib89[11], iopad_unused_aib88[11],
iopad_fs_rcv_clk[11], iopad_fs_rcv_clkb[11], iopad_fs_sr_clk[11], iopad_fs_sr_clkb[11],
iopad_ns_sr_clk[11], iopad_ns_sr_clkb[11], iopad_unused_aib81[11], iopad_unused_aib80[11],
iopad_unused_aib79[11], iopad_unused_aib78[11], iopad_unused_aib77[11], iopad_unused_aib76[11],
iopad_unused_aib75[11], iopad_unused_aib74[11], iopad_unused_aib73[11], iopad_unused_aib72[11],
iopad_unused_aib71[11], iopad_unused_aib70[11], iopad_unused_aib69[11], iopad_unused_aib68[11],
iopad_unused_aib67[11], iopad_unused_aib66[11], iopad_ns_adapter_rstn[11], iopad_unused_aib64[11],
iopad_unused_aib63[11], iopad_unused_aib62[11], iopad_unused_aib61[11], iopad_unused_aib60[11],
iopad_ns_rcv_clkb[11], iopad_unused_aib58[11], iopad_ns_rcv_clk[11], iopad_fs_adapter_rstn[11],
iopad_fs_rcv_div2_clkb[11], iopad_fs_fwd_div2_clkb[11], iopad_fs_fwd_div2_clk[11], iopad_unused_aib52[11],
iopad_unused_aib51[11], iopad_unused_aib50[11], iopad_fs_mac_rdy[11], iopad_fs_rcv_div2_clk[11],
iopad_unused_aib47[11], iopad_unused_aib46[11], iopad_unused_aib45[11], iopad_ns_mac_rdy[11],
iopad_ns_fwd_clk[11], iopad_ns_fwd_clkb[11], iopad_fs_fwd_clk[11], iopad_fs_fwd_clkb[11],
iopad_tx[239:220], iopad_rx[239:220]}),
.s2_ch0_aib( { iopad_fs_sr_data[12], iopad_fs_sr_load[12], iopad_ns_sr_data[12], iopad_ns_sr_load[12],
iopad_unused_aib91[12], iopad_unused_aib90[12], iopad_unused_aib89[12], iopad_unused_aib88[12],
iopad_fs_rcv_clk[12], iopad_fs_rcv_clkb[12], iopad_fs_sr_clk[12], iopad_fs_sr_clkb[12],
iopad_ns_sr_clk[12], iopad_ns_sr_clkb[12], iopad_unused_aib81[12], iopad_unused_aib80[12],
iopad_unused_aib79[12], iopad_unused_aib78[12], iopad_unused_aib77[12], iopad_unused_aib76[12],
iopad_unused_aib75[12], iopad_unused_aib74[12], iopad_unused_aib73[12], iopad_unused_aib72[12],
iopad_unused_aib71[12], iopad_unused_aib70[12], iopad_unused_aib69[12], iopad_unused_aib68[12],
iopad_unused_aib67[12], iopad_unused_aib66[12], iopad_ns_adapter_rstn[12], iopad_unused_aib64[12],
iopad_unused_aib63[12], iopad_unused_aib62[12], iopad_unused_aib61[12], iopad_unused_aib60[12],
iopad_ns_rcv_clkb[12], iopad_unused_aib58[12], iopad_ns_rcv_clk[12], iopad_fs_adapter_rstn[12],
iopad_fs_rcv_div2_clkb[12], iopad_fs_fwd_div2_clkb[12], iopad_fs_fwd_div2_clk[12], iopad_unused_aib52[12],
iopad_unused_aib51[12], iopad_unused_aib50[12], iopad_fs_mac_rdy[12], iopad_fs_rcv_div2_clk[12],
iopad_unused_aib47[12], iopad_unused_aib46[12], iopad_unused_aib45[12], iopad_ns_mac_rdy[12],
iopad_ns_fwd_clk[12], iopad_ns_fwd_clkb[12], iopad_fs_fwd_clk[12], iopad_fs_fwd_clkb[12],
iopad_tx[259:240], iopad_rx[259:240]}),
.s2_ch1_aib( { iopad_fs_sr_data[13], iopad_fs_sr_load[13], iopad_ns_sr_data[13], iopad_ns_sr_load[13],
iopad_unused_aib91[13], iopad_unused_aib90[13], iopad_unused_aib89[13], iopad_unused_aib88[13],
iopad_fs_rcv_clk[13], iopad_fs_rcv_clkb[13], iopad_fs_sr_clk[13], iopad_fs_sr_clkb[13],
iopad_ns_sr_clk[13], iopad_ns_sr_clkb[13], iopad_unused_aib81[13], iopad_unused_aib80[13],
iopad_unused_aib79[13], iopad_unused_aib78[13], iopad_unused_aib77[13], iopad_unused_aib76[13],
iopad_unused_aib75[13], iopad_unused_aib74[13], iopad_unused_aib73[13], iopad_unused_aib72[13],
iopad_unused_aib71[13], iopad_unused_aib70[13], iopad_unused_aib69[13], iopad_unused_aib68[13],
iopad_unused_aib67[13], iopad_unused_aib66[13], iopad_ns_adapter_rstn[13], iopad_unused_aib64[13],
iopad_unused_aib63[13], iopad_unused_aib62[13], iopad_unused_aib61[13], iopad_unused_aib60[13],
iopad_ns_rcv_clkb[13], iopad_unused_aib58[13], iopad_ns_rcv_clk[13], iopad_fs_adapter_rstn[13],
iopad_fs_rcv_div2_clkb[13], iopad_fs_fwd_div2_clkb[13], iopad_fs_fwd_div2_clk[13], iopad_unused_aib52[13],
iopad_unused_aib51[13], iopad_unused_aib50[13], iopad_fs_mac_rdy[13], iopad_fs_rcv_div2_clk[13],
iopad_unused_aib47[13], iopad_unused_aib46[13], iopad_unused_aib45[13], iopad_ns_mac_rdy[13],
iopad_ns_fwd_clk[13], iopad_ns_fwd_clkb[13], iopad_fs_fwd_clk[13], iopad_fs_fwd_clkb[13],
iopad_tx[279:260], iopad_rx[279:260]}),
.s2_ch2_aib( { iopad_fs_sr_data[14], iopad_fs_sr_load[14], iopad_ns_sr_data[14], iopad_ns_sr_load[14],
iopad_unused_aib91[14], iopad_unused_aib90[14], iopad_unused_aib89[14], iopad_unused_aib88[14],
iopad_fs_rcv_clk[14], iopad_fs_rcv_clkb[14], iopad_fs_sr_clk[14], iopad_fs_sr_clkb[14],
iopad_ns_sr_clk[14], iopad_ns_sr_clkb[14], iopad_unused_aib81[14], iopad_unused_aib80[14],
iopad_unused_aib79[14], iopad_unused_aib78[14], iopad_unused_aib77[14], iopad_unused_aib76[14],
iopad_unused_aib75[14], iopad_unused_aib74[14], iopad_unused_aib73[14], iopad_unused_aib72[14],
iopad_unused_aib71[14], iopad_unused_aib70[14], iopad_unused_aib69[14], iopad_unused_aib68[14],
iopad_unused_aib67[14], iopad_unused_aib66[14], iopad_ns_adapter_rstn[14], iopad_unused_aib64[14],
iopad_unused_aib63[14], iopad_unused_aib62[14], iopad_unused_aib61[14], iopad_unused_aib60[14],
iopad_ns_rcv_clkb[14], iopad_unused_aib58[14], iopad_ns_rcv_clk[14], iopad_fs_adapter_rstn[14],
iopad_fs_rcv_div2_clkb[14], iopad_fs_fwd_div2_clkb[14], iopad_fs_fwd_div2_clk[14], iopad_unused_aib52[14],
iopad_unused_aib51[14], iopad_unused_aib50[14], iopad_fs_mac_rdy[14], iopad_fs_rcv_div2_clk[14],
iopad_unused_aib47[14], iopad_unused_aib46[14], iopad_unused_aib45[14], iopad_ns_mac_rdy[14],
iopad_ns_fwd_clk[14], iopad_ns_fwd_clkb[14], iopad_fs_fwd_clk[14], iopad_fs_fwd_clkb[14],
iopad_tx[299:280], iopad_rx[299:280]}),
.s2_ch3_aib( { iopad_fs_sr_data[15], iopad_fs_sr_load[15], iopad_ns_sr_data[15], iopad_ns_sr_load[15],
iopad_unused_aib91[15], iopad_unused_aib90[15], iopad_unused_aib89[15], iopad_unused_aib88[15],
iopad_fs_rcv_clk[15], iopad_fs_rcv_clkb[15], iopad_fs_sr_clk[15], iopad_fs_sr_clkb[15],
iopad_ns_sr_clk[15], iopad_ns_sr_clkb[15], iopad_unused_aib81[15], iopad_unused_aib80[15],
iopad_unused_aib79[15], iopad_unused_aib78[15], iopad_unused_aib77[15], iopad_unused_aib76[15],
iopad_unused_aib75[15], iopad_unused_aib74[15], iopad_unused_aib73[15], iopad_unused_aib72[15],
iopad_unused_aib71[15], iopad_unused_aib70[15], iopad_unused_aib69[15], iopad_unused_aib68[15],
iopad_unused_aib67[15], iopad_unused_aib66[15], iopad_ns_adapter_rstn[15], iopad_unused_aib64[15],
iopad_unused_aib63[15], iopad_unused_aib62[15], iopad_unused_aib61[15], iopad_unused_aib60[15],
iopad_ns_rcv_clkb[15], iopad_unused_aib58[15], iopad_ns_rcv_clk[15], iopad_fs_adapter_rstn[15],
iopad_fs_rcv_div2_clkb[15], iopad_fs_fwd_div2_clkb[15], iopad_fs_fwd_div2_clk[15], iopad_unused_aib52[15],
iopad_unused_aib51[15], iopad_unused_aib50[15], iopad_fs_mac_rdy[15], iopad_fs_rcv_div2_clk[15],
iopad_unused_aib47[15], iopad_unused_aib46[15], iopad_unused_aib45[15], iopad_ns_mac_rdy[15],
iopad_ns_fwd_clk[15], iopad_ns_fwd_clkb[15], iopad_fs_fwd_clk[15], iopad_fs_fwd_clkb[15],
iopad_tx[319:300], iopad_rx[319:300]}),
.s2_ch4_aib( { iopad_fs_sr_data[16], iopad_fs_sr_load[16], iopad_ns_sr_data[16], iopad_ns_sr_load[16],
iopad_unused_aib91[16], iopad_unused_aib90[16], iopad_unused_aib89[16], iopad_unused_aib88[16],
iopad_fs_rcv_clk[16], iopad_fs_rcv_clkb[16], iopad_fs_sr_clk[16], iopad_fs_sr_clkb[16],
iopad_ns_sr_clk[16], iopad_ns_sr_clkb[16], iopad_unused_aib81[16], iopad_unused_aib80[16],
iopad_unused_aib79[16], iopad_unused_aib78[16], iopad_unused_aib77[16], iopad_unused_aib76[16],
iopad_unused_aib75[16], iopad_unused_aib74[16], iopad_unused_aib73[16], iopad_unused_aib72[16],
iopad_unused_aib71[16], iopad_unused_aib70[16], iopad_unused_aib69[16], iopad_unused_aib68[16],
iopad_unused_aib67[16], iopad_unused_aib66[16], iopad_ns_adapter_rstn[16], iopad_unused_aib64[16],
iopad_unused_aib63[16], iopad_unused_aib62[16], iopad_unused_aib61[16], iopad_unused_aib60[16],
iopad_ns_rcv_clkb[16], iopad_unused_aib58[16], iopad_ns_rcv_clk[16], iopad_fs_adapter_rstn[16],
iopad_fs_rcv_div2_clkb[16], iopad_fs_fwd_div2_clkb[16], iopad_fs_fwd_div2_clk[16], iopad_unused_aib52[16],
iopad_unused_aib51[16], iopad_unused_aib50[16], iopad_fs_mac_rdy[16], iopad_fs_rcv_div2_clk[16],
iopad_unused_aib47[16], iopad_unused_aib46[16], iopad_unused_aib45[16], iopad_ns_mac_rdy[16],
iopad_ns_fwd_clk[16], iopad_ns_fwd_clkb[16], iopad_fs_fwd_clk[16], iopad_fs_fwd_clkb[16],
iopad_tx[339:320], iopad_rx[339:320]}),
.s2_ch5_aib( { iopad_fs_sr_data[17], iopad_fs_sr_load[17], iopad_ns_sr_data[17], iopad_ns_sr_load[17],
iopad_unused_aib91[17], iopad_unused_aib90[17], iopad_unused_aib89[17], iopad_unused_aib88[17],
iopad_fs_rcv_clk[17], iopad_fs_rcv_clkb[17], iopad_fs_sr_clk[17], iopad_fs_sr_clkb[17],
iopad_ns_sr_clk[17], iopad_ns_sr_clkb[17], iopad_unused_aib81[17], iopad_unused_aib80[17],
iopad_unused_aib79[17], iopad_unused_aib78[17], iopad_unused_aib77[17], iopad_unused_aib76[17],
iopad_unused_aib75[17], iopad_unused_aib74[17], iopad_unused_aib73[17], iopad_unused_aib72[17],
iopad_unused_aib71[17], iopad_unused_aib70[17], iopad_unused_aib69[17], iopad_unused_aib68[17],
iopad_unused_aib67[17], iopad_unused_aib66[17], iopad_ns_adapter_rstn[17], iopad_unused_aib64[17],
iopad_unused_aib63[17], iopad_unused_aib62[17], iopad_unused_aib61[17], iopad_unused_aib60[17],
iopad_ns_rcv_clkb[17], iopad_unused_aib58[17], iopad_ns_rcv_clk[17], iopad_fs_adapter_rstn[17],
iopad_fs_rcv_div2_clkb[17], iopad_fs_fwd_div2_clkb[17], iopad_fs_fwd_div2_clk[17], iopad_unused_aib52[17],
iopad_unused_aib51[17], iopad_unused_aib50[17], iopad_fs_mac_rdy[17], iopad_fs_rcv_div2_clk[17],
iopad_unused_aib47[17], iopad_unused_aib46[17], iopad_unused_aib45[17], iopad_ns_mac_rdy[17],
iopad_ns_fwd_clk[17], iopad_ns_fwd_clkb[17], iopad_fs_fwd_clk[17], iopad_fs_fwd_clkb[17],
iopad_tx[359:340], iopad_rx[359:340]}),
.s3_ch0_aib( { iopad_fs_sr_data[18], iopad_fs_sr_load[18], iopad_ns_sr_data[18], iopad_ns_sr_load[18],
iopad_unused_aib91[18], iopad_unused_aib90[18], iopad_unused_aib89[18], iopad_unused_aib88[18],
iopad_fs_rcv_clk[18], iopad_fs_rcv_clkb[18], iopad_fs_sr_clk[18], iopad_fs_sr_clkb[18],
iopad_ns_sr_clk[18], iopad_ns_sr_clkb[18], iopad_unused_aib81[18], iopad_unused_aib80[18],
iopad_unused_aib79[18], iopad_unused_aib78[18], iopad_unused_aib77[18], iopad_unused_aib76[18],
iopad_unused_aib75[18], iopad_unused_aib74[18], iopad_unused_aib73[18], iopad_unused_aib72[18],
iopad_unused_aib71[18], iopad_unused_aib70[18], iopad_unused_aib69[18], iopad_unused_aib68[18],
iopad_unused_aib67[18], iopad_unused_aib66[18], iopad_ns_adapter_rstn[18], iopad_unused_aib64[18],
iopad_unused_aib63[18], iopad_unused_aib62[18], iopad_unused_aib61[18], iopad_unused_aib60[18],
iopad_ns_rcv_clkb[18], iopad_unused_aib58[18], iopad_ns_rcv_clk[18], iopad_fs_adapter_rstn[18],
iopad_fs_rcv_div2_clkb[18], iopad_fs_fwd_div2_clkb[18], iopad_fs_fwd_div2_clk[18], iopad_unused_aib52[18],
iopad_unused_aib51[18], iopad_unused_aib50[18], iopad_fs_mac_rdy[18], iopad_fs_rcv_div2_clk[18],
iopad_unused_aib47[18], iopad_unused_aib46[18], iopad_unused_aib45[18], iopad_ns_mac_rdy[18],
iopad_ns_fwd_clk[18], iopad_ns_fwd_clkb[18], iopad_fs_fwd_clk[18], iopad_fs_fwd_clkb[18],
iopad_tx[379:360], iopad_rx[379:360]}),
.s3_ch1_aib( { iopad_fs_sr_data[19], iopad_fs_sr_load[19], iopad_ns_sr_data[19], iopad_ns_sr_load[19],
iopad_unused_aib91[19], iopad_unused_aib90[19], iopad_unused_aib89[19], iopad_unused_aib88[19],
iopad_fs_rcv_clk[19], iopad_fs_rcv_clkb[19], iopad_fs_sr_clk[19], iopad_fs_sr_clkb[19],
iopad_ns_sr_clk[19], iopad_ns_sr_clkb[19], iopad_unused_aib81[19], iopad_unused_aib80[19],
iopad_unused_aib79[19], iopad_unused_aib78[19], iopad_unused_aib77[19], iopad_unused_aib76[19],
iopad_unused_aib75[19], iopad_unused_aib74[19], iopad_unused_aib73[19], iopad_unused_aib72[19],
iopad_unused_aib71[19], iopad_unused_aib70[19], iopad_unused_aib69[19], iopad_unused_aib68[19],
iopad_unused_aib67[19], iopad_unused_aib66[19], iopad_ns_adapter_rstn[19], iopad_unused_aib64[19],
iopad_unused_aib63[19], iopad_unused_aib62[19], iopad_unused_aib61[19], iopad_unused_aib60[19],
iopad_ns_rcv_clkb[19], iopad_unused_aib58[19], iopad_ns_rcv_clk[19], iopad_fs_adapter_rstn[19],
iopad_fs_rcv_div2_clkb[19], iopad_fs_fwd_div2_clkb[19], iopad_fs_fwd_div2_clk[19], iopad_unused_aib52[19],
iopad_unused_aib51[19], iopad_unused_aib50[19], iopad_fs_mac_rdy[19], iopad_fs_rcv_div2_clk[19],
iopad_unused_aib47[19], iopad_unused_aib46[19], iopad_unused_aib45[19], iopad_ns_mac_rdy[19],
iopad_ns_fwd_clk[19], iopad_ns_fwd_clkb[19], iopad_fs_fwd_clk[19], iopad_fs_fwd_clkb[19],
iopad_tx[399:380], iopad_rx[399:380]}),
.s3_ch2_aib( { iopad_fs_sr_data[20], iopad_fs_sr_load[20], iopad_ns_sr_data[20], iopad_ns_sr_load[20],
iopad_unused_aib91[20], iopad_unused_aib90[20], iopad_unused_aib89[20], iopad_unused_aib88[20],
iopad_fs_rcv_clk[20], iopad_fs_rcv_clkb[20], iopad_fs_sr_clk[20], iopad_fs_sr_clkb[20],
iopad_ns_sr_clk[20], iopad_ns_sr_clkb[20], iopad_unused_aib81[20], iopad_unused_aib80[20],
iopad_unused_aib79[20], iopad_unused_aib78[20], iopad_unused_aib77[20], iopad_unused_aib76[20],
iopad_unused_aib75[20], iopad_unused_aib74[20], iopad_unused_aib73[20], iopad_unused_aib72[20],
iopad_unused_aib71[20], iopad_unused_aib70[20], iopad_unused_aib69[20], iopad_unused_aib68[20],
iopad_unused_aib67[20], iopad_unused_aib66[20], iopad_ns_adapter_rstn[20], iopad_unused_aib64[20],
iopad_unused_aib63[20], iopad_unused_aib62[20], iopad_unused_aib61[20], iopad_unused_aib60[20],
iopad_ns_rcv_clkb[20], iopad_unused_aib58[20], iopad_ns_rcv_clk[20], iopad_fs_adapter_rstn[20],
iopad_fs_rcv_div2_clkb[20], iopad_fs_fwd_div2_clkb[20], iopad_fs_fwd_div2_clk[20], iopad_unused_aib52[20],
iopad_unused_aib51[20], iopad_unused_aib50[20], iopad_fs_mac_rdy[20], iopad_fs_rcv_div2_clk[20],
iopad_unused_aib47[20], iopad_unused_aib46[20], iopad_unused_aib45[20], iopad_ns_mac_rdy[20],
iopad_ns_fwd_clk[20], iopad_ns_fwd_clkb[20], iopad_fs_fwd_clk[20], iopad_fs_fwd_clkb[20],
iopad_tx[419:400], iopad_rx[419:400]}),
.s3_ch3_aib( { iopad_fs_sr_data[21], iopad_fs_sr_load[21], iopad_ns_sr_data[21], iopad_ns_sr_load[21],
iopad_unused_aib91[21], iopad_unused_aib90[21], iopad_unused_aib89[21], iopad_unused_aib88[21],
iopad_fs_rcv_clk[21], iopad_fs_rcv_clkb[21], iopad_fs_sr_clk[21], iopad_fs_sr_clkb[21],
iopad_ns_sr_clk[21], iopad_ns_sr_clkb[21], iopad_unused_aib81[21], iopad_unused_aib80[21],
iopad_unused_aib79[21], iopad_unused_aib78[21], iopad_unused_aib77[21], iopad_unused_aib76[21],
iopad_unused_aib75[21], iopad_unused_aib74[21], iopad_unused_aib73[21], iopad_unused_aib72[21],
iopad_unused_aib71[21], iopad_unused_aib70[21], iopad_unused_aib69[21], iopad_unused_aib68[21],
iopad_unused_aib67[21], iopad_unused_aib66[21], iopad_ns_adapter_rstn[21], iopad_unused_aib64[21],
iopad_unused_aib63[21], iopad_unused_aib62[21], iopad_unused_aib61[21], iopad_unused_aib60[21],
iopad_ns_rcv_clkb[21], iopad_unused_aib58[21], iopad_ns_rcv_clk[21], iopad_fs_adapter_rstn[21],
iopad_fs_rcv_div2_clkb[21], iopad_fs_fwd_div2_clkb[21], iopad_fs_fwd_div2_clk[21], iopad_unused_aib52[21],
iopad_unused_aib51[21], iopad_unused_aib50[21], iopad_fs_mac_rdy[21], iopad_fs_rcv_div2_clk[21],
iopad_unused_aib47[21], iopad_unused_aib46[21], iopad_unused_aib45[21], iopad_ns_mac_rdy[21],
iopad_ns_fwd_clk[21], iopad_ns_fwd_clkb[21], iopad_fs_fwd_clk[21], iopad_fs_fwd_clkb[21],
iopad_tx[439:420], iopad_rx[439:420]}),
.s3_ch4_aib( { iopad_fs_sr_data[22], iopad_fs_sr_load[22], iopad_ns_sr_data[22], iopad_ns_sr_load[22],
iopad_unused_aib91[22], iopad_unused_aib90[22], iopad_unused_aib89[22], iopad_unused_aib88[22],
iopad_fs_rcv_clk[22], iopad_fs_rcv_clkb[22], iopad_fs_sr_clk[22], iopad_fs_sr_clkb[22],
iopad_ns_sr_clk[22], iopad_ns_sr_clkb[22], iopad_unused_aib81[22], iopad_unused_aib80[22],
iopad_unused_aib79[22], iopad_unused_aib78[22], iopad_unused_aib77[22], iopad_unused_aib76[22],
iopad_unused_aib75[22], iopad_unused_aib74[22], iopad_unused_aib73[22], iopad_unused_aib72[22],
iopad_unused_aib71[22], iopad_unused_aib70[22], iopad_unused_aib69[22], iopad_unused_aib68[22],
iopad_unused_aib67[22], iopad_unused_aib66[22], iopad_ns_adapter_rstn[22], iopad_unused_aib64[22],
iopad_unused_aib63[22], iopad_unused_aib62[22], iopad_unused_aib61[22], iopad_unused_aib60[22],
iopad_ns_rcv_clkb[22], iopad_unused_aib58[22], iopad_ns_rcv_clk[22], iopad_fs_adapter_rstn[22],
iopad_fs_rcv_div2_clkb[22], iopad_fs_fwd_div2_clkb[22], iopad_fs_fwd_div2_clk[22], iopad_unused_aib52[22],
iopad_unused_aib51[22], iopad_unused_aib50[22], iopad_fs_mac_rdy[22], iopad_fs_rcv_div2_clk[22],
iopad_unused_aib47[22], iopad_unused_aib46[22], iopad_unused_aib45[22], iopad_ns_mac_rdy[22],
iopad_ns_fwd_clk[22], iopad_ns_fwd_clkb[22], iopad_fs_fwd_clk[22], iopad_fs_fwd_clkb[22],
iopad_tx[459:440], iopad_rx[459:440]}),
.s3_ch5_aib( { iopad_fs_sr_data[23], iopad_fs_sr_load[23], iopad_ns_sr_data[23], iopad_ns_sr_load[23],
iopad_unused_aib91[23], iopad_unused_aib90[23], iopad_unused_aib89[23], iopad_unused_aib88[23],
iopad_fs_rcv_clk[23], iopad_fs_rcv_clkb[23], iopad_fs_sr_clk[23], iopad_fs_sr_clkb[23],
iopad_ns_sr_clk[23], iopad_ns_sr_clkb[23], iopad_unused_aib81[23], iopad_unused_aib80[23],
iopad_unused_aib79[23], iopad_unused_aib78[23], iopad_unused_aib77[23], iopad_unused_aib76[23],
iopad_unused_aib75[23], iopad_unused_aib74[23], iopad_unused_aib73[23], iopad_unused_aib72[23],
iopad_unused_aib71[23], iopad_unused_aib70[23], iopad_unused_aib69[23], iopad_unused_aib68[23],
iopad_unused_aib67[23], iopad_unused_aib66[23], iopad_ns_adapter_rstn[23], iopad_unused_aib64[23],
iopad_unused_aib63[23], iopad_unused_aib62[23], iopad_unused_aib61[23], iopad_unused_aib60[23],
iopad_ns_rcv_clkb[23], iopad_unused_aib58[23], iopad_ns_rcv_clk[23], iopad_fs_adapter_rstn[23],
iopad_fs_rcv_div2_clkb[23], iopad_fs_fwd_div2_clkb[23], iopad_fs_fwd_div2_clk[23], iopad_unused_aib52[23],
iopad_unused_aib51[23], iopad_unused_aib50[23], iopad_fs_mac_rdy[23], iopad_fs_rcv_div2_clk[23],
iopad_unused_aib47[23], iopad_unused_aib46[23], iopad_unused_aib45[23], iopad_ns_mac_rdy[23],
iopad_ns_fwd_clk[23], iopad_ns_fwd_clkb[23], iopad_fs_fwd_clk[23], iopad_fs_fwd_clkb[23],
iopad_tx[479:460], iopad_rx[479:460]}),
.device_detect (device_detect),
.por (por),
.i_osc_clk (i_osc_clk),
// .o_aibaux_osc_clk (o_aibaux_osc_clk),
.scan_clk (scan_clk),
.scan_enable (scan_enable),
// .scan_in (scan_in),
.scan_in_ch0 (scan_in_ch0),
.scan_in_ch1 (scan_in_ch1),
.scan_in_ch2 (scan_in_ch2),
.scan_in_ch3 (scan_in_ch3),
.scan_in_ch4 (scan_in_ch4),
.scan_in_ch5 (scan_in_ch5),
.scan_in_ch6 (scan_in_ch6),
.scan_in_ch7 (scan_in_ch7),
.scan_in_ch8 (scan_in_ch8),
.scan_in_ch9 (scan_in_ch9),
.scan_in_ch10 (scan_in_ch10),
.scan_in_ch11 (scan_in_ch11),
.scan_in_ch12 (scan_in_ch12),
.scan_in_ch13 (scan_in_ch13),
.scan_in_ch14 (scan_in_ch14),
.scan_in_ch15 (scan_in_ch15),
.scan_in_ch16 (scan_in_ch16),
.scan_in_ch17 (scan_in_ch17),
.scan_in_ch18 (scan_in_ch18),
.scan_in_ch19 (scan_in_ch19),
.scan_in_ch20 (scan_in_ch20),
.scan_in_ch21 (scan_in_ch21),
.scan_in_ch22 (scan_in_ch22),
.scan_in_ch23 (scan_in_ch23),
// .scan_out (scan_out),
.scan_out_ch0 (scan_out_ch0),
.scan_out_ch1 (scan_out_ch1),
.scan_out_ch2 (scan_out_ch2),
.scan_out_ch3 (scan_out_ch3),
.scan_out_ch4 (scan_out_ch4),
.scan_out_ch5 (scan_out_ch5),
.scan_out_ch6 (scan_out_ch6),
.scan_out_ch7 (scan_out_ch7),
.scan_out_ch8 (scan_out_ch8),
.scan_out_ch9 (scan_out_ch9),
.scan_out_ch10 (scan_out_ch10),
.scan_out_ch11 (scan_out_ch11),
.scan_out_ch12 (scan_out_ch12),
.scan_out_ch13 (scan_out_ch13),
.scan_out_ch14 (scan_out_ch14),
.scan_out_ch15 (scan_out_ch15),
.scan_out_ch16 (scan_out_ch16),
.scan_out_ch17 (scan_out_ch17),
.scan_out_ch18 (scan_out_ch18),
.scan_out_ch19 (scan_out_ch19),
.scan_out_ch20 (scan_out_ch20),
.scan_out_ch21 (scan_out_ch21),
.scan_out_ch22 (scan_out_ch22),
.scan_out_ch23 (scan_out_ch23),
.i_scan_clk (i_scan_clk),
.i_test_scan_en (i_test_scan_en),
.i_test_scan_mode (i_test_scan_mode),
// .i_test_clk_125m (i_test_clk_125m),
// .i_test_clk_1g (i_test_clk_1g),
// .i_test_clk_250m (i_test_clk_250m),
// .i_test_clk_500m (i_test_clk_500m),
// .i_test_clk_62m (i_test_clk_62m),
// .i_test_c3adapt_scan_in (i_test_c3adapt_scan_in),
// .o_test_c3adapt_scan_out (o_test_c3adapt_scan_out),
.i_jtag_clkdr (i_jtag_clkdr),
.i_jtag_clksel (i_jtag_clksel),
.i_jtag_intest (i_jtag_intest),
.i_jtag_mode (i_jtag_mode),
.i_jtag_rstb_en (i_jtag_rstb_en),
.i_jtag_rstb (i_jtag_rstb),
.i_jtag_weakpdn (i_jtag_weakpdn),
.i_jtag_weakpu (i_jtag_weakpu),
.i_jtag_tdi (i_jtag_tdi),
.i_jtag_tx_scanen (i_jtag_tx_scanen),
.o_jtag_tdo (o_jtag_tdo)
);
endmodule |
module c3lib_sync3_reset_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b0),
.SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_set_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow (1),
.ResetVal (1'b1),
.SyncRegWidth (2)
) u_c3lib_sync2_reset_ulvt_gate (
.clk ( clk ),
.rst_in ( rst_n ),
.data_in (data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_set_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b1),
.SyncRegWidth(2)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in ( rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync2_reset_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
//
// );
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b0),
.SyncRegWidth(2)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_sync3_set_ulvt_gate (
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ( rst_n ),
// .data_in ( data_in ),
// .data_out ( data_out )
data_sync_for_aib # (
.ActiveLow(1),
.ResetVal(1'b1),
.SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_in (rst_n ),
.data_in(data_in),
.data_out ( data_out )
);
endmodule |
module c3lib_ckg_lvt_8x(
tst_en,
clk_en,
clk,
gated_clk
);
input wire tst_en;
input wire clk_en;
input wire clk;
output wire gated_clk;
`ifdef BEHAVIORAL
var logic latch_d;
var logic latch_q;
// Formulate control signal
assign latch_d = clk_en | tst_en;
// Latch control signal
always_latch if (~clk) latch_q <= latch_d;
// Actual clk gating gate
assign gated_clk = clk & latch_q;
`else
b15cilb01ah1n08x5 icg_cell (.clkout(gated_clk), .en(clk_en), .te(tst_en), .clk(clk));
`endif
endmodule |
module c3lib_ckinv_svt_8x(
in,
out
);
input in;
output out;
`ifdef BEHAVIORAL
assign out = ~in;
`else
clock_inv u_clock_inv (.out(out), .in(in));
`endif
endmodule |
module aibio_clkdist_inv1_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;
localparam delay_2 = 49.55;
`else
localparam delay_1 = 0.0;
localparam delay_2 = 0.0;
`endif
assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;
assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;
/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/
endmodule |
module aibio_rxclk_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input [4:0] dcc_p_pdsel,
input [4:0] dcc_p_pusel,
input [4:0] dcc_n_pdsel,
input [4:0] dcc_n_pusel,
input rxclkp,
input rxclkn,
input rxclk_en,
input rxclk_localbias_en,
input ipbias,
input [2:0] ibias_ctrl,
input gen1mode_en,
//------Output pins------//
output rxclkp_out,
output rxclkn_out,
//------Spare pins------//
input [3:0] i_rxclk_spare,
output [3:0] o_rxclk_spare
);
wire rxclkp_out_1;
wire rxclkp_out_2;
wire rxclkp_out_3;
wire rxclkn_out_1;
wire rxclkn_out_2;
wire rxclkn_out_3;
`ifdef POST_WORST
localparam delay_rxclkp_out_1 = 150;
localparam delay_rxclkp_out_2 = 5;
localparam delay_rxclkn_out_1 = 150;
localparam delay_rxclkn_out_2 = 3;
`else
localparam delay_rxclkp_out_1 = 0.0;
localparam delay_rxclkp_out_2 = 0.0;
localparam delay_rxclkn_out_1 = 0.0;
localparam delay_rxclkn_out_2 = 0.0;
`endif
assign #(delay_rxclkp_out_1)rxclkp_out_1 = rxclk_en ? rxclkp : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_2 = rxclk_en ? rxclkp_out_1 : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_3 = rxclk_en ? rxclkp_out_2 : 1'b0;
assign #(delay_rxclkp_out_2)rxclkp_out = rxclk_en ? rxclkp_out_3 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_1 = rxclk_en ? rxclkn : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_2 = rxclk_en ? rxclkn_out_1 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_3 = rxclk_en ? rxclkn_out_2 : 1'b0;
assign #(delay_rxclkn_out_2)rxclkn_out = rxclk_en ? rxclkn_out_3 : 1'b0;
endmodule |
module aibio_clkdist_inv2_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;
localparam delay_2 = 16.5;
`else
localparam delay_1 = 0.0;
localparam delay_2 = 0.0;
`endif
assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;
assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;
/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/
endmodule |
module aibio_outclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [3:0]i_adapter_code,
input [3:0]i_soc_code,
//--------Output pins---------//
output o_clk_adapter,
output o_clk_soc
);
assign o_clk_adapter = ~ i_clkphb[i_adapter_code];
assign o_clk_soc = ~ i_clkphb[i_soc_code];
endmodule |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vddc,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_clksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_code,
input [3:0] dll_ckadapter_code,
input [3:0] dll_even_phase1_sel,
input [3:0] dll_odd_phase1_sel,
input [3:0] dll_even_phase2_sel,
input [3:0] dll_odd_phase2_sel,
input [3:0] dll_lockthresh,
input [1:0] dll_lockctrl,
input pwrgood_in,
input dll_dfx_en,
input [4:0] dll_digview_sel,
input [4:0] dll_anaview_sel,
//------Output pins------//
output dll_lock,
output clk_odd,
output clk_even,
output clk_soc,
output clk_adapter,
output pulseclk_odd,
output pulseclk_even,
output inbias,
output ipbias,
output [1:0] dll_digviewout,
output dll_anaviewout,
//------Spare pins------//
input [7:0] i_dll_spare,
output [7:0] o_dll_spare
);
wire clkp,clkn;
wire up,dn,upb,dnb;
wire [15:0]clkphb;
wire dll_enb;
assign dll_enb= ~dll_en;
aibio_inpclk_select_txdll inpclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clk_in(ck_in),
.i_clk_loopback(ck_loopback),
.i_clk_sys(ck_sys),
.i_clk_jtag(ck_jtag),
.i_clksel(inp_clksel),
.o_clkp(clkp),
.o_clkn(clkn)
);
aibio_dll_top dll_top
(
.vddcq(vddcq),
.vss(vss),
.i_clkp(clkp),
.i_clkn(clkn),
.i_clkp_cdr(),
.i_clkn_cdr(),
.i_dll_biasctrl(dll_biasctrl),
.i_dll_capctrl(dll_capctrl),
.i_dll_en(dll_en),
.i_dll_enb(dll_enb),
.o_up(up),
.o_dn(dn),
.o_upb(upb),
.o_dnb(dnb),
.o_dll_clkphb(clkphb),
.o_piclk_180(),
.o_piclk_90(),
.o_cdr_clk(),
.o_pbias(),
.o_nbias()
);
aibio_lock_detector lock_detector
(
.vddcq(vddcq),
.vss(vss),
.i_clkin(ck_sys),
.i_en(dll_en),
.i_up(up),
.i_dn(dn),
.i_upb(upb),
.i_dnb(dnb),
.i_lockthresh(dll_lockthresh[1:0]),
.i_lockctrl(dll_lockctrl),
.lock(dll_lock)
);
aibio_pulsegen_top pulsegen
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(clkphb),
.i_dll_even_phase1_sel(dll_even_phase1_sel),
.i_dll_odd_phase1_sel(dll_odd_phase1_sel),
.i_dll_even_phase2_sel(dll_even_phase2_sel),
.i_dll_odd_phase2_sel(dll_odd_phase2_sel),
.o_clk_even(clk_even),
.o_clk_odd(clk_odd),
.o_pulseclk_even(pulseclk_even),
.o_pulseclk_odd(pulseclk_odd)
);
aibio_outclk_select outclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_adapter_code(dll_ckadapter_code),
.i_soc_code(dll_cksoc_code),
.o_clk_adapter(clk_adapter),
.o_clk_soc(clk_soc)
);
endmodule |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;
assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;
assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;
assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;
assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
(i_clksel == 2'b01) ? i_clk_loopbackp :
(i_clksel == 2'b10) ? i_clk_sysp :
(i_clksel == 2'b11) ? i_clk_jtagp :
1'b0;
assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
(i_clksel == 2'b01) ? i_clk_loopbackn :
(i_clksel == 2'b10) ? i_clk_sysn :
(i_clksel == 2'b11) ? i_clk_jtagn :
1'b0;
endmodule |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkph,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output pins-----------//
output o_clk_even,
output o_clk_odd,
output o_pulseclk_even,
output o_pulseclk_odd
);
wire [3:0]dll_even_phase2_sel_int;
wire [3:0]dll_odd_phase2_sel_int;
wire dll_even_phase2_selb_3;
wire dll_odd_phase2_selb_3;
assign dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign dll_even_phase2_sel_int = {dll_even_phase2_selb_3,i_dll_even_phase2_sel[2:0]};
assign dll_odd_phase2_sel_int = {dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[2:0]};
assign o_clk_even = ~i_clkph[i_dll_even_phase1_sel];
assign o_clk_odd = ~i_clkph[i_dll_odd_phase1_sel];
assign o_pulseclk_even = o_clk_even && (i_clkph[dll_even_phase2_sel_int]);
assign o_pulseclk_odd = o_clk_odd && (i_clkph[dll_odd_phase2_sel_int]);
endmodule |
module aibio_vref_cbb
(
//------Supply pins------//
input vddc,
input vddtx,
inout vss,
//------Input pins------//
input vref_en,
input calvref_en,
input [6:0] vref_bin_0,
input [6:0] vref_bin_1,
input [6:0] vref_bin_2,
input [6:0] vref_bin_3,
input [4:0] calvref_bin,
input gen1mode_en,
input pwrgood_in,
//------Output pins------//
output [3:0] vref,
output calvref,
//------Spare pins------//
input [3:0] i_vref_spare,
output [3:0] o_vref_spare
);
endmodule |
module en_logic_xxpad
(
input data,
input pwrgoodtx,
input pwrgood,
input rst_strap,
input wk_pu_en,
input wk_pd_en,
input compen_n,
input compen_p,
input tx_en,
input sdr_mode_en,
input tx_async_en,
input gen1_en,
output reg pu_en_gen1,
output reg pd_en_gen1,
output reg pu_en_gen2,
output reg pd_en_gen2,
output reg wkpd_en,
output reg wkpu_en
);
wire pg;
wire compen;
wire wk_en;
assign pg = (pwrgoodtx && pwrgood);
assign compen = (compen_p ^ compen_n);
assign wk_en = (wk_pu_en ^ wk_pd_en);
always @(rst_strap,pg,wk_en,compen,tx_en,sdr_mode_en,tx_async_en,gen1_en,data)
begin
if(rst_strap) //reset
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b1;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(!pg) //pwrgoodtx and pwrgood invalid
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(wk_en)
begin
if(wk_pu_en) //Weak PULL-UP
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b1;
end
else if(wk_pd_en) //Weak PULL-DOWN
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b1;
wkpu_en = 1'b0;
end
end
else if(compen)
begin
if(compen_n) //rcomp_n
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b1;
pd_en_gen2 = 1'b1;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(compen_p) //rcomp_p
begin
pu_en_gen1 = 1'b1;
pd_en_gen1 = 1'b1;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
end
else if(tx_async_en) //Async mode(Assumption ---> gen1_en is high): data here is async data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(!tx_en) //No Mode: Both tx_async_en & tx_en is low
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else if(tx_en) //tx_en : high
begin
if(sdr_mode_en) //SDR Mode(Assumption ---> gen1_en is high) : Here data is even data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else
begin
if(gen1_en) //GEN1 Mode : Here data is serialised data
begin
pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
pu_en_gen2 = 1'b0;
pd_en_gen2 = 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
else //GEN2 Mode : Here data is serialised data
begin
pu_en_gen1 = 1'b0;
pd_en_gen1 = 1'b0;
pu_en_gen2 = (data == 1'b1) ? 1'b1 : 1'b0;
pd_en_gen2 = (data == 1'b0) ? 1'b1 : 1'b0;
wkpd_en = 1'b0;
wkpu_en = 1'b0;
end
end
end
end
endmodule |
module pad_out_logic
(
input rst,
input pu_gen1,
input pd_gen1,
input pu_gen2,
input pd_gen2,
input wkpu,
input wkpd,
output reg data_out
);
always @(rst,wkpu,wkpd,pu_gen1,pd_gen1,pu_gen2,pd_gen2)
begin
if(rst)
begin
data_out = 1'b0;
end
else if(wkpu)
begin
data_out = 1'b1;
end
else if(wkpd)
begin
data_out = 1'b0;
end
else if(pu_gen1 && pd_gen1)
begin
data_out = 1'bx;
end
else if(pu_gen2 && pd_gen2)
begin
data_out = 1'bx;
end
else if(pu_gen1 ^ pd_gen1)
begin
data_out = pu_gen1;
end
else if(pu_gen2 ^ pd_gen2)
begin
data_out = pu_gen2;
end
else
begin
data_out = 1'bz;
end
end
endmodule |
module aibio_pvtmon_3to8dec(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [2:0]sel,
//----Output pins----//
output logic [7:0]out
);
always @(sel)
begin
case(sel)
3'b000 : out=8'b0000_0001;
3'b001 : out=8'b0000_0010;
3'b010 : out=8'b0000_0100;
3'b011 : out=8'b0000_1000;
3'b100 : out=8'b0001_0000;
3'b101 : out=8'b0010_0000;
3'b110 : out=8'b0100_0000;
3'b111 : out=8'b1000_0000;
default : out = 8'b0000_0000;
endcase
end
endmodule |
module mux2x1 (
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [1:0]in,
input logic s,
//----Output pins----//
output logic out
);
always @(in or s)
begin
if(s)
out= in[1];
else
out=in[0];
end
endmodule |
module DFF(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic clk,
input logic rb,
input logic d,
//----Output pins----//
output logic o
);
initial o <= 0;
always @(posedge clk or negedge rb )
begin
if(rb == 1'b0)
begin
o = 'd0;
end
else
begin
o = d;
end
end
endmodule |
module aibio_decoder3x8
(
//---------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [2:0] i,
//--------Output pins---------//
output reg [7:0] o
);
always @(i)
case(i)
3'b000 : o = 8'b0000_0001;
3'b001 : o = 8'b0000_0010;
3'b010 : o = 8'b0000_0100;
3'b011 : o = 8'b0000_1000;
3'b100 : o = 8'b0001_0000;
3'b101 : o = 8'b0010_0000;
3'b110 : o = 8'b0100_0000;
3'b111 : o = 8'b1000_0000;
default : o = 8'b0000_0000;
endcase
endmodule |
module aibio_decoder2x4
(
//----------Supply pins------------//
input vddcq,
input vss,
//----------Input pins------------//
input [1:0] i,
//----------Output pins----------//
output reg [3:0] o
);
always @(i)
case(i)
2'b00 : o = 4'b0001;
2'b01 : o = 4'b0010;
2'b10 : o = 4'b0100;
2'b11 : o = 4'b1000;
default : o = 4'b0000;
endcase
endmodule |
module aibio_outclk_mux16x1
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkph,
input [3:0]i_clksel,
//--------Output pins---------//
output o_clk
);
wire [3:0] clk_sel_stg1;
wire [3:0] clk_sel_stg2;
wire [3:0] clkphsel_stg2;
aibio_decoder2x4 I4
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel[1:0]),
.o(clk_sel_stg1)
);
aibio_decoder2x4 I3
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel[3:2]),
.o(clk_sel_stg2)
);
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[3:0]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[0])
);
aibio_pimux4x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[7:4]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[1])
);
aibio_pimux4x1 I2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[11:8]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[2])
);
aibio_pimux4x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph[15:12]),
.i_clkph_sel(clk_sel_stg1),
.o_clkph(clkphsel_stg2[3])
);
aibio_pimux4x1 I5
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(clkphsel_stg2),
.i_clkph_sel(clk_sel_stg2),
.o_clkph(o_clk)
);
endmodule |
module aibio_pimux4x1
(
//----------Supply pins----------//
input vddcq,
input vss,
//---------Input pins-----------//
input [3:0]i_clkph,
input [3:0]i_clkph_sel,
//---------Output pins----------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 4'b0001) ? i_clkph[0] :
(i_clkph_sel == 4'b0010) ? i_clkph[1] :
(i_clkph_sel == 4'b0100) ? i_clkph[2] :
(i_clkph_sel == 4'b1000) ? i_clkph[3] :
1'b0;
endmodule |
module aibio_clock_dist
(
//---------Supply pins------------//
input vddcq,
input vss,
//---------Input pins------------//
input i_piclk_even_in,
input i_piclk_odd_in,
input i_loopback_en,
//---------Output pins----------//
output o_piclk_even_loopback,
output o_piclk_odd_loopback
);
assign o_piclk_even_loopback = i_loopback_en ? i_piclk_even_in : 1'b0;
assign o_piclk_odd_loopback = i_loopback_en ? i_piclk_odd_in : 1'b0;
endmodule |
module aibio_outclk_select
(
//----------Supply pins-----------//
input vddcq,
input vss,
//----------Input pins-----------//
input [3:0] i_adapter_code,
input [3:0] i_soc_code,
input [15:0] i_clkphb,
//----------Output pins-----------//
output o_clk_adapter,
output o_clk_soc
);
wire clk_adapter_b;
wire clk_soc_b;
aibio_outclk_mux16x1 Adapater_MUX
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb),
.i_clksel(i_adapter_code),
.o_clk(clk_adapter_b)
);
aibio_outclk_mux16x1 SOC_MUX
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb),
.i_clksel(i_soc_code),
.o_clk(clk_soc_b)
);
assign o_clk_adapter = ~clk_adapter_b;
assign o_clk_soc = ~clk_soc_b;
endmodule |
module aibio_se_to_diff
(
input vddcq,
input vss,
input i,
output o,
output o_b
);
assign o = i;
assign o_b = ~i;
endmodule |
module aibio_auxch_Schmit_trigger
(
//-------Supply pins----------//
input vddc,
input vss,
//-------Input pin-----------//
input vin,
//-------Output pin---------//
output vout
);
assign vout=vin;
endmodule |
module aibio_auxch_cbb
(
//----supply pins----//
input vddc,
input vss,
//-----input pins-------------//
input dual_mode_sel,
input i_m_power_on_reset,
input m_por_ovrd,
input m_device_detect_ovrd,
input [2:0]rxbuf_cfg,
input powergood,
input gen1mode_en,
//-----inout pins-----------------//
inout xx_power_on_reset,
inout xx_device_detect,
//-------output pins--------------//
output o_m_power_on_reset,
output m_device_detect,
//--------spare pins---------------//
input [3:0]i_aux_spare,
output [3:0]o_aux_spare
);
wire net016;
wire net017;
wire net09;
wire net028;
wire net023;
wire net013;
wire vin1;
wire vin2;
assign net013 = ~i_m_power_on_reset;
assign net09 = ~ dual_mode_sel;
assign net028 = ~net09;
assign net023 = ~vddc;
assign o_m_power_on_reset = (m_por_ovrd & net016);
assign m_device_detect = (net017 | m_device_detect_ovrd);
assign xx_power_on_reset = (net09)? ~net013 : 1'hz;
assign xx_device_detect = (net028) ? ~net023 :1'hz;
assign vin1 = xx_power_on_reset;
assign vin2 = xx_device_detect;
aibio_auxch_Schmit_trigger schmit_trigger1
(
.vddc(vddc),
.vss(vss),
.vin(vin1),
.vout(net016)
);
aibio_auxch_Schmit_trigger schmit_trigger2
(
.vddc(vddc),
.vss(vss),
.vin(vin2),
.vout(net017)
);
endmodule |
module aibio_pulsegen_phsel_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0]i_clkph,
input [2:0]i_ph1sel,
input [2:0]i_ph2sel,
//--------Output pins---------//
output o_clkph1,
output o_clkph2
);
aibio_pulsegen_mux8x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_clksel(i_ph1sel),
.o_clkph(o_clkph1)
);
aibio_pulsegen_mux8x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_clksel(i_ph2sel),
.o_clkph(o_clkph2)
);
endmodule |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
/*
wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;
assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;
assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;
assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;
assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
(i_clksel == 2'b01) ? i_clk_loopbackp :
(i_clksel == 2'b10) ? i_clk_sysp :
(i_clksel == 2'b11) ? i_clk_jtagp :
1'b0;
assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
(i_clksel == 2'b01) ? i_clk_loopbackn :
(i_clksel == 2'b10) ? i_clk_sysn :
(i_clksel == 2'b11) ? i_clk_jtagn :
1'b0;
*/
wire o_clk;
wire [3:0]clksel_decoded;
aibio_decoder2x4 I5
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clksel_decoded)
);
aibio_pimux4x1 MUX_clkp
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtag,i_clk_sys,i_clk_loopback,i_clk_in}),
.o_clkph(o_clk)
);
aibio_se_to_diff se_diff_1
(
.vddcq(vddcq),
.vss(vss),
.i(o_clk),
.o(o_clkp),
.o_b(o_clkn)
);
endmodule |
module aibio_pulsegen_muxfinal
(
//-------Supply pins--------//
input vddcq,
input vss,
//-------Input pins--------//
input [1:0]i_clkph1_even,
input [1:0]i_clkph1_odd,
input [1:0]i_clkph1_sel_even,
input [1:0]i_clkph1_sel_odd,
input [1:0]i_clkph2_even,
input [1:0]i_clkph2_odd,
input [1:0]i_clkph2_sel_even,
input [1:0]i_clkph2_sel_odd,
//-------Output pins---------//
output clk_out_even,
output clk_out_odd,
output pulse_out_even,
output pulse_out_odd
);
wire clkph1b_even;
wire clkph2b_even;
wire clkph1b_odd;
wire clkph2b_odd;
wire clkph2_odd;
wire clkph2_even;
aibio_pulsegen_mux2x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph1_even),
.i_clkph_sel(i_clkph1_sel_even),
.o_clkph(clkph1b_even)
);
aibio_pulsegen_mux2x1 I1
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph2_even),
.i_clkph_sel(i_clkph2_sel_even),
.o_clkph(clkph2b_even)
);
aibio_pulsegen_mux2x1 I3
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph2_odd),
.i_clkph_sel(i_clkph2_sel_odd),
.o_clkph(clkph2b_odd)
);
aibio_pulsegen_mux2x1 I4
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph1_odd),
.i_clkph_sel(i_clkph1_sel_odd),
.o_clkph(clkph1b_odd)
);
assign clk_out_even = ~clkph1b_even;
assign clk_out_odd = ~clkph1b_odd;
assign clkph2_odd = ~clkph2b_odd;
assign clkph2_even = ~clkph2b_even;
assign pulse_out_even = clk_out_even && clkph2_even;
assign pulse_out_odd = clk_out_odd && clkph2_odd;
endmodule |
module aibio_pulsegen_oddevn_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [7:0]i_clkph,
input [2:0]i_evn_ph1_sel,
input [2:0]i_evn_ph2_sel,
input [2:0]i_odd_ph1_sel,
input [2:0]i_odd_ph2_sel,
//--------Output pins-----------//
output o_clkph1_evn,
output o_clkph1_odd,
output o_clkph2_evn,
output o_clkph2_odd
);
aibio_pulsegen_phsel_halfside odd_ph1ph2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_ph1sel(i_odd_ph1_sel),
.i_ph2sel(i_odd_ph2_sel),
.o_clkph1(o_clkph1_odd),
.o_clkph2(o_clkph2_odd)
);
aibio_pulsegen_phsel_halfside evn_ph1ph2
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkph),
.i_ph1sel(i_evn_ph1_sel),
.i_ph2sel(i_evn_ph2_sel),
.o_clkph1(o_clkph1_evn),
.o_clkph2(o_clkph2_evn)
);
endmodule |
module aibio_pulsegen_mux8x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [7:0] i_clkph,
input [2:0] i_clksel,
//-------Output pins---------//
output wor o_clkph
// output o_clkph //For LEC comment above line and uncomment this line
);
wire [7:0] clk_sel;
//wor o_clkph; //For LEC comment this line
aibio_decoder3x8 I1
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clk_sel)
);
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph({i_clkph[3],i_clkph[2],i_clkph[1],i_clkph[0]}),
.i_clkph_sel({clk_sel[3],clk_sel[2],clk_sel[1],clk_sel[0]}),
.o_clkph(o_clkph)
);
aibio_pimux4x1 I0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph({i_clkph[7],i_clkph[6],i_clkph[5],i_clkph[4]}),
.i_clkph_sel({clk_sel[7],clk_sel[6],clk_sel[5],clk_sel[4]}),
.o_clkph(o_clkph)
);
//assign o_clkph = o_clkph_int1 || o_clkph_int2 ;
endmodule |
module aibio_pulsegen_mux2x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [1:0] i_clkph,
input [1:0] i_clkph_sel,
//-------Output pins--------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 2'b01) ? i_clkph[0] :
(i_clkph_sel == 2'b10) ? i_clkph[1] :
1'b0;
endmodule |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_cksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_code,
input [3:0] dll_ckadapter_code,
input [3:0] dll_even_phase1_sel,
input [3:0] dll_odd_phase1_sel,
input [3:0] dll_even_phase2_sel,
input [3:0] dll_odd_phase2_sel,
input [3:0] dll_lockthresh,
input [1:0] dll_lockctrl,
input loopback_en,
input pwrgood_in,
input dll_dfx_en,
input [4:0] dll_digview_sel,
input [4:0] dll_anaview_sel,
//------Output pins------//
output dll_lock,
output clk_odd,
output clk_even,
output clk_soc,
output clk_adapter,
output pulseclk_odd,
output pulseclk_even,
output pulseclk_odd_loopback,
output pulseclk_even_loopback,
output inbias,
output [3:0] ipbias,
output [1:0] dll_digviewout,
output dll_anaviewout,
//------Spare pins------//
input [7:0] i_dll_spare,
output [7:0] o_dll_spare
);
wire clkp,clkn;
wire up,dn,upb,dnb;
wire [15:0]clkphb;
wire dll_lock_en;
wire jtag_en;
wire dll_en_int;
wire dll_enb_int;
wire dll_clk_inp;
wire dll_clk_inn;
wire pulseclk_odd_int;
wire pulseclk_even_int;
wire clk_adapter_int;
wire clk_soc_int;
assign dll_en_int = dll_en & pwrgood_in;
assign dll_enb_int= ~dll_en_int;
`ifdef POST_WORST
localparam delay_inpclk_select = 80.73;
localparam delay_pulsegen = 132;
localparam delay_outclk_select = 114.96;
`else
localparam delay_inpclk_select = 0.0;
localparam delay_pulsegen = 0.0;
localparam delay_outclk_select = 0.0;
`endif
aibio_inpclk_select_txdll inpclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clk_in(ck_in),
.i_clk_loopback(ck_loopback),
.i_clk_sys(ck_sys),
.i_clk_jtag(ck_jtag),
.i_clksel(inp_cksel),
.o_clkp(clkp),
.o_clkn(clkn)
);
assign #(delay_inpclk_select) dll_clk_inp = clkp;
assign #(delay_inpclk_select) dll_clk_inn = clkn;
aibio_dll_top dll_top
(
.vddcq(vddcq),
.vss(vss),
.i_clkp(dll_clk_inp),
.i_clkn(dll_clk_inn),
.i_clkp_cdr(),
.i_clkn_cdr(),
.i_dll_biasctrl(dll_biasctrl),
.i_dll_capctrl(dll_capctrl),
.i_dll_en(dll_en_int),
.i_dll_enb(dll_enb_int),
.i_reset(dll_reset),
.i_jtag_en(jtag_en),
.o_up(up),
.o_dn(dn),
.o_upb(upb),
.o_dnb(dnb),
.o_dll_clkphb(clkphb),
.o_piclk_180(),
.o_piclk_90(),
.o_cdr_clk(),
.o_pbias(),
.o_nbias(),
.ph_diff()
);
aibio_lock_detector lock_detector
(
.vddcq(vddcq),
.vss(vss),
.i_clkin(ck_sys),
.i_up(up),
.i_dn(dn),
.i_upb(upb),
.i_dnb(dnb),
.i_reset(dll_reset),
.i_lockthresh(dll_lockthresh[1:0]),
.i_lockctrl(dll_lockctrl),
.o_dll_lock(dll_lock)
);
aibio_pulsegen_top pulsegen
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_dll_even_phase1_sel(dll_even_phase1_sel),
.i_dll_odd_phase1_sel(dll_odd_phase1_sel),
.i_dll_even_phase2_sel(dll_even_phase2_sel),
.i_dll_odd_phase2_sel(dll_odd_phase2_sel),
.o_clk_even(),
.o_clk_odd(),
.o_pulseclk_even(pulseclk_even_int),
.o_pulseclk_odd(pulseclk_odd_int)
);
aibio_clock_dist piclk_dist
(
.vddcq(vddcq),
.vss(vss),
.i_piclk_even_in(pulseclk_even),
.i_piclk_odd_in(pulseclk_odd),
.i_loopback_en(loopback_en),
.o_piclk_even_loopback(pulseclk_even_loopback),
.o_piclk_odd_loopback(pulseclk_odd_loopback)
);
aibio_outclk_select outclk_select
(
.vddcq(vddcq),
.vss(vss),
.i_clkphb(clkphb),
.i_adapter_code(dll_ckadapter_code),
.i_soc_code(dll_cksoc_code),
.o_clk_adapter(clk_adapter_int),
.o_clk_soc(clk_soc_int)
);
assign jtag_en = inp_cksel[1] && inp_cksel[0] ;
assign #(delay_pulsegen) pulseclk_even = pulseclk_even_int;
assign #(delay_pulsegen) pulseclk_odd = pulseclk_odd_int;
assign #(delay_outclk_select) clk_soc = clk_soc_int;
assign #(delay_outclk_select) clk_adapter = clk_adapter_int;
endmodule |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkphb,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output pins-----------//
output o_clk_even,
output o_clk_odd,
output o_pulseclk_even,
output o_pulseclk_odd
);
wire [1:0]clkph1_even;
wire [1:0]clkph2_even;
wire [1:0]clkph1_odd;
wire [1:0]clkph2_odd;
wire i_dll_odd_phase1_selb_3;
wire i_dll_even_phase1_selb_3;
wire i_dll_odd_phase2_selb_3;
wire i_dll_even_phase2_selb_3;
assign i_dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign i_dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign i_dll_odd_phase1_selb_3 = ~i_dll_odd_phase1_sel[3];
assign i_dll_even_phase1_selb_3 = ~i_dll_even_phase1_sel[3];
aibio_pulsegen_oddevn_halfside phsel_LSB
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb[7:0]),
.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
.o_clkph1_evn(clkph1_even[0]),
.o_clkph1_odd(clkph1_odd[0]),
.o_clkph2_evn(clkph2_even[0]),
.o_clkph2_odd(clkph2_odd[0])
);
aibio_pulsegen_oddevn_halfside phsel_MSB
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clkphb[15:8]),
.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
.o_clkph1_evn(clkph1_even[1]),
.o_clkph1_odd(clkph1_odd[1]),
.o_clkph2_evn(clkph2_even[1]),
.o_clkph2_odd(clkph2_odd[1])
);
aibio_pulsegen_muxfinal muxfinal
(
.vddcq(vddcq),
.vss(vss),
.i_clkph1_even(clkph1_even),
.i_clkph1_odd(clkph1_odd),
.i_clkph1_sel_even({i_dll_even_phase1_sel[3],i_dll_even_phase1_selb_3}),
.i_clkph1_sel_odd({i_dll_odd_phase1_sel[3],i_dll_odd_phase1_selb_3}),
.i_clkph2_even(clkph2_even),
.i_clkph2_odd(clkph2_odd),
.i_clkph2_sel_even({i_dll_even_phase2_selb_3,i_dll_even_phase2_sel[3]}),
.i_clkph2_sel_odd({i_dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[3]}),
.clk_out_even(o_clk_even),
.clk_out_odd(o_clk_odd),
.pulse_out_even(o_pulseclk_even),
.pulse_out_odd(o_pulseclk_odd)
);
endmodule |
module aibio_pioddevn_top
(
//--------Supply pins-----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [7:0]i_picode_evn,
input [7:0]i_picode_odd,
input i_pbias,
input i_nbias,
input [2:0]i_bias_trim,
input [1:0]i_capsel,
input [1:0]i_capselb,
input i_clken,
input i_pien,
input i_reset,
input i_update,
input real ph_diff,
//-------Output pins-----------//
output o_clkpi_evn,
output o_clkpi_odd
);
//--------Internal signals----------//
wire [2:0]pbias_trim;
wire [2:0]nbias_trim;
wire clkph_0;
wire clkph_1;
wire clkph_2;
wire clkph_3;
wire clkph_4;
wire clkph_5;
wire clkph_6;
wire clkph_7;
wire clkph_8;
wire clkph_9;
wire clkph_10;
wire clkph_11;
wire clkph_12;
wire clkph_13;
wire clkph_14;
wire clkph_15;
wire [7:0]clkphsel_stg1_odd;
wire [7:0]clkphsel_stg1_evn;
wire [1:0]clkphsel_stg2_odd;
wire [1:0]clkphsel_stg2_evn;
wire [7:0]pixer_odd;
wire [7:0]pixer_evn;
wire [1:0]phsel_stg2_b_odd;
wire [1:0]phsel_stg2_b_evn;
wire [1:0]phsel_stg2_bb_odd;
wire [1:0]phsel_stg2_bb_evn;
wire clkevn_evn;
wire clkevn_odd;
wire clkodd_evn;
wire clkodd_odd;
assign clkph_0 = ~i_clkphb[0];
assign clkph_1 = ~i_clkphb[1];
assign clkph_2 = ~i_clkphb[2];
assign clkph_3 = ~i_clkphb[3];
assign clkph_4 = ~i_clkphb[4];
assign clkph_5 = ~i_clkphb[5];
assign clkph_6 = ~i_clkphb[6];
assign clkph_7 = ~i_clkphb[7];
assign clkph_8 = ~i_clkphb[8];
assign clkph_9 = ~i_clkphb[9];
assign clkph_10 = ~i_clkphb[10];
assign clkph_11 = ~i_clkphb[11];
assign clkph_12 = ~i_clkphb[12];
assign clkph_13 = ~i_clkphb[13];
assign clkph_14 = ~i_clkphb[14];
assign clkph_15 = ~i_clkphb[15];
assign phsel_stg2_b_odd[0] = ~(clkphsel_stg2_odd[0] && i_pien);
assign phsel_stg2_b_odd[1] = ~(clkphsel_stg2_odd[1] && i_pien);
assign phsel_stg2_bb_odd[0] = ~phsel_stg2_b_odd[0];
assign phsel_stg2_bb_odd[1] = ~phsel_stg2_b_odd[1];
assign phsel_stg2_b_evn[0] = ~(clkphsel_stg2_evn[0] && i_pien);
assign phsel_stg2_b_evn[1] = ~(clkphsel_stg2_evn[1] && i_pien);
assign phsel_stg2_bb_evn[0] = ~phsel_stg2_b_evn[0];
assign phsel_stg2_bb_evn[1] = ~phsel_stg2_b_evn[1];
aibio_bias_trim I2
(
.vddcq(vddcq),
.vss(vss),
.i_bias_trim(i_bias_trim),
.i_pbias(i_pbias),
.i_nbias(i_nbias),
.o_pbias_trim(pbias_trim),
.o_nbias_trim(nbias_trim)
);
aibio_pi_decode_sync odd_decode_sync
(
.vddcq(vddcq),
.vss(vss),
.i_clk_en(i_clken),
.i_clk_sync(o_clkpi_odd),
.i_picode(i_picode_odd),
.i_reset(i_reset),
.i_update(i_update),
.o_clkphsel_stg1_synced(clkphsel_stg1_odd),
.o_clkphsel_stg2_synced(clkphsel_stg2_odd),
.o_pimixer_synced(pixer_odd)
);
aibio_pi_decode_sync evn_decode_sync
(
.vddcq(vddcq),
.vss(vss),
.i_clk_en(i_clken),
.i_clk_sync(o_clkpi_evn),
.i_picode(i_picode_evn),
.i_reset(i_reset),
.i_update(i_update),
.o_clkphsel_stg1_synced(clkphsel_stg1_evn),
.o_clkphsel_stg2_synced(clkphsel_stg2_evn),
.o_pimixer_synced(pixer_evn)
);
aibio_pioddevn_phsel_half phsel_oddevn_LSB
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_capsel),
.i_cap_selb(i_capselb),
.i_clk_evnph({clkph_6,clkph_4,clkph_2,clkph_0}),
.i_clk_evnphsel_stg1_evn({clkphsel_stg1_evn[6],clkphsel_stg1_evn[4],clkphsel_stg1_evn[2],clkphsel_stg1_evn[0]}),
.i_clk_evnphsel_stg1_odd({clkphsel_stg1_odd[6],clkphsel_stg1_odd[4],clkphsel_stg1_odd[2],clkphsel_stg1_odd[0]}),
.i_clk_evnphsel_stg2_evn(phsel_stg2_b_evn[0]),
.i_clk_evnphsel_stg2_odd(phsel_stg2_b_odd[0]),
.i_clk_oddph({clkph_7,clkph_5,clkph_3,clkph_1}),
.i_clk_oddphsel_stg1_evn({clkphsel_stg1_evn[7],clkphsel_stg1_evn[5],clkphsel_stg1_evn[3],clkphsel_stg1_evn[1]}),
.i_clk_oddphsel_stg1_odd({clkphsel_stg1_odd[7],clkphsel_stg1_odd[5],clkphsel_stg1_odd[3],clkphsel_stg1_odd[1]}),
.i_clk_oddphsel_stg2_evn(phsel_stg2_b_evn[1]),
.i_clk_oddphsel_stg2_odd(phsel_stg2_b_odd[1]),
.i_nbias(i_nbias),
.i_nbias_trim(nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(pbias_trim),
.o_clk_evnph_evn(clkevn_evn),
.o_clk_evnph_odd(clkevn_odd),
.o_clk_oddph_evn(clkodd_evn),
.o_clk_oddph_odd(clkodd_odd)
);
aibio_pioddevn_phsel_half phsel_oddevn_MSB
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_capsel),
.i_cap_selb(i_capselb),
.i_clk_evnph({clkph_14,clkph_12,clkph_10,clkph_8}),
.i_clk_evnphsel_stg1_evn({clkphsel_stg1_evn[6],clkphsel_stg1_evn[4],clkphsel_stg1_evn[2],clkphsel_stg1_evn[0]}),
.i_clk_evnphsel_stg1_odd({clkphsel_stg1_odd[6],clkphsel_stg1_odd[4],clkphsel_stg1_odd[2],clkphsel_stg1_odd[0]}),
.i_clk_evnphsel_stg2_evn(phsel_stg2_bb_evn[0]),
.i_clk_evnphsel_stg2_odd(phsel_stg2_bb_odd[0]),
.i_clk_oddph({clkph_15,clkph_13,clkph_11,clkph_9}),
.i_clk_oddphsel_stg1_evn({clkphsel_stg1_evn[7],clkphsel_stg1_evn[5],clkphsel_stg1_evn[3],clkphsel_stg1_evn[1]}),
.i_clk_oddphsel_stg1_odd({clkphsel_stg1_odd[7],clkphsel_stg1_odd[5],clkphsel_stg1_odd[3],clkphsel_stg1_odd[1]}),
.i_clk_oddphsel_stg2_evn(phsel_stg2_bb_evn[1]),
.i_clk_oddphsel_stg2_odd(phsel_stg2_bb_odd[1]),
.i_nbias(i_nbias),
.i_nbias_trim(nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(pbias_trim),
.o_clk_evnph_evn(clkevn_evn),
.o_clk_evnph_odd(clkevn_odd),
.o_clk_oddph_evn(clkodd_evn),
.o_clk_oddph_odd(clkodd_odd)
);
aibio_pioddevn_mixer_top oddevn_mixer
(
.vddcq(vddcq),
.vss(vss),
.i_clkevn_evn(clkevn_evn),
.i_clkevn_odd(clkevn_odd),
.i_clkodd_evn(clkodd_evn),
.i_clkodd_odd(clkodd_odd),
.i_pien(i_pien),
.i_pimixer_evn(pixer_evn),
.i_pimixer_odd(pixer_odd),
.i_clkph({clkph_15,clkph_14,clkph_13,clkph_12,clkph_11,clkph_10,clkph_9,clkph_8,clkph_7,clkph_6,clkph_5,clkph_4,clkph_3,clkph_2,clkph_1,clkph_0}),
.i_pievn_code(i_picode_evn),
.i_piodd_code(i_picode_odd),
.ph_diff(ph_diff),
.o_clk_evn(o_clkpi_evn),
.o_clk_odd(o_clkpi_odd)
);
endmodule |
module aibio_pi_decode_sync
(
//---------Supply pins--------//
input vddcq,
input vss,
//---------Input pins----------//
input i_clk_en,
input i_clk_sync,
input [7:0] i_picode,
input i_reset,
input i_update,
//---------Output pins---------//
output [7:0] o_clkphsel_stg1_synced,
output [1:0] o_clkphsel_stg2_synced,
output [7:0] o_pimixer_synced
);
wire [7:0] clkphsel_stg1;
wire [1:0] clkphsel_stg2;
wire [7:0] pimixer;
aibio_pi_decode I1
(
.vddcq(vddcq),
.vss(vss),
.i_picode(i_picode),
.o_clkphsel_stg1(clkphsel_stg1),
.o_clkphsel_stg2(clkphsel_stg2),
.o_pimixer(pimixer)
);
aibio_pi_codeupdate I2
(
.vddcq(vddcq),
.vss(vss),
.i_clk(i_clk_sync),
.i_clk_en(i_clk_en),
.i_clkphsel_stg1(clkphsel_stg1),
.i_clkphsel_stg2(clkphsel_stg2),
.i_pimixer(pimixer),
.i_update(i_update),
.i_reset(i_reset),
.o_clkphsel_stg1(o_clkphsel_stg1_synced),
.o_clkphsel_stg2(o_clkphsel_stg2_synced),
.o_pimixer(o_pimixer_synced)
);
endmodule |
module aibio_pi_decode
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0] i_picode,
//--------Output pins----------//
output [7:0]o_clkphsel_stg1,
output [1:0]o_clkphsel_stg2,
output [7:0]o_pimixer
);
wire [3:0] picode_plus1;
wire mix_on;
wire [7:0] curr_code;
wire [7:0] next_code;
wire [7:1] therm;
wire [7:1] therm_b;
wire next_odd_en;
wire next_evn_en;
wire i_picode_b_3;
aibio_decoder3x8 I7
(
.vddcq(vddcq),
.vss(vss),
.i(i_picode[5:3]),
.o(curr_code)
);
aibio_decoder3x8 I6
(
.vddcq(vddcq),
.vss(vss),
.i(picode_plus1[2:0]),
.o(next_code)
);
aibio_3bit_bin_to_therm I3
(
.vddcq(vddcq),
.vss(vss),
.b(i_picode[2:0]),
.t(therm)
);
aibio_4bit_plus1 I4
(
.vddcq(vddcq),
.vss(vss),
.i_code(i_picode[6:3]),
.o_code(picode_plus1)
);
assign therm_b[7] = ~therm[7];
assign therm_b[6] = ~therm[6];
assign therm_b[5] = ~therm[5];
assign therm_b[4] = ~therm[4];
assign therm_b[3] = ~therm[3];
assign therm_b[2] = ~therm[2];
assign therm_b[1] = ~therm[1];
//assign mix_on = i_picode[2] || i_picode[1] || i_picode[0];
//assign next_evn_en = i_picode[3] && mix_on ;
assign next_evn_en = i_picode[3];
assign i_picode_b_3 = ~i_picode[3];
//assign next_odd_en = i_picode_b_3 && mix_on;
assign next_odd_en = i_picode_b_3;
assign o_clkphsel_stg2[0] = next_evn_en ? picode_plus1[3] : i_picode[6];
assign o_clkphsel_stg2[1] = next_odd_en ? picode_plus1[3] : i_picode[6];
assign o_clkphsel_stg1[6] = next_evn_en ? next_code[6] : curr_code[6];
assign o_clkphsel_stg1[4] = next_evn_en ? next_code[4] : curr_code[4];
assign o_clkphsel_stg1[2] = next_evn_en ? next_code[2] : curr_code[2];
assign o_clkphsel_stg1[0] = next_evn_en ? next_code[0] : curr_code[0];
assign o_clkphsel_stg1[7] = next_odd_en ? next_code[7] : curr_code[7];
assign o_clkphsel_stg1[5] = next_odd_en ? next_code[5] : curr_code[5];
assign o_clkphsel_stg1[3] = next_odd_en ? next_code[3] : curr_code[3];
assign o_clkphsel_stg1[1] = next_odd_en ? next_code[1] : curr_code[1];
assign o_pimixer[7] = i_picode[3] ? therm_b[7] : therm[7];
assign o_pimixer[6] = i_picode[3] ? therm_b[6] : therm[6];
assign o_pimixer[5] = i_picode[3] ? therm_b[5] : therm[5];
assign o_pimixer[4] = i_picode[3] ? therm_b[4] : therm[4];
assign o_pimixer[3] = i_picode[3] ? therm_b[3] : therm[3];
assign o_pimixer[2] = i_picode[3] ? therm_b[2] : therm[2];
assign o_pimixer[1] = i_picode[3] ? therm_b[1] : therm[1];
assign o_pimixer[0] = i_picode[3];
endmodule |
module aibio_pioddevn_mixer_top
(
//--------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input i_clkevn_evn,
input i_clkevn_odd,
input i_clkodd_evn,
input i_clkodd_odd,
input i_pien,
input [7:0]i_pimixer_evn,
input [7:0]i_pimixer_odd,
input [15:0]i_clkph,
input [7:0]i_pievn_code,
input [7:0]i_piodd_code,
input real ph_diff,
//--------Output pins---------//
output o_clk_evn,
output o_clk_odd
);
wire odd_clk_mixer;
wire evn_clk_mixer;
wire odd_clk_mixerb;
wire evn_clk_mixerb;
wire out_ph_0_flag_evn;
wire out_ph_0_flag_odd;
wire out_ph_0_flag;
wire odd_clk_mixer_int;
wire evn_clk_mixer_int;
aibio_pi_mixer_top mixer_odd
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_evn(i_clkevn_odd),
.i_clkph_odd(i_clkodd_odd),
.i_oddph_en(i_pimixer_odd),
.i_pien(i_pien),
.i_clkph(i_clkph),
.i_picode(i_piodd_code),
.ph_diff(ph_diff),
.o_clkmix_out(odd_clk_mixer)
);
aibio_pi_mixer_top mixer_evn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_evn(i_clkevn_evn),
.i_clkph_odd(i_clkodd_evn),
.i_oddph_en(i_pimixer_evn),
.i_pien(i_pien),
.i_clkph(i_clkph),
.i_picode(i_pievn_code),
.ph_diff(ph_diff),
.o_clkmix_out(evn_clk_mixer)
);
assign evn_clk_mixerb = ~evn_clk_mixer;
assign o_clk_evn = ~evn_clk_mixerb;
assign odd_clk_mixerb = ~odd_clk_mixer;
assign o_clk_odd = ~odd_clk_mixerb;
endmodule |
module aibio_half_adder
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input a,
input b,
//------Output pins---------//
output c,
output s
);
assign s = a^b;
assign c = a&&b;
endmodule |
module aibio_pi_phsel_halfside
(
//---------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1,
input i_clk_evnphsel_stg2,
input [3:0]i_clk_oddph,
input [3:0]i_clk_oddphsel_stg1,
input i_clk_oddphsel_stg2,
input i_nbias,
input [2:0]i_nbias_trim,
input i_pbias,
input [2:0]i_pbias_trim,
//--------Output pins----------//
output o_clk_evnph,
output o_clk_oddph
);
aibio_pi_phsel_quarter phsel_mux_odd
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clk_oddph),
.i_clkphsel_stg1(i_clk_oddphsel_stg1),
.i_clkphsel_stg2(i_clk_oddphsel_stg2),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.o_clkph(o_clk_oddph)
);
aibio_pi_phsel_quarter phsel_mux_evn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph(i_clk_evnph),
.i_clkphsel_stg1(i_clk_evnphsel_stg1),
.i_clkphsel_stg2(i_clk_evnphsel_stg2),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.o_clkph(o_clk_evnph)
);
endmodule |
module aibio_4bit_plus1
(
//-------Supply pins------//
input vddcq,
input vss,
//-------Input pins--------//
input [3:0] i_code,
//-------Output pins-------//
output [3:0] o_code
);
wire net13;
wire net14;
wire net15;
wire net27;
aibio_half_adder I0
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[0]),
.b(1'b1),
.c(net13),
.s(o_code[0])
);
aibio_half_adder I1
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[1]),
.b(net13),
.c(net14),
.s(o_code[1])
);
aibio_half_adder I2
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[2]),
.b(net14),
.c(net15),
.s(o_code[2])
);
aibio_half_adder I3
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[3]),
.b(net15),
.c(net27),
.s(o_code[3])
);
endmodule |
module aibio_inpclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_inp,
input i_clk_inn,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input i_clk_cdr_inp,
input i_clk_cdr_inn,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn,
output o_cdr_clkp,
output o_cdr_clkn
);
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;
wire [3:0] clksel_decoded;
wire net016,net017,net018,net019;
aibio_se_to_diff se_diff_1
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_loopback),
.o(i_clk_loopbackp),
.o_b(i_clk_loopbackn)
);
aibio_se_to_diff I7
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_jtag),
.o(i_clk_jtagp),
.o_b(i_clk_jtagn)
);
aibio_se_to_diff se_diff_2
(
.vddcq(vddcq),
.vss(vss),
.i(i_clk_sys),
.o(i_clk_sysp),
.o_b(i_clk_sysn)
);
aibio_pimux4x1 MUX_dummy_p
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}), //TBD
.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inp}),
.o_clkph(net017)
);
aibio_pimux4x1 MUX_dummy_n
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}),
.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inn}),
.o_clkph(net016)
);
aibio_decoder2x4 I5
(
.vddcq(vddcq),
.vss(vss),
.i(i_clksel),
.o(clksel_decoded)
);
aibio_pimux4x1 MUX_clkp
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtagp,i_clk_sysp,i_clk_loopbackp,i_clk_inp}),
.o_clkph(net019)
);
aibio_pimux4x1 MUX_clkn
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(clksel_decoded),
.i_clkph({i_clk_jtagn,i_clk_sysn,i_clk_loopbackn,i_clk_inn}),
.o_clkph(net018)
);
/*
assign o_cdr_clkp = ~net017;
assign o_cdr_clkn = ~net016;
assign o_clkp = ~net019;
assign o_clkn = ~net018;
*/
assign o_cdr_clkp = net017;
assign o_cdr_clkn = net016;
assign o_clkp = net019;
assign o_clkn = net018;
endmodule |
module aibio_pi_phsel_quarter
(
//--------Supply pins-------------//
input vddcq,
input vss,
//--------Input pins-------------//
input [3:0] i_clkph,
input [3:0] i_clkphsel_stg1,
input i_clkphsel_stg2,
input i_pbias,
input [2:0] i_pbias_trim,
input i_nbias,
input [2:0] i_nbias_trim,
input [1:0] i_cap_sel,
input [1:0] i_cap_selb,
//---------Output pins------------//
output o_clkph
);
wire ph_MUX_out;
aibio_pimux4x1 MUX0
(
.vddcq(vddcq),
.vss(vss),
.i_clkph_sel(i_clkphsel_stg1),
.i_clkph(i_clkph),
.o_clkph(ph_MUX_out)
);
assign o_clkph = (i_clkphsel_stg2 == 1'b1) ? ph_MUX_out : 1'bz;
endmodule |
module aibio_pioddevn_phsel_half
(
//--------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1_evn,
input [3:0]i_clk_evnphsel_stg1_odd,
input i_clk_evnphsel_stg2_evn,
input i_clk_evnphsel_stg2_odd,
input [3:0]i_clk_oddph,
input [3:0]i_clk_oddphsel_stg1_evn,
input [3:0]i_clk_oddphsel_stg1_odd,
input i_clk_oddphsel_stg2_evn,
input i_clk_oddphsel_stg2_odd,
input i_nbias,
input [2:0] i_nbias_trim,
input i_pbias,
input [2:0]i_pbias_trim,
//---------Output pins-----------//
output o_clk_evnph_evn,
output o_clk_evnph_odd,
output o_clk_oddph_evn,
output o_clk_oddph_odd
);
aibio_pi_phsel_halfside oddclk_phselhalf
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.i_clk_evnph(i_clk_evnph),
.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_odd),
.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_odd),
.i_clk_oddph(i_clk_oddph),
.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_odd),
.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_odd),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.o_clk_evnph(o_clk_evnph_odd),
.o_clk_oddph(o_clk_oddph_odd)
);
aibio_pi_phsel_halfside evnclk_phselhalf
(
.vddcq(vddcq),
.vss(vss),
.i_cap_sel(i_cap_sel),
.i_cap_selb(i_cap_selb),
.i_clk_evnph(i_clk_evnph),
.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_evn),
.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_evn),
.i_clk_oddph(i_clk_oddph),
.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_evn),
.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_evn),
.i_nbias(i_nbias),
.i_nbias_trim(i_nbias_trim),
.i_pbias(i_pbias),
.i_pbias_trim(i_pbias_trim),
.o_clk_evnph(o_clk_evnph_evn),
.o_clk_oddph(o_clk_oddph_evn)
);
endmodule |
module aibio_cdr_detect
(
//----------Supply pins------------//
input vddcq,
input vss,
//---------Input pins--------------//
input i_cdr_clk,
input i_piclk_90,
input i_piclk_180,
input i_sdr_mode,
input i_reset,
//---------Output pins-------------//
output reg o_cdr_phdet
);
wire clk_int;
wire rstb;
assign rstb = ~i_reset;
assign clk_int = (i_sdr_mode) ? i_piclk_180 : i_piclk_90;
`ifdef POST_WORST
localparam t_setup = 0.0;
localparam t_hold = 0.0;
localparam t_clk2q = 0.0;
`else
localparam t_setup = 0.0;
localparam t_hold = 0.0;
localparam t_clk2q = 0.0;
`endif
sampler #(t_setup,t_hold,t_clk2q)
i_cdr_phdet
(
.data_in(i_cdr_clk),
.clk(clk_int),
.rst(rstb),
.data_out(o_cdr_phdet)
);
/*
always @(posedge clk_int or negedge rstb)
begin
if(!rstb)
begin
o_cdr_phdet <= 1'b0;
end
else
begin
o_cdr_phdet <= i_cdr_clk;
end
end
*/
endmodule |
module aibio_3bit_bin_to_therm
(
//--------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [2:0] b,
//-------Outptu pins---------//
output reg [6:0] t
);
always @(b)
case(b)
3'b000 : t = 7'b000_0000;
3'b001 : t = 7'b000_0001;
3'b010 : t = 7'b000_0011;
3'b011 : t = 7'b000_0111;
3'b100 : t = 7'b000_1111;
3'b101 : t = 7'b001_1111;
3'b110 : t = 7'b011_1111;
3'b111 : t = 7'b111_1111;
default : t = 8'b0000_0000;
endcase
endmodule |
module aibio_bias_trim
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins---------//
input [2:0]i_bias_trim,
input i_pbias,
input i_nbias,
//--------Output pins----------//
output [2:0]o_pbias_trim,
output [2:0]o_nbias_trim
);
//assign o_pbias_trim = ~(i_bias_trim);
//assign o_nbias_trim = i_bias_trim;
assign o_pbias_trim[0] = i_bias_trim[0] ? i_pbias : vddcq;
assign o_pbias_trim[1] = i_bias_trim[1] ? i_pbias : vddcq;
assign o_pbias_trim[2] = i_bias_trim[2] ? i_pbias : vddcq;
assign o_nbias_trim[0] = i_bias_trim[0] ? i_nbias : vss;
assign o_nbias_trim[1] = i_bias_trim[1] ? i_pbias : vss;
assign o_nbias_trim[2] = i_bias_trim[2] ? i_pbias : vss;
//assign o_pbias_trim = 3'b000;
//assign o_nbias_trim = 3'b000;
endmodule |
module aib_avmm_glue_logic(
// Inputs
input [23:0] i_waitreq_ch, // Wait request of each channel
input [23:0] i_rdatavld_ch, // Read data valid of each channel
input [31:0] o_rdata_ch_0, // Channel 0 read data bus
input [31:0] o_rdata_ch_1, // Channel 1 read data bus
input [31:0] o_rdata_ch_2, // Channel 2 read data bus
input [31:0] o_rdata_ch_3, // Channel 3 read data bus
input [31:0] o_rdata_ch_4, // Channel 4 read data bus
input [31:0] o_rdata_ch_5, // Channel 5 read data bus
input [31:0] o_rdata_ch_6, // Channel 6 read data bus
input [31:0] o_rdata_ch_7, // Channel 7 read data bus
input [31:0] o_rdata_ch_8, // Channel 8 read data bus
input [31:0] o_rdata_ch_9, // Channel 9 read data bus
input [31:0] o_rdata_ch_10, // Channel 10 read data bus
input [31:0] o_rdata_ch_11, // Channel 11 read data bus
input [31:0] o_rdata_ch_12, // Channel 12 read data bus
input [31:0] o_rdata_ch_13, // Channel 13 read data bus
input [31:0] o_rdata_ch_14, // Channel 14 read data bus
input [31:0] o_rdata_ch_15, // Channel 15 read data bus
input [31:0] o_rdata_ch_16, // Channel 16 read data bus
input [31:0] o_rdata_ch_17, // Channel 17 read data bus
input [31:0] o_rdata_ch_18, // Channel 18 read data bus
input [31:0] o_rdata_ch_19, // Channel 19 read data bus
input [31:0] o_rdata_ch_20, // Channel 20 read data bus
input [31:0] o_rdata_ch_21, // Channel 21 read data bus
input [31:0] o_rdata_ch_22, // Channel 22 read data bus
input [31:0] o_rdata_ch_23, // Channel 23 read data bus
input avmm_rdatavld_top, // Top register valid read data
input [31:0] avmm_rdata_top, // Top register read data bus
input avmm_waitreq_top, // Top register wait request
// Outputs
output o_waitreq, // Wait request
output o_rdatavld, // Read data valid
output [31:0] o_rdata // Read data bus
);
assign o_waitreq = (&i_waitreq_ch) & avmm_waitreq_top;
assign o_rdatavld = (|i_rdatavld_ch) | avmm_rdatavld_top;
assign o_rdata[31:0] = o_rdata_ch_0[31:0] |
o_rdata_ch_1[31:0] |
o_rdata_ch_2[31:0] |
o_rdata_ch_3[31:0] |
o_rdata_ch_4[31:0] |
o_rdata_ch_5[31:0] |
o_rdata_ch_6[31:0] |
o_rdata_ch_7[31:0] |
o_rdata_ch_8[31:0] |
o_rdata_ch_9[31:0] |
o_rdata_ch_10[31:0] |
o_rdata_ch_11[31:0] |
o_rdata_ch_12[31:0] |
o_rdata_ch_13[31:0] |
o_rdata_ch_14[31:0] |
o_rdata_ch_15[31:0] |
o_rdata_ch_16[31:0] |
o_rdata_ch_17[31:0] |
o_rdata_ch_18[31:0] |
o_rdata_ch_19[31:0] |
o_rdata_ch_20[31:0] |
o_rdata_ch_21[31:0] |
o_rdata_ch_22[31:0] |
o_rdata_ch_23[31:0] |
avmm_rdata_top[31:0];
endmodule // avalon_glue_logic |
module aib_fifo_rdata_ored #(
parameter DWIDTH = 80, // FIFO Input data width
parameter DEPTH = 3 // FIFO Depth
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata,
// Input
input [DEPTH-1:0][DWIDTH-1:0] fifo_out_sel
);
integer n;
always @(*)
begin
fifo_rdata = {DWIDTH{1'b0}};
for(n = 0; n < DEPTH; n = n + 1)
begin
fifo_rdata = fifo_rdata | fifo_out_sel[n];
end
end
endmodule // aib_fifo_rdata_ored |
module aib_rxfifo_rd_dpath #(
parameter DWIDTH = 320,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH*4
)
(
output [DWIDTH-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [1:0] r_fifo_mode, // FIFO mode
input m_gen2_mode, // Gen2 mode
input [DEPTH-1 :0][DWIDTH-1:0] fifo_data_async, // FIFO data
input rd_clk, // FIFO read clock
input rd_rst_n // FIFO read asynchronous reset
);
wire [DEPTH4-1:0][79:0] fifo_out_sel;
wire [DEPTH4-1 :0][79:0] fifo_dword_async;
wire [DWIDTH-1:0] fifo_rdata;
genvar k;
generate
for(k=0; k < DEPTH; k = k+1)
begin: fifo_dword_async_gen
assign fifo_dword_async[(4*k)] = fifo_data_async[k][79:0];
assign fifo_dword_async[(4*k)+1] = fifo_data_async[k][159:80];
assign fifo_dword_async[(4*k)+2] = fifo_data_async[k][239:160];
assign fifo_dword_async[(4*k)+3] = fifo_data_async[k][319:240];
end // block: fifo_dword_async_gen
endgenerate
generate
for(k=0; k < DEPTH4; k = k+1)
begin: fifo_and_sel
aib_fifo_and_sel #(.DWIDTH (80))
aib_fifo_and_sel(
// Outputs
.fifo_out_sel (fifo_out_sel[k]),
// Inputs
.fifo_rd_en (fifo_rd_en[k]),
.fifo_rd_in (fifo_dword_async[k][80-1:0])
);
end // fifo_and_sel
endgenerate
aib_rxfifo_rdata_sel #(
.DEPTH (DEPTH),
.DWIDTH (DWIDTH)
)
aib_rxfifo_rdata_sel(
// Output
.fifo_rdata (fifo_rdata[DWIDTH-1:0]),
//Input
.r_fifo_mode (r_fifo_mode[1:0]), // FIFO mode
.m_gen2_mode (m_gen2_mode), // GEN2 mode
.fifo_out_sel (fifo_out_sel)
);
aib_fifo_rdata_buf #(
.DWIDTH (DWIDTH)
)
aib_fifo_rdata_buf(
// outputs
.fifo_rdata_ff (rdata_sync_ff[DWIDTH-1:0]),
// Inputs
.fifo_rdata (fifo_rdata[DWIDTH-1:0]),
.rd_clk (rd_clk),
.rd_rst_n (rd_rst_n)
);
endmodule // aib_rxfifo_rd_dpath |
module aib_txfifo_rd_dpath #(
parameter DINW = 320,
parameter DOUTW = 80,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH * 4
)
(
output [DOUTW-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [DEPTH-1:0][DINW-1:0] fifo_data_async, // FIFO data
input rd_clk, // FIFO read clock
input rd_rst_n // FIFO read asynchronous reset
);
wire [DEPTH4-1:0][DOUTW-1:0] fifo_out_sel;
wire [DOUTW-1:0] fifo_rdata;
wire [DEPTH4-1 :0][79:0] fifo_dword_async;
genvar k;
generate
for(k=0; k < DEPTH; k = k+1)
begin: fifo_dword_async_gen
assign fifo_dword_async[(4*k)] = fifo_data_async[k][79:0];
assign fifo_dword_async[(4*k)+1] = fifo_data_async[k][159:80];
assign fifo_dword_async[(4*k)+2] = fifo_data_async[k][239:160];
assign fifo_dword_async[(4*k)+3] = fifo_data_async[k][319:240];
end // block: fifo_dword_async_gen
endgenerate
generate
for(k=0; k < DEPTH4; k = k+1)
begin: fifo_and_sel
aib_fifo_and_sel #(.DWIDTH (DOUTW))
aib_fifo_and_sel(
// Outputs
.fifo_out_sel (fifo_out_sel[k]),
// Inputs
.fifo_rd_en (fifo_rd_en[k]),
.fifo_rd_in (fifo_dword_async[k][DOUTW-1:0])
);
end // fifo_and_sel
endgenerate
aib_fifo_rdata_ored #(
.DEPTH (DEPTH4),
.DWIDTH (DOUTW)
)
aib_fifo_rdata_ored(
// Output
.fifo_rdata (fifo_rdata[DOUTW-1:0]),
//Input
.fifo_out_sel (fifo_out_sel)
);
aib_fifo_rdata_buf #(
.DWIDTH (DOUTW)
)
aib_fifo_rdata_buf(
// outputs
.fifo_rdata_ff (rdata_sync_ff[DOUTW-1:0]),
// Inputs
.fifo_rdata (fifo_rdata[DOUTW-1:0]),
.rd_clk (rd_clk),
.rd_rst_n (rd_rst_n)
);
endmodule // aib_txfifo_rd_dpath |
module aib_tx_bert #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
input clk, // TX BERT clock
input rstn, // Active low asynchronous reset
input [ 3:0] tx_start_pulse, // Start pulse to enable LFSR and Pattern
input [ 3:0] tx_rst_pulse, // Synchronous reset pulse
input [ 2:0] gen0_ptrn_sel_ff, // Select Pattern in generator0
input [ 2:0] gen1_ptrn_sel_ff, // Select Pattern in generator1
input [ 2:0] gen2_ptrn_sel_ff, // Select Pattern in generator2
input [ 2:0] gen3_ptrn_sel_ff, // Select Pattern in generator3
input [ 1:0] lane39_gen_sel_ff, // Lane39 selection
input [ 1:0] lane38_gen_sel_ff, // Lane38 selection
input [ 1:0] lane37_gen_sel_ff, // Lane37 selection
input [ 1:0] lane36_gen_sel_ff, // Lane36 selection
input [ 1:0] lane35_gen_sel_ff, // Lane35 selection
input [ 1:0] lane34_gen_sel_ff, // Lane34 selection
input [ 1:0] lane33_gen_sel_ff, // Lane33 selection
input [ 1:0] lane32_gen_sel_ff, // Lane32 selection
input [ 1:0] lane31_gen_sel_ff, // Lane31 selection
input [ 1:0] lane30_gen_sel_ff, // Lane30 selection
input [ 1:0] lane29_gen_sel_ff, // Lane29 selection
input [ 1:0] lane28_gen_sel_ff, // Lane28 selection
input [ 1:0] lane27_gen_sel_ff, // Lane27 selection
input [ 1:0] lane26_gen_sel_ff, // Lane26 selection
input [ 1:0] lane25_gen_sel_ff, // Lane25 selection
input [ 1:0] lane24_gen_sel_ff, // Lane24 selection
input [ 1:0] lane23_gen_sel_ff, // Lane23 selection
input [ 1:0] lane22_gen_sel_ff, // Lane22 selection
input [ 1:0] lane21_gen_sel_ff, // Lane21 selection
input [ 1:0] lane20_gen_sel_ff, // Lane20 selection
input [ 1:0] lane19_gen_sel_ff, // Lane19 selection
input [ 1:0] lane18_gen_sel_ff, // Lane18 selection
input [ 1:0] lane17_gen_sel_ff, // Lane17 selection
input [ 1:0] lane16_gen_sel_ff, // Lane16 selection
input [ 1:0] lane15_gen_sel_ff, // Lane15 selection
input [ 1:0] lane14_gen_sel_ff, // Lane14 selection
input [ 1:0] lane13_gen_sel_ff, // Lane13 selection
input [ 1:0] lane12_gen_sel_ff, // Lane12 selection
input [ 1:0] lane11_gen_sel_ff, // Lane11 selection
input [ 1:0] lane10_gen_sel_ff, // Lane10 selection
input [ 1:0] lane9_gen_sel_ff, // Lane9 selection
input [ 1:0] lane8_gen_sel_ff, // Lane8 selection
input [ 1:0] lane7_gen_sel_ff, // Lane7 selection
input [ 1:0] lane6_gen_sel_ff, // Lane6 selection
input [ 1:0] lane5_gen_sel_ff, // Lane5 selection
input [ 1:0] lane4_gen_sel_ff, // Lane4 selection
input [ 1:0] lane3_gen_sel_ff, // Lane3 selection
input [ 1:0] lane2_gen_sel_ff, // Lane2 selection
input [ 1:0] lane1_gen_sel_ff, // Lane1 selection
input [ 1:0] lane0_gen_sel_ff, // Lane0 selection
input [15:0] seed_ld_0, // Generator0 seed load
input [15:0] seed_ld_1, // Generator1 seed load
input [15:0] seed_ld_2, // Generator2 seed load
input [15:0] seed_ld_3, // Generator3 seed load
input [31:0] txwdata_sync_ff, // Data bus to load seed
input sdr_mode, // Sigle data rate mode
input [1:0] tx_fifo_mode, // TX FIFO mode
input m_gen2_mode, // GEN2 mode selector
output [3:0] tx_seed_good, // Seed is different from zero
output [3:0] tx_bertgen_en, // LFSR is running
output [319:0] tx_bert_data_out // TX Bert output for 40x8 bits wide signal
);
// Internal signals
wire [ 79:0] tx_gen_sel; // Selects data source for each LANE
wire [319:0] tx_bert_data_out_g1;
wire [319:0] tx_bert_data_out_g1_ddr;
wire [319:0] tx_bert_data_out_g1_sdr;
wire [319:0] tx_bert_data_out_g2;
reg [7:0] tx_gen0_data; // Reg for selecting the Pattern output
reg [7:0] tx_gen1_data; // Reg for selecting the PRBS 7 output
reg [7:0] tx_gen2_data; // Reg for selecting the PRBS 15 output
reg [7:0] tx_gen3_data; // Reg for selecting the PRBS 23 output
reg [39:0][7:0] mux_out; // Reg for the 8 bits wide output of the 40 muxes
reg [1:0] tx_sft_nb; // Select the number of shifts per clock
// Local parameters for selecting the output
localparam [1:0] GEN0 = 2'b00;
localparam [1:0] GEN1 = 2'b01;
localparam [1:0] GEN2 = 2'b10;
localparam [1:0] GEN3 = 2'b11;
// FIFO mode local params
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
//------------------------------------------------------------------------------
// Instantiation of modules
//------------------------------------------------------------------------------
// BERT generator 0
aib_bert_gen #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_gen0(
// Inputs
.clk (clk),
.rstn (rstn),
.tx_start_pulse (tx_start_pulse[0]),
.tx_rst_pulse (tx_rst_pulse[0]),
.tx_sft_nb (tx_sft_nb[1:0]),
.tx_ptrn_sel (gen0_ptrn_sel_ff[2:0]),
.tx_seed (txwdata_sync_ff[31:0]),
.tx_seed_ld (seed_ld_0[15:0]),
// Outputs
.tx_seed_good (tx_seed_good[0]),
.tx_bert_run_ff (tx_bertgen_en[0]),
.tx_bert_data (tx_gen0_data[7:0])
);
// BERT generator 1
aib_bert_gen #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_gen1(
// Inputs
.clk (clk),
.rstn (rstn),
.tx_start_pulse (tx_start_pulse[1]),
.tx_rst_pulse (tx_rst_pulse[1]),
.tx_sft_nb (tx_sft_nb[1:0]),
.tx_ptrn_sel (gen1_ptrn_sel_ff[2:0]),
.tx_seed (txwdata_sync_ff[31:0]),
.tx_seed_ld (seed_ld_1[15:0]),
// Outputs
.tx_seed_good (tx_seed_good[1]),
.tx_bert_run_ff (tx_bertgen_en[1]),
.tx_bert_data (tx_gen1_data[7:0])
);
// BERT generator 2
aib_bert_gen #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_gen2(
// Inputs
.clk (clk),
.rstn (rstn),
.tx_start_pulse (tx_start_pulse[2]),
.tx_rst_pulse (tx_rst_pulse[2]),
.tx_sft_nb (tx_sft_nb[1:0]),
.tx_ptrn_sel (gen2_ptrn_sel_ff[2:0]),
.tx_seed (txwdata_sync_ff[31:0]),
.tx_seed_ld (seed_ld_2[15:0]),
// Outputs
.tx_seed_good (tx_seed_good[2]),
.tx_bert_run_ff (tx_bertgen_en[2]),
.tx_bert_data (tx_gen2_data[7:0])
);
// BERT generator 3
aib_bert_gen #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_gen3(
// Inputs
.clk (clk),
.rstn (rstn),
.tx_start_pulse (tx_start_pulse[3]),
.tx_rst_pulse (tx_rst_pulse[3]),
.tx_sft_nb (tx_sft_nb[1:0]),
.tx_ptrn_sel (gen3_ptrn_sel_ff[2:0]),
.tx_seed (txwdata_sync_ff[31:0]),
.tx_seed_ld (seed_ld_3[15:0]),
// Outputs
.tx_seed_good (tx_seed_good[3]),
.tx_bert_run_ff (tx_bertgen_en[3]),
.tx_bert_data (tx_gen3_data[7:0])
);
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
//Logic to select the number of bits per clock
always @(*)
begin: tx_sft_nb_logic
case(tx_fifo_mode[1:0])
FIFO_1X: // FIFO 1:1 rate
begin
if(sdr_mode)
tx_sft_nb[1:0] = 2'b00; // 1 bits per clock
else
tx_sft_nb[1:0] = 2'b01; // 2 bits per clock
end
FIFO_2X: // FIFO 1:2 rate
begin
if(sdr_mode)
tx_sft_nb[1:0] = 2'b01; // 2 bits per clock
else
tx_sft_nb[1:0] = 2'b10; // 4 bits per clock
end
FIFO_4X: // FIFO 1:4 rate
begin
if(sdr_mode)
tx_sft_nb[1:0] = 2'b10; // 4 bits per clock
else
tx_sft_nb[1:0] = 2'b11; // 8 bits per clock
end
default: // register mode - BERT does not support
begin
if(sdr_mode)
tx_sft_nb[1:0] = 2'b00; // 1 bits per clock
else
tx_sft_nb[1:0] = 2'b01; // 2 bits per clock
end
endcase
end // block: tx_sft_nb_logic
//------------------------------------------------------------------------------
// Output logic for each of the 40 8 bits wide muxes
//------------------------------------------------------------------------------
assign tx_gen_sel[79:0] = { lane39_gen_sel_ff[1:0],
lane38_gen_sel_ff[1:0],
lane37_gen_sel_ff[1:0],
lane36_gen_sel_ff[1:0],
lane35_gen_sel_ff[1:0],
lane34_gen_sel_ff[1:0],
lane33_gen_sel_ff[1:0],
lane32_gen_sel_ff[1:0],
lane31_gen_sel_ff[1:0],
lane30_gen_sel_ff[1:0],
lane29_gen_sel_ff[1:0],
lane28_gen_sel_ff[1:0],
lane27_gen_sel_ff[1:0],
lane26_gen_sel_ff[1:0],
lane25_gen_sel_ff[1:0],
lane24_gen_sel_ff[1:0],
lane23_gen_sel_ff[1:0],
lane22_gen_sel_ff[1:0],
lane21_gen_sel_ff[1:0],
lane20_gen_sel_ff[1:0],
lane19_gen_sel_ff[1:0],
lane18_gen_sel_ff[1:0],
lane17_gen_sel_ff[1:0],
lane16_gen_sel_ff[1:0],
lane15_gen_sel_ff[1:0],
lane14_gen_sel_ff[1:0],
lane13_gen_sel_ff[1:0],
lane12_gen_sel_ff[1:0],
lane11_gen_sel_ff[1:0],
lane10_gen_sel_ff[1:0],
lane9_gen_sel_ff[1:0],
lane8_gen_sel_ff[1:0],
lane7_gen_sel_ff[1:0],
lane6_gen_sel_ff[1:0],
lane5_gen_sel_ff[1:0],
lane4_gen_sel_ff[1:0],
lane3_gen_sel_ff[1:0],
lane2_gen_sel_ff[1:0],
lane1_gen_sel_ff[1:0],
lane0_gen_sel_ff[1:0] };
// Transmit data MUX output per lane
genvar j;
generate
for(j=0; j<40; j=j+1)
begin: mux_out_gen
always @(*)
begin
case ({tx_gen_sel[(2*j)+1],tx_gen_sel[2*j]}) // Source Selection
GEN0: mux_out[j][7:0] = tx_gen0_data[7:0]; // GEN0 output
GEN1: mux_out[j][7:0] = tx_gen1_data[7:0]; // GEN1 output
GEN2: mux_out[j][7:0] = tx_gen2_data[7:0]; // GEN2 output
GEN3: mux_out[j][7:0] = tx_gen3_data[7:0]; // GEN3 output
endcase
end
end
endgenerate
//------------------------------------------------------------------------------
// Assigning the bits for 320 bits wide output
//------------------------------------------------------------------------------
// Unused bits in GEN1 mode received GEN2 bits
assign tx_bert_data_out_g1_sdr[319:80] = tx_bert_data_out_g2[319:80] ;
assign tx_bert_data_out_g1_ddr[319:80] = tx_bert_data_out_g2[319:80];
// TX BERT data for GEN1 mode with DDR
genvar m;
genvar n;
generate
for(m=0; m<4; m=m+2)
begin:m_tx_bert_g1_ddr
for(n=0; n<20; n=n+1)
begin: n_tx_bert_g1_ddr
assign tx_bert_data_out_g1_ddr[(m*20)+(2*n)+1:(m*20)+(2*n)] =
{mux_out[n][6-m],mux_out[n][7-m]};
end // block:n_tx_bert_g1_ddr
end // block: m_tx_bert_g1_ddr
endgenerate
// TX BERT data for GEN1 mode with SDR
generate
for(m=0; m<2; m=m+1)
begin:m_tx_bert_g1_sdr
for(n=0; n<20; n=n+1)
begin: n_tx_bert_g1_sdr
assign tx_bert_data_out_g1_sdr[(m*40)+(2*n)] = mux_out[n][7-m];
assign tx_bert_data_out_g1_sdr[(m*40)+(2*n)+1] =
tx_bert_data_out_g1_ddr[(m*40)+(2*n)+1];
end // block: n_tx_bert_g1_sdr
end // block: m_tx_bert_g1_sdr
endgenerate
// TX BERT data for GEN2 mode
genvar p;
genvar q;
generate
for(p=0; p<8; p=p+2)
begin:p_tx_bert_data_out_g2
for(q=0; q<40; q=q+1)
assign tx_bert_data_out_g2[(p*40)+(2*q)+1:(p*40)+(2*q)] =
{mux_out[q][6-p],mux_out[q][7-p]};
end // block: p_tx_bert_data_out_g2
endgenerate
// TX BERT data for GEN1 mode
assign tx_bert_data_out_g1[319:0] = sdr_mode ?
tx_bert_data_out_g1_sdr[319:0] :
tx_bert_data_out_g1_ddr[319:0];
// TX BERT data
assign tx_bert_data_out[319:0] = m_gen2_mode ?
tx_bert_data_out_g2[319:0] :
tx_bert_data_out_g1[319:0];
endmodule |
module emib_ch_m2s2 (
inout [101:0] s_aib,
inout [101:0] m_aib
);
genvar i;
generate
for (i=0; i<102; i=i+1) begin: aib_io_conn
aliasv xaliasv95 (
.PLUS(m_aib[i]),
.MINUS(s_aib[101-i])
);
end
endgenerate
endmodule |
module emib_m2s2 # ( parameter ROTATE = 0) (
inout [101:0] s_ch0_aib,
inout [101:0] s_ch1_aib,
inout [101:0] s_ch2_aib,
inout [101:0] s_ch3_aib,
inout [101:0] s_ch4_aib,
inout [101:0] s_ch5_aib,
inout [101:0] s_ch6_aib,
inout [101:0] s_ch7_aib,
inout [101:0] s_ch8_aib,
inout [101:0] s_ch9_aib,
inout [101:0] s_ch10_aib,
inout [101:0] s_ch11_aib,
inout [101:0] s_ch12_aib,
inout [101:0] s_ch13_aib,
inout [101:0] s_ch14_aib,
inout [101:0] s_ch15_aib,
inout [101:0] s_ch16_aib,
inout [101:0] s_ch17_aib,
inout [101:0] s_ch18_aib,
inout [101:0] s_ch19_aib,
inout [101:0] s_ch20_aib,
inout [101:0] s_ch21_aib,
inout [101:0] s_ch22_aib,
inout [101:0] s_ch23_aib,
inout [101:0] m_ch0_aib,
inout [101:0] m_ch1_aib,
inout [101:0] m_ch2_aib,
inout [101:0] m_ch3_aib,
inout [101:0] m_ch4_aib,
inout [101:0] m_ch5_aib,
inout [101:0] m_ch6_aib,
inout [101:0] m_ch7_aib,
inout [101:0] m_ch8_aib,
inout [101:0] m_ch9_aib,
inout [101:0] m_ch10_aib,
inout [101:0] m_ch11_aib,
inout [101:0] m_ch12_aib,
inout [101:0] m_ch13_aib,
inout [101:0] m_ch14_aib,
inout [101:0] m_ch15_aib,
inout [101:0] m_ch16_aib,
inout [101:0] m_ch17_aib,
inout [101:0] m_ch18_aib,
inout [101:0] m_ch19_aib,
inout [101:0] m_ch20_aib,
inout [101:0] m_ch21_aib,
inout [101:0] m_ch22_aib,
inout [101:0] m_ch23_aib
);
generate
if (ROTATE == 1) begin
emib_ch_m2s2 ch0 (
.s_aib(s_ch23_aib),
.m_aib(m_ch0_aib)
);
emib_ch_m2s2 ch1 (
.s_aib(s_ch22_aib),
.m_aib(m_ch1_aib)
);
emib_ch_m2s2 ch2 (
.s_aib(s_ch21_aib),
.m_aib(m_ch2_aib)
);
emib_ch_m2s2 ch3 (
.s_aib(s_ch20_aib),
.m_aib(m_ch3_aib)
);
emib_ch_m2s2 ch4 (
.s_aib(s_ch19_aib),
.m_aib(m_ch4_aib)
);
emib_ch_m2s2 ch5 (
.s_aib(s_ch18_aib),
.m_aib(m_ch5_aib)
);
emib_ch_m2s2 ch6 (
.s_aib(s_ch17_aib),
.m_aib(m_ch6_aib)
);
emib_ch_m2s2 ch7 (
.s_aib(s_ch16_aib),
.m_aib(m_ch7_aib)
);
emib_ch_m2s2 ch8 (
.s_aib(s_ch15_aib),
.m_aib(m_ch8_aib)
);
emib_ch_m2s2 ch9 (
.s_aib(s_ch14_aib),
.m_aib(m_ch9_aib)
);
emib_ch_m2s2 ch10 (
.s_aib(s_ch13_aib),
.m_aib(m_ch10_aib)
);
emib_ch_m2s2 ch11 (
.s_aib(s_ch12_aib),
.m_aib(m_ch11_aib)
);
emib_ch_m2s2 ch12 (
.s_aib(s_ch11_aib),
.m_aib(m_ch12_aib)
);
emib_ch_m2s2 ch13 (
.s_aib(s_ch10_aib),
.m_aib(m_ch13_aib)
);
emib_ch_m2s2 ch14 (
.s_aib(s_ch9_aib),
.m_aib(m_ch14_aib)
);
emib_ch_m2s2 ch15 (
.s_aib(s_ch8_aib),
.m_aib(m_ch15_aib)
);
emib_ch_m2s2 ch16 (
.s_aib(s_ch7_aib),
.m_aib(m_ch16_aib)
);
emib_ch_m2s2 ch17 (
.s_aib(s_ch6_aib),
.m_aib(m_ch17_aib)
);
emib_ch_m2s2 ch18 (
.s_aib(s_ch5_aib),
.m_aib(m_ch18_aib)
);
emib_ch_m2s2 ch19 (
.s_aib(s_ch4_aib),
.m_aib(m_ch19_aib)
);
emib_ch_m2s2 ch20 (
.s_aib(s_ch3_aib),
.m_aib(m_ch20_aib)
);
emib_ch_m2s2 ch21 (
.s_aib(s_ch2_aib),
.m_aib(m_ch21_aib)
);
emib_ch_m2s2 ch22 (
.s_aib(s_ch1_aib),
.m_aib(m_ch22_aib)
);
emib_ch_m2s2 ch23 (
.s_aib(s_ch0_aib),
.m_aib(m_ch23_aib)
);
end
else begin
emib_ch_m2s2 ch0 (
.s_aib(s_ch0_aib),
.m_aib(m_ch0_aib)
);
emib_ch_m2s2 ch1 (
.s_aib(s_ch1_aib),
.m_aib(m_ch1_aib)
);
emib_ch_m2s2 ch2 (
.s_aib(s_ch2_aib),
.m_aib(m_ch2_aib)
);
emib_ch_m2s2 ch3 (
.s_aib(s_ch3_aib),
.m_aib(m_ch3_aib)
);
emib_ch_m2s2 ch4 (
.s_aib(s_ch4_aib),
.m_aib(m_ch4_aib)
);
emib_ch_m2s2 ch5 (
.s_aib(s_ch5_aib),
.m_aib(m_ch5_aib)
);
emib_ch_m2s2 ch6 (
.s_aib(s_ch6_aib),
.m_aib(m_ch6_aib)
);
emib_ch_m2s2 ch7 (
.s_aib(s_ch7_aib),
.m_aib(m_ch7_aib)
);
emib_ch_m2s2 ch8 (
.s_aib(s_ch8_aib),
.m_aib(m_ch8_aib)
);
emib_ch_m2s2 ch9 (
.s_aib(s_ch9_aib),
.m_aib(m_ch9_aib)
);
emib_ch_m2s2 ch10 (
.s_aib(s_ch10_aib),
.m_aib(m_ch10_aib)
);
emib_ch_m2s2 ch11 (
.s_aib(s_ch11_aib),
.m_aib(m_ch11_aib)
);
emib_ch_m2s2 ch12 (
.s_aib(s_ch12_aib),
.m_aib(m_ch12_aib)
);
emib_ch_m2s2 ch13 (
.s_aib(s_ch13_aib),
.m_aib(m_ch13_aib)
);
emib_ch_m2s2 ch14 (
.s_aib(s_ch14_aib),
.m_aib(m_ch14_aib)
);
emib_ch_m2s2 ch15 (
.s_aib(s_ch15_aib),
.m_aib(m_ch15_aib)
);
emib_ch_m2s2 ch16 (
.s_aib(s_ch16_aib),
.m_aib(m_ch16_aib)
);
emib_ch_m2s2 ch17 (
.s_aib(s_ch17_aib),
.m_aib(m_ch17_aib)
);
emib_ch_m2s2 ch18 (
.s_aib(s_ch18_aib),
.m_aib(m_ch18_aib)
);
emib_ch_m2s2 ch19 (
.s_aib(s_ch19_aib),
.m_aib(m_ch19_aib)
);
emib_ch_m2s2 ch20 (
.s_aib(s_ch20_aib),
.m_aib(m_ch20_aib)
);
emib_ch_m2s2 ch21 (
.s_aib(s_ch21_aib),
.m_aib(m_ch21_aib)
);
emib_ch_m2s2 ch22 (
.s_aib(s_ch22_aib),
.m_aib(m_ch22_aib)
);
emib_ch_m2s2 ch23 (
.s_aib(s_ch23_aib),
.m_aib(m_ch23_aib)
);
end
endgenerate
endmodule |
module emib_ch_m2s1 (
inout [95:0] s_aib,
inout [101:0] m_aib
);
wire tie_low = 1'b0;
aliasv xaliasv101 (
.PLUS(m_aib[101]),
.MINUS()
);
aliasv xaliasv100 (
.PLUS(m_aib[100]),
.MINUS()
);
aliasv xaliasv99 (
.PLUS(m_aib[99]),
.MINUS()
);
aliasv xaliasv98 (
.PLUS(m_aib[98]),
.MINUS()
);
aliasv xaliasv97 (
.PLUS(m_aib[97]),
.MINUS()
);
aliasv xaliasv96 (
.PLUS(m_aib[96]),
.MINUS()
);
aliasv xaliasv95 (
.PLUS(m_aib[95]),
.MINUS()
);
aliasv xaliasv94 (
.PLUS(m_aib[94]),
.MINUS()
);
aliasv xaliasv93 (
.PLUS(m_aib[93]),
.MINUS()
);
aliasv xaliasv92 (
.PLUS(m_aib[92]),
.MINUS()
);
aliasv xaliasv91 (
.PLUS(m_aib[91]),
.MINUS()
);
aliasv xaliasv90 (
.PLUS(m_aib[90]),
.MINUS()
);
aliasv xaliasv89 (
.PLUS(m_aib[89]),
.MINUS()
);
aliasv xaliasv88 (
.PLUS(m_aib[88]),
.MINUS()
);
aliasv xaliasv87 (
.PLUS(m_aib[87]),
.MINUS()
);
aliasv xaliasv86 (
.PLUS(m_aib[86]),
.MINUS()
);
aliasv xaliasv85 (
.PLUS(m_aib[85]),
.MINUS()
);
aliasv xaliasv84 (
.PLUS(m_aib[84]),
.MINUS()
);
aliasv xaliasv83 (
.PLUS(m_aib[83]),
.MINUS()
);
aliasv xaliasv82 (
.PLUS(m_aib[82]),
.MINUS()
);
aliasv xaliasv81 (
.PLUS(m_aib[81]),
.MINUS(s_aib[38])
);
aliasv xaliasv80 (
.PLUS(m_aib[80]),
.MINUS(s_aib[39])
);
aliasv xaliasv79 (
.PLUS(m_aib[79]),
.MINUS(s_aib[36])
);
aliasv xaliasv78 (
.PLUS(m_aib[78]),
.MINUS(s_aib[37])
);
aliasv xaliasv77 (
.PLUS(m_aib[77]),
.MINUS(s_aib[34])
);
aliasv xaliasv76 (
.PLUS(m_aib[76]),
.MINUS(s_aib[35])
);
aliasv xaliasv75 (
.PLUS(m_aib[75]),
.MINUS(s_aib[32])
);
aliasv xaliasv74 (
.PLUS(m_aib[74]),
.MINUS(s_aib[33])
);
aliasv xaliasv73 (
.PLUS(m_aib[73]),
.MINUS(s_aib[30])
);
aliasv xaliasv72 (
.PLUS(m_aib[72]),
.MINUS(s_aib[31])
);
aliasv xaliasv71 (
.PLUS(m_aib[71]),
.MINUS(s_aib[43])
);
aliasv xaliasv70 (
.PLUS(m_aib[70]),
.MINUS(s_aib[42])
);
aliasv xaliasv69 (
.PLUS(m_aib[69]),
.MINUS(s_aib[28])
);
aliasv xaliasv68 (
.PLUS(m_aib[68]),
.MINUS(s_aib[29])
);
aliasv xaliasv67 (
.PLUS(m_aib[67]),
.MINUS(s_aib[26])
);
aliasv xaliasv66 (
.PLUS(m_aib[66]),
.MINUS(s_aib[27])
);
aliasv xaliasv65 (
.PLUS(m_aib[65]),
.MINUS(s_aib[24])
);
aliasv xaliasv64 (
.PLUS(m_aib[64]),
.MINUS(s_aib[25])
);
aliasv xaliasv63 (
.PLUS(m_aib[63]),
.MINUS(s_aib[22])
);
aliasv xaliasv62 (
.PLUS(m_aib[62]),
.MINUS(s_aib[23])
);
aliasv xaliasv61 (
.PLUS(m_aib[61]),
.MINUS(s_aib[20])
);
aliasv xaliasv60 (
.PLUS(m_aib[60]),
.MINUS(s_aib[21])
);
aliasv xaliasv59 (
.PLUS(m_aib[59]),
.MINUS(s_aib[57])
);
aliasv xaliasv58 (
.PLUS(m_aib[58]),
.MINUS(s_aib[59])
);
aliasv xaliasv57 (
.PLUS(m_aib[57]),
.MINUS(s_aib[83])
);
aliasv xaliasv56 (
.PLUS(m_aib[56]),
.MINUS(s_aib[82])
);
aliasv xaliasv55 (
.PLUS(m_aib[55]),
.MINUS(s_aib[93])
);
aliasv xaliasv54 (
.PLUS(m_aib[54]),
.MINUS(s_aib[92])
);
aliasv xaliasv53 (
.PLUS(m_aib[53]),
.MINUS(s_aib[44])
);
aliasv xaliasv52 (
.PLUS(m_aib[52]),
.MINUS(s_aib[65])
);
aliasv xaliasv51 (
.PLUS(m_aib[51]),
.MINUS()
);
aliasv xaliasv50 (
.PLUS(m_aib[50]),
.MINUS()
);
aliasv xaliasv49 (
.PLUS(m_aib[49]),
.MINUS(s_aib[56])
);
aliasv xaliasv48 (
.PLUS(m_aib[48]),
.MINUS(s_aib[49])
);
aliasv xaliasv47 (
.PLUS(m_aib[47]),
.MINUS(s_aib[94])
);
aliasv xaliasv46 (
.PLUS(m_aib[46]),
.MINUS(s_aib[95])
);
aliasv xaliasv45 (
.PLUS(m_aib[45]),
.MINUS(s_aib[84])
);
aliasv xaliasv44 (
.PLUS(m_aib[44]),
.MINUS(s_aib[85])
);
aliasv xaliasv43 (
.PLUS(m_aib[43]),
.MINUS(s_aib[86])
);
aliasv xaliasv42 (
.PLUS(m_aib[42]),
.MINUS(s_aib[87])
);
aliasv xaliasv41 (
.PLUS(m_aib[41]),
.MINUS(s_aib[1])
);
aliasv xaliasv40 (
.PLUS(m_aib[40]),
.MINUS(s_aib[0])
);
aliasv xaliasv39 (
.PLUS(m_aib[39]),
.MINUS(s_aib[3])
);
aliasv xaliasv38 (
.PLUS(m_aib[38]),
.MINUS(s_aib[2])
);
aliasv xaliasv37 (
.PLUS(m_aib[37]),
.MINUS(s_aib[5])
);
aliasv xaliasv36 (
.PLUS(m_aib[36]),
.MINUS(s_aib[4])
);
aliasv xaliasv35 (
.PLUS(m_aib[35]),
.MINUS(s_aib[7])
);
aliasv xaliasv34 (
.PLUS(m_aib[34]),
.MINUS(s_aib[6])
);
aliasv xaliasv33 (
.PLUS(m_aib[33]),
.MINUS(s_aib[9])
);
aliasv xaliasv32 (
.PLUS(m_aib[32]),
.MINUS(s_aib[8])
);
aliasv xaliasv31 (
.PLUS(m_aib[31]),
.MINUS(s_aib[40])
);
aliasv xaliasv30 (
.PLUS(m_aib[30]),
.MINUS(s_aib[41])
);
aliasv xaliasv29 (
.PLUS(m_aib[29]),
.MINUS(s_aib[11])
);
aliasv xaliasv28 (
.PLUS(m_aib[28]),
.MINUS(s_aib[10])
);
aliasv xaliasv27 (
.PLUS(m_aib[27]),
.MINUS(s_aib[13])
);
aliasv xaliasv26 (
.PLUS(m_aib[26]),
.MINUS(s_aib[12])
);
aliasv xaliasv25 (
.PLUS(m_aib[25]),
.MINUS(s_aib[15])
);
aliasv xaliasv24 (
.PLUS(m_aib[24]),
.MINUS(s_aib[14])
);
aliasv xaliasv23 (
.PLUS(m_aib[23]),
.MINUS(s_aib[17])
);
aliasv xaliasv22 (
.PLUS(m_aib[22]),
.MINUS(s_aib[16])
);
aliasv xaliasv21 (
.PLUS(m_aib[21]),
.MINUS(s_aib[19])
);
aliasv xaliasv20 (
.PLUS(m_aib[20]),
.MINUS(s_aib[18])
);
aliasv xaliasv19 (
.PLUS(m_aib[19]),
.MINUS()
);
aliasv xaliasv18 (
.PLUS(m_aib[18]),
.MINUS()
);
aliasv xaliasv17 (
.PLUS(m_aib[17]),
.MINUS()
);
aliasv xaliasv16 (
.PLUS(m_aib[16]),
.MINUS()
);
aliasv xaliasv15 (
.PLUS(m_aib[15]),
.MINUS()
);
aliasv xaliasv14 (
.PLUS(m_aib[14]),
.MINUS()
);
aliasv xaliasv13 (
.PLUS(m_aib[13]),
.MINUS()
);
aliasv xaliasv12 (
.PLUS(m_aib[12]),
.MINUS()
);
aliasv xaliasv11 (
.PLUS(m_aib[11]),
.MINUS()
);
aliasv xaliasv10 (
.PLUS(m_aib[10]),
.MINUS()
);
aliasv xaliasv9 (
.PLUS(m_aib[9]),
.MINUS()
);
aliasv xaliasv8 (
.PLUS(m_aib[8]),
.MINUS()
);
aliasv xaliasv7 (
.PLUS(m_aib[7]),
.MINUS()
);
aliasv xaliasv6 (
.PLUS(m_aib[6]),
.MINUS()
);
aliasv xaliasv5 (
.PLUS(m_aib[5]),
.MINUS()
);
aliasv xaliasv4 (
.PLUS(m_aib[4]),
.MINUS()
);
aliasv xaliasv3 (
.PLUS(m_aib[3]),
.MINUS()
);
aliasv xaliasv2 (
.PLUS(m_aib[2]),
.MINUS()
);
aliasv xaliasv1 (
.PLUS(m_aib[1]),
.MINUS()
);
aliasv xaliasv0 (
.PLUS(m_aib[0]),
.MINUS()
);
//Unused pin of Slave MAIB
aliasv xalias_sl45 (
.PLUS(),
.MINUS(s_aib[45])
);
aliasv xalias_sl58 (
.PLUS(),
.MINUS(s_aib[58])
);
aliasv xalias_sl61 (
.PLUS(),
.MINUS(s_aib[61])
);
aliasv xalias_sl63 (
.PLUS(),
.MINUS(s_aib[63])
);
aliasv xalias_sl64 (
.PLUS(),
.MINUS(s_aib[64])
);
aliasv xalias_sl67 (
.PLUS(),
.MINUS(s_aib[67])
);
aliasv xalias_sl73 (
.PLUS(),
.MINUS(s_aib[73])
);
aliasv xalias_sl74 (
.PLUS(),
.MINUS(s_aib[74])
);
aliasv xalias_sl78 (
.PLUS(),
.MINUS(s_aib[78])
);
aliasv xalias_sl79 (
.PLUS(),
.MINUS(s_aib[79])
);
aliasv xalias_sl80 (
.PLUS(),
.MINUS(s_aib[80])
);
aliasv xalias_sl81 (
.PLUS(),
.MINUS(s_aib[81])
);
aliasv xalias_sl88 (
.PLUS(),
.MINUS(s_aib[88])
);
aliasv xalias_sl89 (
.PLUS(),
.MINUS(s_aib[89])
);
aliasv xalias_sl47 (
.PLUS(tie_low),
.MINUS(s_aib[47])
);
aliasv xalias_sl46 (
.PLUS(tie_low),
.MINUS(s_aib[46])
);
aliasv xalias_sl48 (
.PLUS(tie_low),
.MINUS(s_aib[48])
);
aliasv xalias_sl50 (
.PLUS(tie_low),
.MINUS(s_aib[50])
);
aliasv xalias_sl51 (
.PLUS(tie_low),
.MINUS(s_aib[51])
);
aliasv xalias_sl52 (
.PLUS(tie_low),
.MINUS(s_aib[52])
);
aliasv xalias_sl53 (
.PLUS(tie_low),
.MINUS(s_aib[53])
);
aliasv xalias_sl54 (
.PLUS(tie_low),
.MINUS(s_aib[54])
);
aliasv xalias_sl55 (
.PLUS(tie_low),
.MINUS(s_aib[55])
);
aliasv xalias_sl60 (
.PLUS(tie_low),
.MINUS(s_aib[60])
);
aliasv xalias_sl62 (
.PLUS(tie_low),
.MINUS(s_aib[62])
);
aliasv xalias_sl66 (
.PLUS(tie_low),
.MINUS(s_aib[66])
);
aliasv xalias_sl68 (
.PLUS(tie_low),
.MINUS(s_aib[68])
);
aliasv xalias_sl69 (
.PLUS(tie_low),
.MINUS(s_aib[69])
);
aliasv xalias_sl70 (
.PLUS(tie_low),
.MINUS(s_aib[70])
);
aliasv xalias_sl71 (
.PLUS(tie_low),
.MINUS(s_aib[71])
);
aliasv xalias_sl72 (
.PLUS(),
.MINUS(s_aib[72])
);
aliasv xalias_sl75 (
.PLUS(tie_low),
.MINUS(s_aib[75])
);
aliasv xalias_sl76 (
.PLUS(tie_low),
.MINUS(s_aib[76])
);
aliasv xalias_sl77 (
.PLUS(tie_low),
.MINUS(s_aib[77])
);
aliasv xalias_sl90 (
.PLUS(tie_low),
.MINUS(s_aib[90])
);
aliasv xalias_sl91 (
.PLUS(tie_low),
.MINUS(s_aib[91])
);
endmodule |
module emib_ch_m1s2 (
inout [95:0] m_aib,
inout [101:0] s_aib
);
wire tie_low = 1'b0;
wire tie_hi = 1'b1;
aliasv xaliasv101 (
.MINUS(s_aib[101]),
.PLUS()
);
aliasv xaliasv100 (
.MINUS(s_aib[100]),
.PLUS()
);
aliasv xaliasv99 (
.MINUS(s_aib[99]),
.PLUS()
);
aliasv xaliasv98 (
.MINUS(s_aib[98]),
.PLUS()
);
aliasv xaliasv97 (
.MINUS(s_aib[97]),
.PLUS()
);
aliasv xaliasv96 (
.MINUS(s_aib[96]),
.PLUS()
);
aliasv xaliasv95 (
.MINUS(s_aib[95]),
.PLUS()
);
aliasv xaliasv94 (
.MINUS(s_aib[94]),
.PLUS()
);
aliasv xaliasv93 (
.MINUS(s_aib[93]),
.PLUS()
);
aliasv xaliasv92 (
.MINUS(s_aib[92]),
.PLUS()
);
aliasv xaliasv91 (
.MINUS(s_aib[91]),
.PLUS()
);
aliasv xaliasv90 (
.MINUS(s_aib[90]),
.PLUS()
);
aliasv xaliasv89 (
.MINUS(s_aib[89]),
.PLUS()
);
aliasv xaliasv88 (
.MINUS(s_aib[88]),
.PLUS()
);
aliasv xaliasv87 (
.MINUS(s_aib[87]),
.PLUS()
);
aliasv xaliasv86 (
.MINUS(s_aib[86]),
.PLUS()
);
aliasv xaliasv85 (
.MINUS(s_aib[85]),
.PLUS()
);
aliasv xaliasv84 (
.MINUS(s_aib[84]),
.PLUS()
);
aliasv xaliasv83 (
.MINUS(s_aib[83]),
.PLUS()
);
aliasv xaliasv82 (
.MINUS(s_aib[82]),
.PLUS()
);
aliasv xaliasv81 (
.MINUS(s_aib[81]),
.PLUS(m_aib[18])
);
aliasv xaliasv80 (
.MINUS(s_aib[80]),
.PLUS(m_aib[19])
);
aliasv xaliasv79 (
.MINUS(s_aib[79]),
.PLUS(m_aib[16])
);
aliasv xaliasv78 (
.MINUS(s_aib[78]),
.PLUS(m_aib[17])
);
aliasv xaliasv77 (
.MINUS(s_aib[77]),
.PLUS(m_aib[14])
);
aliasv xaliasv76 (
.MINUS(s_aib[76]),
.PLUS(m_aib[15])
);
aliasv xaliasv75 (
.MINUS(s_aib[75]),
.PLUS(m_aib[12])
);
aliasv xaliasv74 (
.MINUS(s_aib[74]),
.PLUS(m_aib[13])
);
aliasv xaliasv73 (
.MINUS(s_aib[73]),
.PLUS(m_aib[10])
);
aliasv xaliasv72 (
.MINUS(s_aib[72]),
.PLUS(m_aib[11])
);
aliasv xaliasv71 (
.MINUS(s_aib[71]),
.PLUS(m_aib[41])
);
aliasv xaliasv70 (
.MINUS(s_aib[70]),
.PLUS(m_aib[40])
);
aliasv xaliasv69 (
.MINUS(s_aib[69]),
.PLUS(m_aib[8])
);
aliasv xaliasv68 (
.MINUS(s_aib[68]),
.PLUS(m_aib[9])
);
aliasv xaliasv67 (
.MINUS(s_aib[67]),
.PLUS(m_aib[6])
);
aliasv xaliasv66 (
.MINUS(s_aib[66]),
.PLUS(m_aib[7])
);
aliasv xaliasv65 (
.MINUS(s_aib[65]),
.PLUS(m_aib[4])
);
aliasv xaliasv64 (
.MINUS(s_aib[64]),
.PLUS(m_aib[5])
);
aliasv xaliasv63 (
.MINUS(s_aib[63]),
.PLUS(m_aib[2])
);
aliasv xaliasv62 (
.MINUS(s_aib[62]),
.PLUS(m_aib[3])
);
aliasv xaliasv61 (
.MINUS(s_aib[61]),
.PLUS(m_aib[0])
);
aliasv xaliasv60 (
.MINUS(s_aib[60]),
.PLUS(m_aib[1])
);
aliasv xaliasv59 (
.MINUS(s_aib[59]),
.PLUS(m_aib[87])
);
aliasv xaliasv58 (
.MINUS(s_aib[58]),
.PLUS(m_aib[86])
);
aliasv xaliasv57 (
.MINUS(s_aib[57]),
.PLUS(m_aib[85])
);
aliasv xaliasv56 (
.MINUS(s_aib[56]),
.PLUS(m_aib[84])
);
aliasv xaliasv55 (
.MINUS(s_aib[55]),
.PLUS(m_aib[95])
);
aliasv xaliasv54 (
.MINUS(s_aib[54]),
.PLUS(m_aib[94])
);
aliasv xaliasv53 (
.MINUS(s_aib[53]),
.PLUS(m_aib[49])
);
aliasv xaliasv52 (
.MINUS(s_aib[52]),
.PLUS(m_aib[56])
);
aliasv xaliasv51 (
.MINUS(s_aib[51]),
.PLUS()
);
aliasv xaliasv50 (
.MINUS(s_aib[50]),
.PLUS()
);
aliasv xaliasv49 (
.MINUS(s_aib[49]),
.PLUS(m_aib[65])
);
aliasv xaliasv48 (
.MINUS(s_aib[48]),
.PLUS(m_aib[44])
);
aliasv xaliasv47 (
.MINUS(s_aib[47]),
.PLUS(m_aib[92])
);
aliasv xaliasv46 (
.MINUS(s_aib[46]),
.PLUS(m_aib[93])
);
aliasv xaliasv45 (
.MINUS(s_aib[45]),
.PLUS(m_aib[82])
);
aliasv xaliasv44 (
.MINUS(s_aib[44]),
.PLUS(m_aib[83])
);
aliasv xaliasv43 (
.MINUS(s_aib[43]),
.PLUS(m_aib[59])
);
aliasv xaliasv42 (
.MINUS(s_aib[42]),
.PLUS(m_aib[57])
);
aliasv xaliasv41 (
.MINUS(s_aib[41]),
.PLUS(m_aib[21])
);
aliasv xaliasv40 (
.MINUS(s_aib[40]),
.PLUS(m_aib[20])
);
aliasv xaliasv39 (
.MINUS(s_aib[39]),
.PLUS(m_aib[23])
);
aliasv xaliasv38 (
.MINUS(s_aib[38]),
.PLUS(m_aib[22])
);
aliasv xaliasv37 (
.MINUS(s_aib[37]),
.PLUS(m_aib[25])
);
aliasv xaliasv36 (
.MINUS(s_aib[36]),
.PLUS(m_aib[24])
);
aliasv xaliasv35 (
.MINUS(s_aib[35]),
.PLUS(m_aib[27])
);
aliasv xaliasv34 (
.MINUS(s_aib[34]),
.PLUS(m_aib[26])
);
aliasv xaliasv33 (
.MINUS(s_aib[33]),
.PLUS(m_aib[29])
);
aliasv xaliasv32 (
.MINUS(s_aib[32]),
.PLUS(m_aib[28])
);
aliasv xaliasv31 (
.MINUS(s_aib[31]),
.PLUS(m_aib[42])
);
aliasv xaliasv30 (
.MINUS(s_aib[30]),
.PLUS(m_aib[43])
);
aliasv xaliasv29 (
.MINUS(s_aib[29]),
.PLUS(m_aib[31])
);
aliasv xaliasv28 (
.MINUS(s_aib[28]),
.PLUS(m_aib[30])
);
aliasv xaliasv27 (
.MINUS(s_aib[27]),
.PLUS(m_aib[33])
);
aliasv xaliasv26 (
.MINUS(s_aib[26]),
.PLUS(m_aib[32])
);
aliasv xaliasv25 (
.MINUS(s_aib[25]),
.PLUS(m_aib[35])
);
aliasv xaliasv24 (
.MINUS(s_aib[24]),
.PLUS(m_aib[34])
);
aliasv xaliasv23 (
.MINUS(s_aib[23]),
.PLUS(m_aib[37])
);
aliasv xaliasv22 (
.MINUS(s_aib[22]),
.PLUS(m_aib[36])
);
aliasv xaliasv21 (
.MINUS(s_aib[21]),
.PLUS(m_aib[39])
);
aliasv xaliasv20 (
.MINUS(s_aib[20]),
.PLUS(m_aib[38])
);
aliasv xaliasv19 (
.MINUS(s_aib[19]),
.PLUS()
);
aliasv xaliasv18 (
.MINUS(s_aib[18]),
.PLUS()
);
aliasv xaliasv17 (
.MINUS(s_aib[17]),
.PLUS()
);
aliasv xaliasv16 (
.MINUS(s_aib[16]),
.PLUS()
);
aliasv xaliasv15 (
.MINUS(s_aib[15]),
.PLUS()
);
aliasv xaliasv14 (
.MINUS(s_aib[14]),
.PLUS()
);
aliasv xaliasv13 (
.MINUS(s_aib[13]),
.PLUS()
);
aliasv xaliasv12 (
.MINUS(s_aib[12]),
.PLUS()
);
aliasv xaliasv11 (
.MINUS(s_aib[11]),
.PLUS()
);
aliasv xaliasv10 (
.MINUS(s_aib[10]),
.PLUS()
);
aliasv xaliasv9 (
.MINUS(s_aib[9]),
.PLUS()
);
aliasv xaliasv8 (
.MINUS(s_aib[8]),
.PLUS()
);
aliasv xaliasv7 (
.MINUS(s_aib[7]),
.PLUS()
);
aliasv xaliasv6 (
.MINUS(s_aib[6]),
.PLUS()
);
aliasv xaliasv5 (
.MINUS(s_aib[5]),
.PLUS()
);
aliasv xaliasv4 (
.MINUS(s_aib[4]),
.PLUS()
);
aliasv xaliasv3 (
.MINUS(s_aib[3]),
.PLUS()
);
aliasv xaliasv2 (
.MINUS(s_aib[2]),
.PLUS()
);
aliasv xaliasv1 (
.MINUS(s_aib[1]),
.PLUS()
);
aliasv xaliasv0 (
.MINUS(s_aib[0]),
.PLUS()
);
//Unused pin of Gen1 Master AIB
aliasv xalias_ms45 (
.MINUS(tie_low),
.PLUS(m_aib[45])
);
aliasv xalias_ms58 (
.MINUS(tie_low),
.PLUS(m_aib[58])
);
aliasv xalias_ms61 (
.MINUS(tie_hi),
.PLUS(m_aib[61])
);
aliasv xalias_ms63 (
.MINUS(tie_low),
.PLUS(m_aib[63])
);
aliasv xalias_ms64 (
.MINUS(tie_low),
.PLUS(m_aib[64])
);
aliasv xalias_ms67 (
.MINUS(tie_low),
.PLUS(m_aib[67])
);
aliasv xalias_ms73 (
.MINUS(tie_low),
.PLUS(m_aib[73])
);
aliasv xalias_ms74 (
.MINUS(tie_low),
.PLUS(m_aib[74])
);
aliasv xalias_ms78 (
.MINUS(tie_low),
.PLUS(m_aib[78])
);
aliasv xalias_ms79 (
.MINUS(tie_low),
.PLUS(m_aib[79])
);
aliasv xalias_ms80 (
.MINUS(tie_low),
.PLUS(m_aib[80])
);
aliasv xalias_ms81 (
.MINUS(tie_low),
.PLUS(m_aib[81])
);
aliasv xalias_ms88 (
.MINUS(tie_low),
.PLUS(m_aib[88])
);
aliasv xalias_ms89 (
.MINUS(tie_low),
.PLUS(m_aib[89])
);
aliasv xalias_ms47 (
.MINUS(),
.PLUS(m_aib[47])
);
aliasv xalias_ms46 (
.MINUS(),
.PLUS(m_aib[46])
);
aliasv xalias_ms48 (
.MINUS(),
.PLUS(m_aib[48])
);
aliasv xalias_ms50 (
.MINUS(),
.PLUS(m_aib[50])
);
aliasv xalias_ms51 (
.MINUS(),
.PLUS(m_aib[51])
);
aliasv xalias_ms52 (
.MINUS(),
.PLUS(m_aib[52])
);
aliasv xalias_ms53 (
.MINUS(),
.PLUS(m_aib[53])
);
aliasv xalias_ms54 (
.MINUS(),
.PLUS(m_aib[54])
);
aliasv xalias_ms55 (
.MINUS(),
.PLUS(m_aib[55])
);
aliasv xalias_ms60 (
.MINUS(),
.PLUS(m_aib[60])
);
aliasv xalias_ms62 (
.MINUS(),
.PLUS(m_aib[62])
);
aliasv xalias_ms66 (
.MINUS(),
.PLUS(m_aib[66])
);
aliasv xalias_ms68 (
.MINUS(),
.PLUS(m_aib[68])
);
aliasv xalias_ms69 (
.MINUS(),
.PLUS(m_aib[69])
);
aliasv xalias_ms70 (
.MINUS(),
.PLUS(m_aib[70])
);
aliasv xalias_ms71 (
.MINUS(),
.PLUS(m_aib[71])
);
aliasv xalias_ms72 (
.MINUS(),
.PLUS(m_aib[72])
);
aliasv xalias_ms75 (
.MINUS(),
.PLUS(m_aib[75])
);
aliasv xalias_ms76 (
.MINUS(),
.PLUS(m_aib[76])
);
aliasv xalias_ms77 (
.MINUS(),
.PLUS(m_aib[77])
);
aliasv xalias_ms90 (
.MINUS(),
.PLUS(m_aib[90])
);
aliasv xalias_ms91 (
.MINUS(),
.PLUS(m_aib[91])
);
endmodule |
module emib_m2s1 (
inout [95:0] s_ch0_aib,
inout [95:0] s_ch1_aib,
inout [95:0] s_ch2_aib,
inout [95:0] s_ch3_aib,
inout [95:0] s_ch4_aib,
inout [95:0] s_ch5_aib,
inout [95:0] s_ch6_aib,
inout [95:0] s_ch7_aib,
inout [95:0] s_ch8_aib,
inout [95:0] s_ch9_aib,
inout [95:0] s_ch10_aib,
inout [95:0] s_ch11_aib,
inout [95:0] s_ch12_aib,
inout [95:0] s_ch13_aib,
inout [95:0] s_ch14_aib,
inout [95:0] s_ch15_aib,
inout [95:0] s_ch16_aib,
inout [95:0] s_ch17_aib,
inout [95:0] s_ch18_aib,
inout [95:0] s_ch19_aib,
inout [95:0] s_ch20_aib,
inout [95:0] s_ch21_aib,
inout [95:0] s_ch22_aib,
inout [95:0] s_ch23_aib,
inout [101:0] m_ch0_aib,
inout [101:0] m_ch1_aib,
inout [101:0] m_ch2_aib,
inout [101:0] m_ch3_aib,
inout [101:0] m_ch4_aib,
inout [101:0] m_ch5_aib,
inout [101:0] m_ch6_aib,
inout [101:0] m_ch7_aib,
inout [101:0] m_ch8_aib,
inout [101:0] m_ch9_aib,
inout [101:0] m_ch10_aib,
inout [101:0] m_ch11_aib,
inout [101:0] m_ch12_aib,
inout [101:0] m_ch13_aib,
inout [101:0] m_ch14_aib,
inout [101:0] m_ch15_aib,
inout [101:0] m_ch16_aib,
inout [101:0] m_ch17_aib,
inout [101:0] m_ch18_aib,
inout [101:0] m_ch19_aib,
inout [101:0] m_ch20_aib,
inout [101:0] m_ch21_aib,
inout [101:0] m_ch22_aib,
inout [101:0] m_ch23_aib
);
emib_ch_m2s1 ch0 (
.s_aib(s_ch0_aib),
.m_aib(m_ch0_aib)
);
emib_ch_m2s1 ch1 (
.s_aib(s_ch1_aib),
.m_aib(m_ch1_aib)
);
emib_ch_m2s1 ch2 (
.s_aib(s_ch2_aib),
.m_aib(m_ch2_aib)
);
emib_ch_m2s1 ch3 (
.s_aib(s_ch3_aib),
.m_aib(m_ch3_aib)
);
emib_ch_m2s1 ch4 (
.s_aib(s_ch4_aib),
.m_aib(m_ch4_aib)
);
emib_ch_m2s1 ch5 (
.s_aib(s_ch5_aib),
.m_aib(m_ch5_aib)
);
emib_ch_m2s1 ch6 (
.s_aib(s_ch6_aib),
.m_aib(m_ch6_aib)
);
emib_ch_m2s1 ch7 (
.s_aib(s_ch7_aib),
.m_aib(m_ch7_aib)
);
emib_ch_m2s1 ch8 (
.s_aib(s_ch8_aib),
.m_aib(m_ch8_aib)
);
emib_ch_m2s1 ch9 (
.s_aib(s_ch9_aib),
.m_aib(m_ch9_aib)
);
emib_ch_m2s1 ch10 (
.s_aib(s_ch10_aib),
.m_aib(m_ch10_aib)
);
emib_ch_m2s1 ch11 (
.s_aib(s_ch11_aib),
.m_aib(m_ch11_aib)
);
emib_ch_m2s1 ch12 (
.s_aib(s_ch12_aib),
.m_aib(m_ch12_aib)
);
emib_ch_m2s1 ch13 (
.s_aib(s_ch13_aib),
.m_aib(m_ch13_aib)
);
emib_ch_m2s1 ch14 (
.s_aib(s_ch14_aib),
.m_aib(m_ch14_aib)
);
emib_ch_m2s1 ch15 (
.s_aib(s_ch15_aib),
.m_aib(m_ch15_aib)
);
emib_ch_m2s1 ch16 (
.s_aib(s_ch16_aib),
.m_aib(m_ch16_aib)
);
emib_ch_m2s1 ch17 (
.s_aib(s_ch17_aib),
.m_aib(m_ch17_aib)
);
emib_ch_m2s1 ch18 (
.s_aib(s_ch18_aib),
.m_aib(m_ch18_aib)
);
emib_ch_m2s1 ch19 (
.s_aib(s_ch19_aib),
.m_aib(m_ch19_aib)
);
emib_ch_m2s1 ch20 (
.s_aib(s_ch20_aib),
.m_aib(m_ch20_aib)
);
emib_ch_m2s1 ch21 (
.s_aib(s_ch21_aib),
.m_aib(m_ch21_aib)
);
emib_ch_m2s1 ch22 (
.s_aib(s_ch22_aib),
.m_aib(m_ch22_aib)
);
emib_ch_m2s1 ch23 (
.s_aib(s_ch23_aib),
.m_aib(m_ch23_aib)
);
endmodule |
module lut_C
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 182;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010001100101;
2: y = 16'b0000100011001000;
3: y = 16'b0000110100101001;
4: y = 16'b0001000110000110;
5: y = 16'b0001010111011110;
6: y = 16'b0001101000101111;
7: y = 16'b0001111001111000;
8: y = 16'b0010001010111000;
9: y = 16'b0010011011101101;
10: y = 16'b0010101100010111;
11: y = 16'b0010111100110011;
12: y = 16'b0011001101000010;
13: y = 16'b0011011101000001;
14: y = 16'b0011101100101111;
15: y = 16'b0011111100001011;
16: y = 16'b0100001011010101;
17: y = 16'b0100011010001010;
18: y = 16'b0100101000101010;
19: y = 16'b0100110110110011;
20: y = 16'b0101000100100110;
21: y = 16'b0101010001111111;
22: y = 16'b0101011110111111;
23: y = 16'b0101101011100101;
24: y = 16'b0101110111101111;
25: y = 16'b0110000011011101;
26: y = 16'b0110001110101110;
27: y = 16'b0110011001100000;
28: y = 16'b0110100011110100;
29: y = 16'b0110101101101000;
30: y = 16'b0110110110111100;
31: y = 16'b0110111111101110;
32: y = 16'b0111000111111111;
33: y = 16'b0111001111101101;
34: y = 16'b0111010110111000;
35: y = 16'b0111011101100000;
36: y = 16'b0111100011100100;
37: y = 16'b0111101001000011;
38: y = 16'b0111101101111110;
39: y = 16'b0111110010010011;
40: y = 16'b0111110110000011;
41: y = 16'b0111111001001100;
42: y = 16'b0111111011110000;
43: y = 16'b0111111101101101;
44: y = 16'b0111111111000100;
45: y = 16'b0111111111110100;
46: y = 16'b0111111111111110;
47: y = 16'b0111111111100001;
48: y = 16'b0111111110011101;
49: y = 16'b0111111100110011;
50: y = 16'b0111111010100011;
51: y = 16'b0111110111101100;
52: y = 16'b0111110100001111;
53: y = 16'b0111110000001101;
54: y = 16'b0111101011100101;
55: y = 16'b0111100110011000;
56: y = 16'b0111100000100111;
57: y = 16'b0111011010010001;
58: y = 16'b0111010011010111;
59: y = 16'b0111001011111010;
60: y = 16'b0111000011111011;
61: y = 16'b0110111011011001;
62: y = 16'b0110110010010110;
63: y = 16'b0110101000110010;
64: y = 16'b0110011110101110;
65: y = 16'b0110010100001011;
66: y = 16'b0110001001001001;
67: y = 16'b0101111101101010;
68: y = 16'b0101110001101110;
69: y = 16'b0101100101010110;
70: y = 16'b0101011000100011;
71: y = 16'b0101001011010110;
72: y = 16'b0100111101110000;
73: y = 16'b0100101111110010;
74: y = 16'b0100100001011101;
75: y = 16'b0100010010110010;
76: y = 16'b0100000011110010;
77: y = 16'b0011110100011111;
78: y = 16'b0011100100111010;
79: y = 16'b0011010101000011;
80: y = 16'b0011000100111100;
81: y = 16'b0010110100100111;
82: y = 16'b0010100100000011;
83: y = 16'b0010010011010100;
84: y = 16'b0010000010011001;
85: y = 16'b0001110001010100;
86: y = 16'b0001100000000111;
87: y = 16'b0001001110110011;
88: y = 16'b0000111101011000;
89: y = 16'b0000101011111001;
90: y = 16'b0000011010010111;
91: y = 16'b0000001000110010;
92: y = 16'b1111110111001110;
93: y = 16'b1111100101101001;
94: y = 16'b1111010100000111;
95: y = 16'b1111000010101000;
96: y = 16'b1110110001001101;
97: y = 16'b1110011111111001;
98: y = 16'b1110001110101100;
99: y = 16'b1101111101100111;
100: y = 16'b1101101100101100;
101: y = 16'b1101011011111101;
102: y = 16'b1101001011011001;
103: y = 16'b1100111011000100;
104: y = 16'b1100101010111101;
105: y = 16'b1100011011000110;
106: y = 16'b1100001011100001;
107: y = 16'b1011111100001110;
108: y = 16'b1011101101001110;
109: y = 16'b1011011110100011;
110: y = 16'b1011010000001110;
111: y = 16'b1011000010010000;
112: y = 16'b1010110100101010;
113: y = 16'b1010100111011101;
114: y = 16'b1010011010101010;
115: y = 16'b1010001110010010;
116: y = 16'b1010000010010110;
117: y = 16'b1001110110110111;
118: y = 16'b1001101011110101;
119: y = 16'b1001100001010010;
120: y = 16'b1001010111001110;
121: y = 16'b1001001101101010;
122: y = 16'b1001000100100111;
123: y = 16'b1000111100000101;
124: y = 16'b1000110100000110;
125: y = 16'b1000101100101001;
126: y = 16'b1000100101101111;
127: y = 16'b1000011111011001;
128: y = 16'b1000011001101000;
129: y = 16'b1000010100011011;
130: y = 16'b1000001111110011;
131: y = 16'b1000001011110001;
132: y = 16'b1000001000010100;
133: y = 16'b1000000101011101;
134: y = 16'b1000000011001101;
135: y = 16'b1000000001100011;
136: y = 16'b1000000000011111;
137: y = 16'b1000000000000010;
138: y = 16'b1000000000001100;
139: y = 16'b1000000000111100;
140: y = 16'b1000000010010011;
141: y = 16'b1000000100010000;
142: y = 16'b1000000110110100;
143: y = 16'b1000001001111101;
144: y = 16'b1000001101101101;
145: y = 16'b1000010010000010;
146: y = 16'b1000010110111101;
147: y = 16'b1000011100011100;
148: y = 16'b1000100010100000;
149: y = 16'b1000101001001000;
150: y = 16'b1000110000010011;
151: y = 16'b1000111000000001;
152: y = 16'b1001000000010010;
153: y = 16'b1001001001000100;
154: y = 16'b1001010010011000;
155: y = 16'b1001011100001100;
156: y = 16'b1001100110100000;
157: y = 16'b1001110001010010;
158: y = 16'b1001111100100011;
159: y = 16'b1010001000010001;
160: y = 16'b1010010100011011;
161: y = 16'b1010100001000001;
162: y = 16'b1010101110000001;
163: y = 16'b1010111011011010;
164: y = 16'b1011001001001101;
165: y = 16'b1011010111010110;
166: y = 16'b1011100101110110;
167: y = 16'b1011110100101011;
168: y = 16'b1100000011110101;
169: y = 16'b1100010011010001;
170: y = 16'b1100100010111111;
171: y = 16'b1100110010111110;
172: y = 16'b1101000011001101;
173: y = 16'b1101010011101001;
174: y = 16'b1101100100010011;
175: y = 16'b1101110101001000;
176: y = 16'b1110000110001000;
177: y = 16'b1110010111010001;
178: y = 16'b1110101000100010;
179: y = 16'b1110111001111010;
180: y = 16'b1111001011010111;
181: y = 16'b1111011100111000;
182: y = 16'b1111101110011011;
default: y = 16'b0;
endcase
endmodule |
module lut_Cs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 172;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010010100110;
2: y = 16'b0000100101001010;
3: y = 16'b0000110111101011;
4: y = 16'b0001001010001000;
5: y = 16'b0001011100011110;
6: y = 16'b0001101110101100;
7: y = 16'b0010000000110001;
8: y = 16'b0010010010101011;
9: y = 16'b0010100100011001;
10: y = 16'b0010110101111001;
11: y = 16'b0011000111001001;
12: y = 16'b0011011000001001;
13: y = 16'b0011101000110110;
14: y = 16'b0011111001010000;
15: y = 16'b0100001001010101;
16: y = 16'b0100011001000011;
17: y = 16'b0100101000011010;
18: y = 16'b0100110111011000;
19: y = 16'b0101000101111011;
20: y = 16'b0101010100000011;
21: y = 16'b0101100001101110;
22: y = 16'b0101101110111011;
23: y = 16'b0101111011101001;
24: y = 16'b0110000111111000;
25: y = 16'b0110010011100101;
26: y = 16'b0110011110110000;
27: y = 16'b0110101001011000;
28: y = 16'b0110110011011100;
29: y = 16'b0110111100111100;
30: y = 16'b0111000101110110;
31: y = 16'b0111001110001001;
32: y = 16'b0111010101110110;
33: y = 16'b0111011100111011;
34: y = 16'b0111100011010111;
35: y = 16'b0111101001001011;
36: y = 16'b0111101110010110;
37: y = 16'b0111110010110110;
38: y = 16'b0111110110101101;
39: y = 16'b0111111001111001;
40: y = 16'b0111111100011011;
41: y = 16'b0111111110010010;
42: y = 16'b0111111111011101;
43: y = 16'b0111111111111110;
44: y = 16'b0111111111110011;
45: y = 16'b0111111110111101;
46: y = 16'b0111111101011100;
47: y = 16'b0111111011010000;
48: y = 16'b0111111000011001;
49: y = 16'b0111110100110111;
50: y = 16'b0111110000101011;
51: y = 16'b0111101011110110;
52: y = 16'b0111100110010110;
53: y = 16'b0111100000001110;
54: y = 16'b0111011001011101;
55: y = 16'b0111010010000100;
56: y = 16'b0111001010000100;
57: y = 16'b0111000001011101;
58: y = 16'b0110111000010001;
59: y = 16'b0110101110011111;
60: y = 16'b0110100100001000;
61: y = 16'b0110011001001111;
62: y = 16'b0110001101110010;
63: y = 16'b0110000001110101;
64: y = 16'b0101110101010110;
65: y = 16'b0101101000011000;
66: y = 16'b0101011010111100;
67: y = 16'b0101001101000010;
68: y = 16'b0100111110101101;
69: y = 16'b0100101111111100;
70: y = 16'b0100100000110010;
71: y = 16'b0100010001001111;
72: y = 16'b0100000001010101;
73: y = 16'b0011110001000110;
74: y = 16'b0011100000100010;
75: y = 16'b0011001111101011;
76: y = 16'b0010111110100011;
77: y = 16'b0010101101001011;
78: y = 16'b0010011011100100;
79: y = 16'b0010001001110000;
80: y = 16'b0001110111110000;
81: y = 16'b0001100101100110;
82: y = 16'b0001010011010011;
83: y = 16'b0001000000111010;
84: y = 16'b0000101110011011;
85: y = 16'b0000011011111000;
86: y = 16'b0000001001010011;
87: y = 16'b1111110110101101;
88: y = 16'b1111100100001000;
89: y = 16'b1111010001100101;
90: y = 16'b1110111111000110;
91: y = 16'b1110101100101101;
92: y = 16'b1110011010011010;
93: y = 16'b1110001000010000;
94: y = 16'b1101110110010000;
95: y = 16'b1101100100011100;
96: y = 16'b1101010010110101;
97: y = 16'b1101000001011101;
98: y = 16'b1100110000010101;
99: y = 16'b1100011111011110;
100: y = 16'b1100001110111010;
101: y = 16'b1011111110101011;
102: y = 16'b1011101110110001;
103: y = 16'b1011011111001110;
104: y = 16'b1011010000000100;
105: y = 16'b1011000001010011;
106: y = 16'b1010110010111110;
107: y = 16'b1010100101000100;
108: y = 16'b1010010111101000;
109: y = 16'b1010001010101010;
110: y = 16'b1001111110001011;
111: y = 16'b1001110010001110;
112: y = 16'b1001100110110001;
113: y = 16'b1001011011111000;
114: y = 16'b1001010001100001;
115: y = 16'b1001000111101111;
116: y = 16'b1000111110100011;
117: y = 16'b1000110101111100;
118: y = 16'b1000101101111100;
119: y = 16'b1000100110100011;
120: y = 16'b1000011111110010;
121: y = 16'b1000011001101010;
122: y = 16'b1000010100001010;
123: y = 16'b1000001111010101;
124: y = 16'b1000001011001001;
125: y = 16'b1000000111100111;
126: y = 16'b1000000100110000;
127: y = 16'b1000000010100100;
128: y = 16'b1000000001000011;
129: y = 16'b1000000000001101;
130: y = 16'b1000000000000010;
131: y = 16'b1000000000100011;
132: y = 16'b1000000001101110;
133: y = 16'b1000000011100101;
134: y = 16'b1000000110000111;
135: y = 16'b1000001001010011;
136: y = 16'b1000001101001010;
137: y = 16'b1000010001101010;
138: y = 16'b1000010110110101;
139: y = 16'b1000011100101001;
140: y = 16'b1000100011000101;
141: y = 16'b1000101010001010;
142: y = 16'b1000110001110111;
143: y = 16'b1000111010001010;
144: y = 16'b1001000011000100;
145: y = 16'b1001001100100100;
146: y = 16'b1001010110101000;
147: y = 16'b1001100001010000;
148: y = 16'b1001101100011011;
149: y = 16'b1001111000001000;
150: y = 16'b1010000100010111;
151: y = 16'b1010010001000101;
152: y = 16'b1010011110010010;
153: y = 16'b1010101011111101;
154: y = 16'b1010111010000101;
155: y = 16'b1011001000101000;
156: y = 16'b1011010111100110;
157: y = 16'b1011100110111101;
158: y = 16'b1011110110101011;
159: y = 16'b1100000110110000;
160: y = 16'b1100010111001010;
161: y = 16'b1100100111110111;
162: y = 16'b1100111000110111;
163: y = 16'b1101001010000111;
164: y = 16'b1101011011100111;
165: y = 16'b1101101101010101;
166: y = 16'b1101111111001111;
167: y = 16'b1110010001010100;
168: y = 16'b1110100011100010;
169: y = 16'b1110110101111000;
170: y = 16'b1111001000010101;
171: y = 16'b1111011010110110;
172: y = 16'b1111101101011010;
default: y = 16'b0;
endcase
endmodule |
module lut_D
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 162;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010011101111;
2: y = 16'b0000100111011100;
3: y = 16'b0000111011000101;
4: y = 16'b0001001110101000;
5: y = 16'b0001100010000100;
6: y = 16'b0001110101010111;
7: y = 16'b0010001000011111;
8: y = 16'b0010011011011001;
9: y = 16'b0010101110000101;
10: y = 16'b0011000000100000;
11: y = 16'b0011010010101001;
12: y = 16'b0011100100011110;
13: y = 16'b0011110101111101;
14: y = 16'b0100000111000101;
15: y = 16'b0100010111110100;
16: y = 16'b0100101000001000;
17: y = 16'b0100111000000000;
18: y = 16'b0101000111011011;
19: y = 16'b0101010110010110;
20: y = 16'b0101100100110000;
21: y = 16'b0101110010101001;
22: y = 16'b0101111111111111;
23: y = 16'b0110001100110000;
24: y = 16'b0110011000111011;
25: y = 16'b0110100100011111;
26: y = 16'b0110101111011100;
27: y = 16'b0110111001101111;
28: y = 16'b0111000011011001;
29: y = 16'b0111001100010111;
30: y = 16'b0111010100101010;
31: y = 16'b0111011100010000;
32: y = 16'b0111100011001001;
33: y = 16'b0111101001010100;
34: y = 16'b0111101110110000;
35: y = 16'b0111110011011101;
36: y = 16'b0111110111011011;
37: y = 16'b0111111010101001;
38: y = 16'b0111111101000111;
39: y = 16'b0111111110110100;
40: y = 16'b0111111111110001;
41: y = 16'b0111111111111101;
42: y = 16'b0111111111011001;
43: y = 16'b0111111110000100;
44: y = 16'b0111111011111110;
45: y = 16'b0111111001001000;
46: y = 16'b0111110101100010;
47: y = 16'b0111110001001101;
48: y = 16'b0111101100001000;
49: y = 16'b0111100110010100;
50: y = 16'b0111011111110010;
51: y = 16'b0111011000100010;
52: y = 16'b0111010000100110;
53: y = 16'b0111000111111101;
54: y = 16'b0110111110101001;
55: y = 16'b0110110100101011;
56: y = 16'b0110101010000011;
57: y = 16'b0110011110110010;
58: y = 16'b0110010010111010;
59: y = 16'b0110000110011100;
60: y = 16'b0101111001011000;
61: y = 16'b0101101011110001;
62: y = 16'b0101011101100111;
63: y = 16'b0101001110111100;
64: y = 16'b0100111111110001;
65: y = 16'b0100110000001000;
66: y = 16'b0100100000000001;
67: y = 16'b0100001111100000;
68: y = 16'b0011111110100100;
69: y = 16'b0011101101010001;
70: y = 16'b0011011011100110;
71: y = 16'b0011001001100111;
72: y = 16'b0010110111010101;
73: y = 16'b0010100100110001;
74: y = 16'b0010010001111110;
75: y = 16'b0001111110111100;
76: y = 16'b0001101011101111;
77: y = 16'b0001011000010111;
78: y = 16'b0001000100110111;
79: y = 16'b0000110001010001;
80: y = 16'b0000011101100110;
81: y = 16'b0000001001110111;
82: y = 16'b1111110110001001;
83: y = 16'b1111100010011010;
84: y = 16'b1111001110101111;
85: y = 16'b1110111011001001;
86: y = 16'b1110100111101001;
87: y = 16'b1110010100010001;
88: y = 16'b1110000001000100;
89: y = 16'b1101101110000010;
90: y = 16'b1101011011001111;
91: y = 16'b1101001000101011;
92: y = 16'b1100110110011001;
93: y = 16'b1100100100011010;
94: y = 16'b1100010010101111;
95: y = 16'b1100000001011100;
96: y = 16'b1011110000100000;
97: y = 16'b1011011111111111;
98: y = 16'b1011001111111000;
99: y = 16'b1011000000001111;
100: y = 16'b1010110001000100;
101: y = 16'b1010100010011001;
102: y = 16'b1010010100001111;
103: y = 16'b1010000110101000;
104: y = 16'b1001111001100100;
105: y = 16'b1001101101000110;
106: y = 16'b1001100001001110;
107: y = 16'b1001010101111101;
108: y = 16'b1001001011010101;
109: y = 16'b1001000001010111;
110: y = 16'b1000111000000011;
111: y = 16'b1000101111011010;
112: y = 16'b1000100111011110;
113: y = 16'b1000100000001110;
114: y = 16'b1000011001101100;
115: y = 16'b1000010011111000;
116: y = 16'b1000001110110011;
117: y = 16'b1000001010011110;
118: y = 16'b1000000110111000;
119: y = 16'b1000000100000010;
120: y = 16'b1000000001111100;
121: y = 16'b1000000000100111;
122: y = 16'b1000000000000011;
123: y = 16'b1000000000001111;
124: y = 16'b1000000001001100;
125: y = 16'b1000000010111001;
126: y = 16'b1000000101010111;
127: y = 16'b1000001000100101;
128: y = 16'b1000001100100011;
129: y = 16'b1000010001010000;
130: y = 16'b1000010110101100;
131: y = 16'b1000011100110111;
132: y = 16'b1000100011110000;
133: y = 16'b1000101011010110;
134: y = 16'b1000110011101001;
135: y = 16'b1000111100100111;
136: y = 16'b1001000110010001;
137: y = 16'b1001010000100100;
138: y = 16'b1001011011100001;
139: y = 16'b1001100111000101;
140: y = 16'b1001110011010000;
141: y = 16'b1010000000000001;
142: y = 16'b1010001101010111;
143: y = 16'b1010011011010000;
144: y = 16'b1010101001101010;
145: y = 16'b1010111000100101;
146: y = 16'b1011001000000000;
147: y = 16'b1011010111111000;
148: y = 16'b1011101000001100;
149: y = 16'b1011111000111011;
150: y = 16'b1100001010000011;
151: y = 16'b1100011011100010;
152: y = 16'b1100101101010111;
153: y = 16'b1100111111100000;
154: y = 16'b1101010001111011;
155: y = 16'b1101100100100111;
156: y = 16'b1101110111100001;
157: y = 16'b1110001010101001;
158: y = 16'b1110011101111100;
159: y = 16'b1110110001011000;
160: y = 16'b1111000100111011;
161: y = 16'b1111011000100100;
162: y = 16'b1111101100010001;
default: y = 16'b0;
endcase
endmodule |
module lut_Ds
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 153;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010100111001;
2: y = 16'b0000101001101111;
3: y = 16'b0000111110100001;
4: y = 16'b0001010011001100;
5: y = 16'b0001100111101110;
6: y = 16'b0001111100000101;
7: y = 16'b0010010000010000;
8: y = 16'b0010100100001010;
9: y = 16'b0010110111110011;
10: y = 16'b0011001011001001;
11: y = 16'b0011011110001001;
12: y = 16'b0011110000110001;
13: y = 16'b0100000011000000;
14: y = 16'b0100010100110011;
15: y = 16'b0100100110001001;
16: y = 16'b0100110110111111;
17: y = 16'b0101000111010100;
18: y = 16'b0101010111000110;
19: y = 16'b0101100110010100;
20: y = 16'b0101110100111100;
21: y = 16'b0110000010111100;
22: y = 16'b0110010000010010;
23: y = 16'b0110011100111110;
24: y = 16'b0110101000111110;
25: y = 16'b0110110100010001;
26: y = 16'b0110111110110101;
27: y = 16'b0111001000101010;
28: y = 16'b0111010001101110;
29: y = 16'b0111011010000000;
30: y = 16'b0111100001100000;
31: y = 16'b0111101000001101;
32: y = 16'b0111101110000101;
33: y = 16'b0111110011001001;
34: y = 16'b0111110111011000;
35: y = 16'b0111111010110001;
36: y = 16'b0111111101010101;
37: y = 16'b0111111111000010;
38: y = 16'b0111111111111000;
39: y = 16'b0111111111111000;
40: y = 16'b0111111111000010;
41: y = 16'b0111111101010101;
42: y = 16'b0111111010110001;
43: y = 16'b0111110111011000;
44: y = 16'b0111110011001001;
45: y = 16'b0111101110000101;
46: y = 16'b0111101000001101;
47: y = 16'b0111100001100000;
48: y = 16'b0111011010000000;
49: y = 16'b0111010001101110;
50: y = 16'b0111001000101010;
51: y = 16'b0110111110110101;
52: y = 16'b0110110100010001;
53: y = 16'b0110101000111110;
54: y = 16'b0110011100111110;
55: y = 16'b0110010000010010;
56: y = 16'b0110000010111100;
57: y = 16'b0101110100111100;
58: y = 16'b0101100110010100;
59: y = 16'b0101010111000110;
60: y = 16'b0101000111010100;
61: y = 16'b0100110110111111;
62: y = 16'b0100100110001001;
63: y = 16'b0100010100110011;
64: y = 16'b0100000011000000;
65: y = 16'b0011110000110001;
66: y = 16'b0011011110001001;
67: y = 16'b0011001011001001;
68: y = 16'b0010110111110011;
69: y = 16'b0010100100001010;
70: y = 16'b0010010000010000;
71: y = 16'b0001111100000101;
72: y = 16'b0001100111101110;
73: y = 16'b0001010011001100;
74: y = 16'b0000111110100001;
75: y = 16'b0000101001101111;
76: y = 16'b0000010100111001;
77: y = 16'b0000000000000000;
78: y = 16'b1111101011000111;
79: y = 16'b1111010110010001;
80: y = 16'b1111000001011111;
81: y = 16'b1110101100110100;
82: y = 16'b1110011000010010;
83: y = 16'b1110000011111011;
84: y = 16'b1101101111110000;
85: y = 16'b1101011011110110;
86: y = 16'b1101001000001101;
87: y = 16'b1100110100110111;
88: y = 16'b1100100001110111;
89: y = 16'b1100001111001111;
90: y = 16'b1011111101000000;
91: y = 16'b1011101011001101;
92: y = 16'b1011011001110111;
93: y = 16'b1011001001000001;
94: y = 16'b1010111000101100;
95: y = 16'b1010101000111010;
96: y = 16'b1010011001101100;
97: y = 16'b1010001011000100;
98: y = 16'b1001111101000100;
99: y = 16'b1001101111101110;
100: y = 16'b1001100011000010;
101: y = 16'b1001010111000010;
102: y = 16'b1001001011101111;
103: y = 16'b1001000001001011;
104: y = 16'b1000110111010110;
105: y = 16'b1000101110010010;
106: y = 16'b1000100110000000;
107: y = 16'b1000011110100000;
108: y = 16'b1000010111110011;
109: y = 16'b1000010001111011;
110: y = 16'b1000001100110111;
111: y = 16'b1000001000101000;
112: y = 16'b1000000101001111;
113: y = 16'b1000000010101011;
114: y = 16'b1000000000111110;
115: y = 16'b1000000000001000;
116: y = 16'b1000000000001000;
117: y = 16'b1000000000111110;
118: y = 16'b1000000010101011;
119: y = 16'b1000000101001111;
120: y = 16'b1000001000101000;
121: y = 16'b1000001100110111;
122: y = 16'b1000010001111011;
123: y = 16'b1000010111110011;
124: y = 16'b1000011110100000;
125: y = 16'b1000100110000000;
126: y = 16'b1000101110010010;
127: y = 16'b1000110111010110;
128: y = 16'b1001000001001011;
129: y = 16'b1001001011101111;
130: y = 16'b1001010111000010;
131: y = 16'b1001100011000010;
132: y = 16'b1001101111101110;
133: y = 16'b1001111101000100;
134: y = 16'b1010001011000100;
135: y = 16'b1010011001101100;
136: y = 16'b1010101000111010;
137: y = 16'b1010111000101100;
138: y = 16'b1011001001000001;
139: y = 16'b1011011001110111;
140: y = 16'b1011101011001101;
141: y = 16'b1011111101000000;
142: y = 16'b1100001111001111;
143: y = 16'b1100100001110111;
144: y = 16'b1100110100110111;
145: y = 16'b1101001000001101;
146: y = 16'b1101011011110110;
147: y = 16'b1101101111110000;
148: y = 16'b1110000011111011;
149: y = 16'b1110011000010010;
150: y = 16'b1110101100110100;
151: y = 16'b1111000001011111;
152: y = 16'b1111010110010001;
153: y = 16'b1111101011000111;
default: y = 16'b0;
endcase
endmodule |
module lut_E
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 144;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010110001011;
2: y = 16'b0000101100010100;
3: y = 16'b0001000010011000;
4: y = 16'b0001011000010011;
5: y = 16'b0001101110000100;
6: y = 16'b0010000011101000;
7: y = 16'b0010011000111011;
8: y = 16'b0010101101111101;
9: y = 16'b0011000010101001;
10: y = 16'b0011010110111111;
11: y = 16'b0011101010111010;
12: y = 16'b0011111110011001;
13: y = 16'b0100010001011001;
14: y = 16'b0100100011111001;
15: y = 16'b0100110101110110;
16: y = 16'b0101000111001101;
17: y = 16'b0101010111111101;
18: y = 16'b0101101000000100;
19: y = 16'b0101110111011111;
20: y = 16'b0110000110001110;
21: y = 16'b0110010100001101;
22: y = 16'b0110100001011100;
23: y = 16'b0110101101111001;
24: y = 16'b0110111001100010;
25: y = 16'b0111000100010110;
26: y = 16'b0111001110010100;
27: y = 16'b0111010111011010;
28: y = 16'b0111011111100111;
29: y = 16'b0111100110111011;
30: y = 16'b0111101101010101;
31: y = 16'b0111110010110011;
32: y = 16'b0111110111010101;
33: y = 16'b0111111010111011;
34: y = 16'b0111111101100011;
35: y = 16'b0111111111001111;
36: y = 16'b0111111111111101;
37: y = 16'b0111111111101110;
38: y = 16'b0111111110100001;
39: y = 16'b0111111100010111;
40: y = 16'b0111111001001111;
41: y = 16'b0111110101001011;
42: y = 16'b0111110000001011;
43: y = 16'b0111101010001111;
44: y = 16'b0111100011011001;
45: y = 16'b0111011011101000;
46: y = 16'b0111010010111110;
47: y = 16'b0111001001011100;
48: y = 16'b0110111111000011;
49: y = 16'b0110110011110100;
50: y = 16'b0110100111110001;
51: y = 16'b0110011010111011;
52: y = 16'b0110001101010011;
53: y = 16'b0101111110111100;
54: y = 16'b0101101111110111;
55: y = 16'b0101100000000110;
56: y = 16'b0101001111101010;
57: y = 16'b0100111110100110;
58: y = 16'b0100101100111100;
59: y = 16'b0100011010101110;
60: y = 16'b0100000111111101;
61: y = 16'b0011110100101101;
62: y = 16'b0011100001000000;
63: y = 16'b0011001100110111;
64: y = 16'b0010111000010110;
65: y = 16'b0010100011011111;
66: y = 16'b0010001110010100;
67: y = 16'b0001111000111000;
68: y = 16'b0001100011001101;
69: y = 16'b0001001101010111;
70: y = 16'b0000110111010111;
71: y = 16'b0000100001010000;
72: y = 16'b0000001011000110;
73: y = 16'b1111110100111010;
74: y = 16'b1111011110110000;
75: y = 16'b1111001000101001;
76: y = 16'b1110110010101001;
77: y = 16'b1110011100110011;
78: y = 16'b1110000111001000;
79: y = 16'b1101110001101100;
80: y = 16'b1101011100100001;
81: y = 16'b1101000111101010;
82: y = 16'b1100110011001001;
83: y = 16'b1100011111000000;
84: y = 16'b1100001011010011;
85: y = 16'b1011111000000011;
86: y = 16'b1011100101010010;
87: y = 16'b1011010011000100;
88: y = 16'b1011000001011010;
89: y = 16'b1010110000010110;
90: y = 16'b1010011111111010;
91: y = 16'b1010010000001001;
92: y = 16'b1010000001000100;
93: y = 16'b1001110010101101;
94: y = 16'b1001100101000101;
95: y = 16'b1001011000001111;
96: y = 16'b1001001100001100;
97: y = 16'b1001000000111101;
98: y = 16'b1000110110100100;
99: y = 16'b1000101101000010;
100: y = 16'b1000100100011000;
101: y = 16'b1000011100100111;
102: y = 16'b1000010101110001;
103: y = 16'b1000001111110101;
104: y = 16'b1000001010110101;
105: y = 16'b1000000110110001;
106: y = 16'b1000000011101001;
107: y = 16'b1000000001011111;
108: y = 16'b1000000000010010;
109: y = 16'b1000000000000011;
110: y = 16'b1000000000110001;
111: y = 16'b1000000010011101;
112: y = 16'b1000000101000101;
113: y = 16'b1000001000101011;
114: y = 16'b1000001101001101;
115: y = 16'b1000010010101011;
116: y = 16'b1000011001000101;
117: y = 16'b1000100000011001;
118: y = 16'b1000101000100110;
119: y = 16'b1000110001101100;
120: y = 16'b1000111011101010;
121: y = 16'b1001000110011110;
122: y = 16'b1001010010000111;
123: y = 16'b1001011110100100;
124: y = 16'b1001101011110011;
125: y = 16'b1001111001110010;
126: y = 16'b1010001000100001;
127: y = 16'b1010010111111100;
128: y = 16'b1010101000000011;
129: y = 16'b1010111000110011;
130: y = 16'b1011001010001010;
131: y = 16'b1011011100000111;
132: y = 16'b1011101110100111;
133: y = 16'b1100000001100111;
134: y = 16'b1100010101000110;
135: y = 16'b1100101001000001;
136: y = 16'b1100111101010111;
137: y = 16'b1101010010000011;
138: y = 16'b1101100111000101;
139: y = 16'b1101111100011000;
140: y = 16'b1110010001111100;
141: y = 16'b1110100111101101;
142: y = 16'b1110111101101000;
143: y = 16'b1111010011101100;
144: y = 16'b1111101001110101;
default: y = 16'b0;
endcase
endmodule |
module lut_F
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 136;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010111011110;
2: y = 16'b0000101110111001;
3: y = 16'b0001000110001110;
4: y = 16'b0001011101011001;
5: y = 16'b0001110100011000;
6: y = 16'b0010001011000111;
7: y = 16'b0010100001100100;
8: y = 16'b0010110111101010;
9: y = 16'b0011001101011000;
10: y = 16'b0011100010101011;
11: y = 16'b0011110111011110;
12: y = 16'b0100001011110001;
13: y = 16'b0100011111011111;
14: y = 16'b0100110010100111;
15: y = 16'b0101000101000101;
16: y = 16'b0101010110111000;
17: y = 16'b0101100111111101;
18: y = 16'b0101111000010001;
19: y = 16'b0110000111110010;
20: y = 16'b0110010110011111;
21: y = 16'b0110100100010101;
22: y = 16'b0110110001010010;
23: y = 16'b0110111101010101;
24: y = 16'b0111001000011101;
25: y = 16'b0111010010100110;
26: y = 16'b0111011011110001;
27: y = 16'b0111100011111100;
28: y = 16'b0111101011000110;
29: y = 16'b0111110001001110;
30: y = 16'b0111110110010011;
31: y = 16'b0111111010010100;
32: y = 16'b0111111101010001;
33: y = 16'b0111111111001001;
34: y = 16'b0111111111111101;
35: y = 16'b0111111111101100;
36: y = 16'b0111111110010110;
37: y = 16'b0111111011111011;
38: y = 16'b0111111000011100;
39: y = 16'b0111110011111001;
40: y = 16'b0111101110010010;
41: y = 16'b0111100111101001;
42: y = 16'b0111011111111111;
43: y = 16'b0111010111010100;
44: y = 16'b0111001101101001;
45: y = 16'b0111000011000001;
46: y = 16'b0110110111011011;
47: y = 16'b0110101010111011;
48: y = 16'b0110011101100001;
49: y = 16'b0110001111001111;
50: y = 16'b0110000000001000;
51: y = 16'b0101110000001101;
52: y = 16'b0101011111100000;
53: y = 16'b0101001110000100;
54: y = 16'b0100111011111011;
55: y = 16'b0100101001001000;
56: y = 16'b0100010101101101;
57: y = 16'b0100000001101100;
58: y = 16'b0011101101001000;
59: y = 16'b0011011000000101;
60: y = 16'b0011000010100101;
61: y = 16'b0010101100101010;
62: y = 16'b0010010110011000;
63: y = 16'b0001111111110010;
64: y = 16'b0001101000111011;
65: y = 16'b0001010001110101;
66: y = 16'b0000111010100101;
67: y = 16'b0000100011001100;
68: y = 16'b0000001011101111;
69: y = 16'b1111110100010001;
70: y = 16'b1111011100110100;
71: y = 16'b1111000101011011;
72: y = 16'b1110101110001011;
73: y = 16'b1110010111000101;
74: y = 16'b1110000000001110;
75: y = 16'b1101101001101000;
76: y = 16'b1101010011010110;
77: y = 16'b1100111101011011;
78: y = 16'b1100100111111011;
79: y = 16'b1100010010111000;
80: y = 16'b1011111110010100;
81: y = 16'b1011101010010011;
82: y = 16'b1011010110111000;
83: y = 16'b1011000100000101;
84: y = 16'b1010110001111100;
85: y = 16'b1010100000100000;
86: y = 16'b1010001111110011;
87: y = 16'b1001111111111000;
88: y = 16'b1001110000110001;
89: y = 16'b1001100010011111;
90: y = 16'b1001010101000101;
91: y = 16'b1001001000100101;
92: y = 16'b1000111100111111;
93: y = 16'b1000110010010111;
94: y = 16'b1000101000101100;
95: y = 16'b1000100000000001;
96: y = 16'b1000011000010111;
97: y = 16'b1000010001101110;
98: y = 16'b1000001100000111;
99: y = 16'b1000000111100100;
100: y = 16'b1000000100000101;
101: y = 16'b1000000001101010;
102: y = 16'b1000000000010100;
103: y = 16'b1000000000000011;
104: y = 16'b1000000000110111;
105: y = 16'b1000000010101111;
106: y = 16'b1000000101101100;
107: y = 16'b1000001001101101;
108: y = 16'b1000001110110010;
109: y = 16'b1000010100111010;
110: y = 16'b1000011100000100;
111: y = 16'b1000100100001111;
112: y = 16'b1000101101011010;
113: y = 16'b1000110111100011;
114: y = 16'b1001000010101011;
115: y = 16'b1001001110101110;
116: y = 16'b1001011011101011;
117: y = 16'b1001101001100001;
118: y = 16'b1001111000001110;
119: y = 16'b1010000111101111;
120: y = 16'b1010011000000011;
121: y = 16'b1010101001001000;
122: y = 16'b1010111010111011;
123: y = 16'b1011001101011001;
124: y = 16'b1011100000100001;
125: y = 16'b1011110100001111;
126: y = 16'b1100001000100010;
127: y = 16'b1100011101010101;
128: y = 16'b1100110010101000;
129: y = 16'b1101001000010110;
130: y = 16'b1101011110011100;
131: y = 16'b1101110100111001;
132: y = 16'b1110001011101000;
133: y = 16'b1110100010100111;
134: y = 16'b1110111001110010;
135: y = 16'b1111010001000111;
136: y = 16'b1111101000100010;
default: y = 16'b0;
endcase
endmodule |
module lut_Fs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 128;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011000111011;
2: y = 16'b0000110001110011;
3: y = 16'b0001001010100011;
4: y = 16'b0001100011001000;
5: y = 16'b0001111011011101;
6: y = 16'b0010010011100000;
7: y = 16'b0010101011001101;
8: y = 16'b0011000010011111;
9: y = 16'b0011011001010100;
10: y = 16'b0011101111101000;
11: y = 16'b0100000101011000;
12: y = 16'b0100011010100000;
13: y = 16'b0100101110111101;
14: y = 16'b0101000010101100;
15: y = 16'b0101010101101010;
16: y = 16'b0101100111110100;
17: y = 16'b0101111001001000;
18: y = 16'b0110001001100010;
19: y = 16'b0110011001000001;
20: y = 16'b0110100111100001;
21: y = 16'b0110110101000010;
22: y = 16'b0111000001100000;
23: y = 16'b0111001100111001;
24: y = 16'b0111010111001101;
25: y = 16'b0111100000011001;
26: y = 16'b0111101000011100;
27: y = 16'b0111101111010110;
28: y = 16'b0111110101000011;
29: y = 16'b0111111001100101;
30: y = 16'b0111111100111010;
31: y = 16'b0111111111000010;
32: y = 16'b0111111111111101;
33: y = 16'b0111111111101001;
34: y = 16'b0111111110001000;
35: y = 16'b0111111011011010;
36: y = 16'b0111110111011110;
37: y = 16'b0111110010010110;
38: y = 16'b0111101100000010;
39: y = 16'b0111100100100100;
40: y = 16'b0111011011111100;
41: y = 16'b0111010010001100;
42: y = 16'b0111000111010101;
43: y = 16'b0110111011011001;
44: y = 16'b0110101110011010;
45: y = 16'b0110100000011001;
46: y = 16'b0110010001011001;
47: y = 16'b0110000001011100;
48: y = 16'b0101110000100101;
49: y = 16'b0101011110110110;
50: y = 16'b0101001100010001;
51: y = 16'b0100111000111010;
52: y = 16'b0100100100110100;
53: y = 16'b0100010000000001;
54: y = 16'b0011111010100101;
55: y = 16'b0011100100100011;
56: y = 16'b0011001101111110;
57: y = 16'b0010110110111001;
58: y = 16'b0010011111011001;
59: y = 16'b0010000111100001;
60: y = 16'b0001101111010101;
61: y = 16'b0001010110110111;
62: y = 16'b0000111110001100;
63: y = 16'b0000100101011000;
64: y = 16'b0000001100011110;
65: y = 16'b1111110011100010;
66: y = 16'b1111011010101000;
67: y = 16'b1111000001110100;
68: y = 16'b1110101001001001;
69: y = 16'b1110010000101011;
70: y = 16'b1101111000011111;
71: y = 16'b1101100000100111;
72: y = 16'b1101001001000111;
73: y = 16'b1100110010000010;
74: y = 16'b1100011011011101;
75: y = 16'b1100000101011011;
76: y = 16'b1011101111111111;
77: y = 16'b1011011011001100;
78: y = 16'b1011000111000110;
79: y = 16'b1010110011101111;
80: y = 16'b1010100001001010;
81: y = 16'b1010001111011011;
82: y = 16'b1001111110100100;
83: y = 16'b1001101110100111;
84: y = 16'b1001011111100111;
85: y = 16'b1001010001100110;
86: y = 16'b1001000100100111;
87: y = 16'b1000111000101011;
88: y = 16'b1000101101110100;
89: y = 16'b1000100100000100;
90: y = 16'b1000011011011100;
91: y = 16'b1000010011111110;
92: y = 16'b1000001101101010;
93: y = 16'b1000001000100010;
94: y = 16'b1000000100100110;
95: y = 16'b1000000001111000;
96: y = 16'b1000000000010111;
97: y = 16'b1000000000000011;
98: y = 16'b1000000000111110;
99: y = 16'b1000000011000110;
100: y = 16'b1000000110011011;
101: y = 16'b1000001010111101;
102: y = 16'b1000010000101010;
103: y = 16'b1000010111100100;
104: y = 16'b1000011111100111;
105: y = 16'b1000101000110011;
106: y = 16'b1000110011000111;
107: y = 16'b1000111110100000;
108: y = 16'b1001001010111110;
109: y = 16'b1001011000011111;
110: y = 16'b1001100110111111;
111: y = 16'b1001110110011110;
112: y = 16'b1010000110111000;
113: y = 16'b1010011000001100;
114: y = 16'b1010101010010110;
115: y = 16'b1010111101010100;
116: y = 16'b1011010001000011;
117: y = 16'b1011100101100000;
118: y = 16'b1011111010101000;
119: y = 16'b1100010000011000;
120: y = 16'b1100100110101100;
121: y = 16'b1100111101100001;
122: y = 16'b1101010100110011;
123: y = 16'b1101101100100000;
124: y = 16'b1110000100100011;
125: y = 16'b1110011100111000;
126: y = 16'b1110110101011101;
127: y = 16'b1111001110001101;
128: y = 16'b1111100111000101;
default: y = 16'b0;
endcase
endmodule |
module lut_G
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 121;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011010010111;
2: y = 16'b0000110100101001;
3: y = 16'b0001001110110011;
4: y = 16'b0001101000101111;
5: y = 16'b0010000010011001;
6: y = 16'b0010011011101101;
7: y = 16'b0010110100100111;
8: y = 16'b0011001101000010;
9: y = 16'b0011100100111010;
10: y = 16'b0011111100001011;
11: y = 16'b0100010010110010;
12: y = 16'b0100101000101010;
13: y = 16'b0100111101110000;
14: y = 16'b0101010001111111;
15: y = 16'b0101100101010110;
16: y = 16'b0101110111101111;
17: y = 16'b0110001001001001;
18: y = 16'b0110011001100000;
19: y = 16'b0110101000110010;
20: y = 16'b0110110110111100;
21: y = 16'b0111000011111011;
22: y = 16'b0111001111101101;
23: y = 16'b0111011010010001;
24: y = 16'b0111100011100100;
25: y = 16'b0111101011100101;
26: y = 16'b0111110010010011;
27: y = 16'b0111110111101100;
28: y = 16'b0111111011110000;
29: y = 16'b0111111110011101;
30: y = 16'b0111111111110100;
31: y = 16'b0111111111110100;
32: y = 16'b0111111110011101;
33: y = 16'b0111111011110000;
34: y = 16'b0111110111101100;
35: y = 16'b0111110010010011;
36: y = 16'b0111101011100101;
37: y = 16'b0111100011100100;
38: y = 16'b0111011010010001;
39: y = 16'b0111001111101101;
40: y = 16'b0111000011111011;
41: y = 16'b0110110110111100;
42: y = 16'b0110101000110010;
43: y = 16'b0110011001100000;
44: y = 16'b0110001001001001;
45: y = 16'b0101110111101111;
46: y = 16'b0101100101010110;
47: y = 16'b0101010001111111;
48: y = 16'b0100111101110000;
49: y = 16'b0100101000101010;
50: y = 16'b0100010010110010;
51: y = 16'b0011111100001011;
52: y = 16'b0011100100111010;
53: y = 16'b0011001101000010;
54: y = 16'b0010110100100111;
55: y = 16'b0010011011101101;
56: y = 16'b0010000010011001;
57: y = 16'b0001101000101111;
58: y = 16'b0001001110110011;
59: y = 16'b0000110100101001;
60: y = 16'b0000011010010111;
61: y = 16'b0000000000000000;
62: y = 16'b1111100101101001;
63: y = 16'b1111001011010111;
64: y = 16'b1110110001001101;
65: y = 16'b1110010111010001;
66: y = 16'b1101111101100111;
67: y = 16'b1101100100010011;
68: y = 16'b1101001011011001;
69: y = 16'b1100110010111110;
70: y = 16'b1100011011000110;
71: y = 16'b1100000011110101;
72: y = 16'b1011101101001110;
73: y = 16'b1011010111010110;
74: y = 16'b1011000010010000;
75: y = 16'b1010101110000001;
76: y = 16'b1010011010101010;
77: y = 16'b1010001000010001;
78: y = 16'b1001110110110111;
79: y = 16'b1001100110100000;
80: y = 16'b1001010111001110;
81: y = 16'b1001001001000100;
82: y = 16'b1000111100000101;
83: y = 16'b1000110000010011;
84: y = 16'b1000100101101111;
85: y = 16'b1000011100011100;
86: y = 16'b1000010100011011;
87: y = 16'b1000001101101101;
88: y = 16'b1000001000010100;
89: y = 16'b1000000100010000;
90: y = 16'b1000000001100011;
91: y = 16'b1000000000001100;
92: y = 16'b1000000000001100;
93: y = 16'b1000000001100011;
94: y = 16'b1000000100010000;
95: y = 16'b1000001000010100;
96: y = 16'b1000001101101101;
97: y = 16'b1000010100011011;
98: y = 16'b1000011100011100;
99: y = 16'b1000100101101111;
100: y = 16'b1000110000010011;
101: y = 16'b1000111100000101;
102: y = 16'b1001001001000100;
103: y = 16'b1001010111001110;
104: y = 16'b1001100110100000;
105: y = 16'b1001110110110111;
106: y = 16'b1010001000010001;
107: y = 16'b1010011010101010;
108: y = 16'b1010101110000001;
109: y = 16'b1011000010010000;
110: y = 16'b1011010111010110;
111: y = 16'b1011101101001110;
112: y = 16'b1100000011110101;
113: y = 16'b1100011011000110;
114: y = 16'b1100110010111110;
115: y = 16'b1101001011011001;
116: y = 16'b1101100100010011;
117: y = 16'b1101111101100111;
118: y = 16'b1110010111010001;
119: y = 16'b1110110001001101;
120: y = 16'b1111001011010111;
121: y = 16'b1111100101101001;
default: y = 16'b0;
endcase
endmodule |
module lut_Gs
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 114;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011011111101;
2: y = 16'b0000110111110101;
3: y = 16'b0001010011100011;
4: y = 16'b0001101111000000;
5: y = 16'b0010001010001000;
6: y = 16'b0010100100110110;
7: y = 16'b0010111111000101;
8: y = 16'b0011011000101110;
9: y = 16'b0011110001101111;
10: y = 16'b0100001010000001;
11: y = 16'b0100100001100001;
12: y = 16'b0100111000001001;
13: y = 16'b0101001101110101;
14: y = 16'b0101100010100010;
15: y = 16'b0101110110001011;
16: y = 16'b0110001000101101;
17: y = 16'b0110011010000100;
18: y = 16'b0110101010001100;
19: y = 16'b0110111001000011;
20: y = 16'b0111000110100101;
21: y = 16'b0111010010110001;
22: y = 16'b0111011101100100;
23: y = 16'b0111100110111011;
24: y = 16'b0111101110110110;
25: y = 16'b0111110101010010;
26: y = 16'b0111111010001110;
27: y = 16'b0111111101101001;
28: y = 16'b0111111111100011;
29: y = 16'b0111111111111100;
30: y = 16'b0111111110110011;
31: y = 16'b0111111100001000;
32: y = 16'b0111110111111100;
33: y = 16'b0111110010010000;
34: y = 16'b0111101011000100;
35: y = 16'b0111100010011011;
36: y = 16'b0111011000010110;
37: y = 16'b0111001100110110;
38: y = 16'b0110111111111111;
39: y = 16'b0110110001110010;
40: y = 16'b0110100010010010;
41: y = 16'b0110010001100010;
42: y = 16'b0101111111100101;
43: y = 16'b0101101100011111;
44: y = 16'b0101011000010100;
45: y = 16'b0101000011000111;
46: y = 16'b0100101100111100;
47: y = 16'b0100010101111000;
48: y = 16'b0011111101111110;
49: y = 16'b0011100101010100;
50: y = 16'b0011001011111110;
51: y = 16'b0010110010000010;
52: y = 16'b0010010111100011;
53: y = 16'b0001111100100111;
54: y = 16'b0001100001010100;
55: y = 16'b0001000101101110;
56: y = 16'b0000101001111010;
57: y = 16'b0000001101111111;
58: y = 16'b1111110010000001;
59: y = 16'b1111010110000110;
60: y = 16'b1110111010010010;
61: y = 16'b1110011110101100;
62: y = 16'b1110000011011001;
63: y = 16'b1101101000011101;
64: y = 16'b1101001101111110;
65: y = 16'b1100110100000010;
66: y = 16'b1100011010101100;
67: y = 16'b1100000010000010;
68: y = 16'b1011101010001000;
69: y = 16'b1011010011000100;
70: y = 16'b1010111100111001;
71: y = 16'b1010100111101100;
72: y = 16'b1010010011100001;
73: y = 16'b1010000000011011;
74: y = 16'b1001101110011110;
75: y = 16'b1001011101101110;
76: y = 16'b1001001110001110;
77: y = 16'b1001000000000001;
78: y = 16'b1000110011001010;
79: y = 16'b1000100111101010;
80: y = 16'b1000011101100101;
81: y = 16'b1000010100111100;
82: y = 16'b1000001101110000;
83: y = 16'b1000001000000100;
84: y = 16'b1000000011111000;
85: y = 16'b1000000001001101;
86: y = 16'b1000000000000100;
87: y = 16'b1000000000011101;
88: y = 16'b1000000010010111;
89: y = 16'b1000000101110010;
90: y = 16'b1000001010101110;
91: y = 16'b1000010001001010;
92: y = 16'b1000011001000101;
93: y = 16'b1000100010011100;
94: y = 16'b1000101101001111;
95: y = 16'b1000111001011011;
96: y = 16'b1001000110111101;
97: y = 16'b1001010101110100;
98: y = 16'b1001100101111100;
99: y = 16'b1001110111010011;
100: y = 16'b1010001001110101;
101: y = 16'b1010011101011110;
102: y = 16'b1010110010001011;
103: y = 16'b1011000111110111;
104: y = 16'b1011011110011111;
105: y = 16'b1011110101111111;
106: y = 16'b1100001110010001;
107: y = 16'b1100100111010010;
108: y = 16'b1101000000111011;
109: y = 16'b1101011011001010;
110: y = 16'b1101110101111000;
111: y = 16'b1110010001000000;
112: y = 16'b1110101100011101;
113: y = 16'b1111001000001011;
114: y = 16'b1111100100000011;
default: y = 16'b0;
endcase
endmodule |
module lut_A
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 108;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011101100000;
2: y = 16'b0000111010111001;
3: y = 16'b0001011000000110;
4: y = 16'b0001110101000001;
5: y = 16'b0010010001100010;
6: y = 16'b0010101101100100;
7: y = 16'b0011001001000010;
8: y = 16'b0011100011110101;
9: y = 16'b0011111101110111;
10: y = 16'b0100010111000011;
11: y = 16'b0100101111010100;
12: y = 16'b0101000110100101;
13: y = 16'b0101011100110000;
14: y = 16'b0101110001110001;
15: y = 16'b0110000101100100;
16: y = 16'b0110011000000011;
17: y = 16'b0110101001001100;
18: y = 16'b0110111000111010;
19: y = 16'b0111000111001011;
20: y = 16'b0111010011111011;
21: y = 16'b0111011111000111;
22: y = 16'b0111101000101110;
23: y = 16'b0111110000101101;
24: y = 16'b0111110111000010;
25: y = 16'b0111111011101100;
26: y = 16'b0111111110101010;
27: y = 16'b0111111111111100;
28: y = 16'b0111111111100000;
29: y = 16'b0111111101011000;
30: y = 16'b0111111001100100;
31: y = 16'b0111110100000100;
32: y = 16'b0111101100111010;
33: y = 16'b0111100100001000;
34: y = 16'b0111011001101110;
35: y = 16'b0111001101101111;
36: y = 16'b0111000000001111;
37: y = 16'b0110110001001111;
38: y = 16'b0110100000110011;
39: y = 16'b0110001110111110;
40: y = 16'b0101111011110100;
41: y = 16'b0101100111011010;
42: y = 16'b0101010001110100;
43: y = 16'b0100111011000101;
44: y = 16'b0100100011010100;
45: y = 16'b0100001010100100;
46: y = 16'b0011110000111100;
47: y = 16'b0011010110100001;
48: y = 16'b0010111011011000;
49: y = 16'b0010011111100111;
50: y = 16'b0010000011010101;
51: y = 16'b0001100110100110;
52: y = 16'b0001001001100010;
53: y = 16'b0000101100001110;
54: y = 16'b0000001110110000;
55: y = 16'b1111110001010000;
56: y = 16'b1111010011110010;
57: y = 16'b1110110110011110;
58: y = 16'b1110011001011010;
59: y = 16'b1101111100101011;
60: y = 16'b1101100000011001;
61: y = 16'b1101000100101000;
62: y = 16'b1100101001011111;
63: y = 16'b1100001111000100;
64: y = 16'b1011110101011100;
65: y = 16'b1011011100101100;
66: y = 16'b1011000100111011;
67: y = 16'b1010101110001100;
68: y = 16'b1010011000100110;
69: y = 16'b1010000100001100;
70: y = 16'b1001110001000010;
71: y = 16'b1001011111001101;
72: y = 16'b1001001110110001;
73: y = 16'b1000111111110001;
74: y = 16'b1000110010010001;
75: y = 16'b1000100110010010;
76: y = 16'b1000011011111000;
77: y = 16'b1000010011000110;
78: y = 16'b1000001011111100;
79: y = 16'b1000000110011100;
80: y = 16'b1000000010101000;
81: y = 16'b1000000000100000;
82: y = 16'b1000000000000100;
83: y = 16'b1000000001010110;
84: y = 16'b1000000100010100;
85: y = 16'b1000001000111110;
86: y = 16'b1000001111010011;
87: y = 16'b1000010111010010;
88: y = 16'b1000100000111001;
89: y = 16'b1000101100000101;
90: y = 16'b1000111000110101;
91: y = 16'b1001000111000110;
92: y = 16'b1001010110110100;
93: y = 16'b1001100111111101;
94: y = 16'b1001111010011100;
95: y = 16'b1010001110001111;
96: y = 16'b1010100011010000;
97: y = 16'b1010111001011011;
98: y = 16'b1011010000101100;
99: y = 16'b1011101000111101;
100: y = 16'b1100000010001001;
101: y = 16'b1100011100001011;
102: y = 16'b1100110110111110;
103: y = 16'b1101010010011100;
104: y = 16'b1101101110011110;
105: y = 16'b1110001010111111;
106: y = 16'b1110100111111010;
107: y = 16'b1111000101000111;
108: y = 16'b1111100010100000;
default: y = 16'b0;
endcase
endmodule |
module lut_As
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 101;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011111100001;
2: y = 16'b0000111110111011;
3: y = 16'b0001011110000101;
4: y = 16'b0001111100111000;
5: y = 16'b0010011011001101;
6: y = 16'b0010111000111101;
7: y = 16'b0011010101111111;
8: y = 16'b0011110010001110;
9: y = 16'b0100001101100010;
10: y = 16'b0100100111110100;
11: y = 16'b0101000000111110;
12: y = 16'b0101011000111011;
13: y = 16'b0101101111100100;
14: y = 16'b0110000100110011;
15: y = 16'b0110011000100101;
16: y = 16'b0110101010110011;
17: y = 16'b0110111011011001;
18: y = 16'b0111001010010100;
19: y = 16'b0111010111011111;
20: y = 16'b0111100010111000;
21: y = 16'b0111101100011100;
22: y = 16'b0111110100001000;
23: y = 16'b0111111001111011;
24: y = 16'b0111111101110011;
25: y = 16'b0111111111101111;
26: y = 16'b0111111111101111;
27: y = 16'b0111111101110011;
28: y = 16'b0111111001111011;
29: y = 16'b0111110100001000;
30: y = 16'b0111101100011100;
31: y = 16'b0111100010111000;
32: y = 16'b0111010111011111;
33: y = 16'b0111001010010100;
34: y = 16'b0110111011011001;
35: y = 16'b0110101010110011;
36: y = 16'b0110011000100101;
37: y = 16'b0110000100110011;
38: y = 16'b0101101111100100;
39: y = 16'b0101011000111011;
40: y = 16'b0101000000111110;
41: y = 16'b0100100111110100;
42: y = 16'b0100001101100010;
43: y = 16'b0011110010001110;
44: y = 16'b0011010101111111;
45: y = 16'b0010111000111101;
46: y = 16'b0010011011001101;
47: y = 16'b0001111100111000;
48: y = 16'b0001011110000101;
49: y = 16'b0000111110111011;
50: y = 16'b0000011111100001;
51: y = 16'b0000000000000000;
52: y = 16'b1111100000011111;
53: y = 16'b1111000001000101;
54: y = 16'b1110100001111011;
55: y = 16'b1110000011001000;
56: y = 16'b1101100100110011;
57: y = 16'b1101000111000011;
58: y = 16'b1100101010000001;
59: y = 16'b1100001101110010;
60: y = 16'b1011110010011110;
61: y = 16'b1011011000001100;
62: y = 16'b1010111111000010;
63: y = 16'b1010100111000101;
64: y = 16'b1010010000011100;
65: y = 16'b1001111011001101;
66: y = 16'b1001100111011011;
67: y = 16'b1001010101001101;
68: y = 16'b1001000100100111;
69: y = 16'b1000110101101100;
70: y = 16'b1000101000100001;
71: y = 16'b1000011101001000;
72: y = 16'b1000010011100100;
73: y = 16'b1000001011111000;
74: y = 16'b1000000110000101;
75: y = 16'b1000000010001101;
76: y = 16'b1000000000010001;
77: y = 16'b1000000000010001;
78: y = 16'b1000000010001101;
79: y = 16'b1000000110000101;
80: y = 16'b1000001011111000;
81: y = 16'b1000010011100100;
82: y = 16'b1000011101001000;
83: y = 16'b1000101000100001;
84: y = 16'b1000110101101100;
85: y = 16'b1001000100100111;
86: y = 16'b1001010101001101;
87: y = 16'b1001100111011011;
88: y = 16'b1001111011001101;
89: y = 16'b1010010000011100;
90: y = 16'b1010100111000101;
91: y = 16'b1010111111000010;
92: y = 16'b1011011000001100;
93: y = 16'b1011110010011110;
94: y = 16'b1100001101110010;
95: y = 16'b1100101010000001;
96: y = 16'b1101000111000011;
97: y = 16'b1101100100110011;
98: y = 16'b1110000011001000;
99: y = 16'b1110100001111011;
100: y = 16'b1111000001000101;
101: y = 16'b1111100000011111;
default: y = 16'b0;
endcase
endmodule |
module lut_B
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 96;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000100001001001;
2: y = 16'b0001000010001001;
3: y = 16'b0001100010110111;
4: y = 16'b0010000011001011;
5: y = 16'b0010100010111100;
6: y = 16'b0011000010000001;
7: y = 16'b0011100000010010;
8: y = 16'b0011111101100110;
9: y = 16'b0100011001110111;
10: y = 16'b0100110100111011;
11: y = 16'b0101001110101101;
12: y = 16'b0101100111000101;
13: y = 16'b0101111101111101;
14: y = 16'b0110010011001110;
15: y = 16'b0110100110110011;
16: y = 16'b0110111000100111;
17: y = 16'b0111001000100100;
18: y = 16'b0111010110100110;
19: y = 16'b0111100010101010;
20: y = 16'b0111101100101101;
21: y = 16'b0111110100101100;
22: y = 16'b0111111010100100;
23: y = 16'b0111111110010100;
24: y = 16'b0111111111111011;
25: y = 16'b0111111111011000;
26: y = 16'b0111111100101101;
27: y = 16'b0111110111111001;
28: y = 16'b0111110000111101;
29: y = 16'b0111100111111100;
30: y = 16'b0111011100111000;
31: y = 16'b0111001111110101;
32: y = 16'b0111000000110100;
33: y = 16'b0110101111111011;
34: y = 16'b0110011101001111;
35: y = 16'b0110001000110011;
36: y = 16'b0101110010101110;
37: y = 16'b0101011011000101;
38: y = 16'b0101000001111111;
39: y = 16'b0100100111100011;
40: y = 16'b0100001011110111;
41: y = 16'b0011101111000100;
42: y = 16'b0011010001010000;
43: y = 16'b0010110010100100;
44: y = 16'b0010010011001001;
45: y = 16'b0001110011000101;
46: y = 16'b0001010010100011;
47: y = 16'b0000110001101011;
48: y = 16'b0000010000100101;
49: y = 16'b1111101111011011;
50: y = 16'b1111001110010101;
51: y = 16'b1110101101011101;
52: y = 16'b1110001100111011;
53: y = 16'b1101101100110111;
54: y = 16'b1101001101011100;
55: y = 16'b1100101110110000;
56: y = 16'b1100010000111100;
57: y = 16'b1011110100001001;
58: y = 16'b1011011000011101;
59: y = 16'b1010111110000001;
60: y = 16'b1010100100111011;
61: y = 16'b1010001101010010;
62: y = 16'b1001110111001101;
63: y = 16'b1001100010110001;
64: y = 16'b1001010000000101;
65: y = 16'b1000111111001100;
66: y = 16'b1000110000001011;
67: y = 16'b1000100011001000;
68: y = 16'b1000011000000100;
69: y = 16'b1000001111000011;
70: y = 16'b1000001000000111;
71: y = 16'b1000000011010011;
72: y = 16'b1000000000101000;
73: y = 16'b1000000000000101;
74: y = 16'b1000000001101100;
75: y = 16'b1000000101011100;
76: y = 16'b1000001011010100;
77: y = 16'b1000010011010011;
78: y = 16'b1000011101010110;
79: y = 16'b1000101001011010;
80: y = 16'b1000110111011100;
81: y = 16'b1001000111011001;
82: y = 16'b1001011001001101;
83: y = 16'b1001101100110010;
84: y = 16'b1010000010000011;
85: y = 16'b1010011000111011;
86: y = 16'b1010110001010011;
87: y = 16'b1011001011000101;
88: y = 16'b1011100110001001;
89: y = 16'b1100000010011010;
90: y = 16'b1100011111101110;
91: y = 16'b1100111101111111;
92: y = 16'b1101011101000100;
93: y = 16'b1101111100110101;
94: y = 16'b1110011101001001;
95: y = 16'b1110111101110111;
96: y = 16'b1111011110110111;
default: y = 16'b0;
endcase
endmodule |