{"task_id": "2012_q1g", "prompt": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q1g", "prompt": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1;\n\t\t\t4'h1: f = 1;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 0;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 0;\n\t\t\t4'hb: f = 0;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 0;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2b", "prompt": "module top_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n", "canonical_solution": "\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[5:0] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[5:4],temp[2:1]} == !{temp[3],temp[0]} );\t\n\t\t\t// Make y[3,0] and y[5,4,2,1] mutually exclusive, so we can accept Y3=(~y[3] & ~y[0]) &~w as a valid answer too.\n\n\t\t\ty <= temp;\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y1;\n\t\tint errortime_Y1;\n\t\tint errors_Y3;\n\t\tint errortime_Y3;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [5:0] y;\n\tlogic w;\n\tlogic Y1_ref;\n\tlogic Y1_dut;\n\tlogic Y3_ref;\n\tlogic Y3_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut,Y3_ref,Y3_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_ref),\n\t\t.Y3(Y3_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_dut),\n\t\t.Y3(Y3_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y1\", stats1.errors_Y1, stats1.errortime_Y1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y1\");\n\t\tif (stats1.errors_Y3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y3\", stats1.errors_Y3, stats1.errortime_Y3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y3\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y1_ref, Y3_ref } === ( { Y1_ref, Y3_ref } ^ { Y1_dut, Y3_dut } ^ { Y1_ref, Y3_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))\n\t\tbegin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;\n\t\t\tstats1.errors_Y1 = stats1.errors_Y1+1'b1; end\n\t\tif (Y3_ref !== ( Y3_ref ^ Y3_dut ^ Y3_ref ))\n\t\tbegin if (stats1.errors_Y3 == 0) stats1.errortime_Y3 = $time;\n\t\t\tstats1.errors_Y3 = stats1.errors_Y3+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2b", "prompt": "module top_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n", "canonical_solution": "\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [5:0] y,\n\tinput w,\n\toutput Y1,\n\toutput Y3\n);\n\tassign Y1 = y[0]&w;\n\tassign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[5:0] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[5:4],temp[2:1]} == !{temp[3],temp[0]} );\t\n\t\t\t// Make y[3,0] and y[5,4,2,1] mutually exclusive, so we can accept Y3=(~y[3] & ~y[0]) &~w as a valid answer too.\n\n\t\t\ty <= temp;\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y1;\n\t\tint errortime_Y1;\n\t\tint errors_Y3;\n\t\tint errortime_Y3;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [5:0] y;\n\tlogic w;\n\tlogic Y1_ref;\n\tlogic Y1_dut;\n\tlogic Y3_ref;\n\tlogic Y3_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut,Y3_ref,Y3_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_ref),\n\t\t.Y3(Y3_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y1(Y1_dut),\n\t\t.Y3(Y3_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y1\", stats1.errors_Y1, stats1.errortime_Y1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y1\");\n\t\tif (stats1.errors_Y3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y3\", stats1.errors_Y3, stats1.errortime_Y3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y3\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y1_ref, Y3_ref } === ( { Y1_ref, Y3_ref } ^ { Y1_dut, Y3_dut } ^ { Y1_ref, Y3_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))\n\t\tbegin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;\n\t\t\tstats1.errors_Y1 = stats1.errors_Y1+1'b1; end\n\t\tif (Y3_ref !== ( Y3_ref ^ Y3_dut ^ Y3_ref ))\n\t\tbegin if (stats1.errors_Y3 == 0) stats1.errortime_Y3 = $time;\n\t\t\tstats1.errors_Y3 = stats1.errors_Y3+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2fsm", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "canonical_solution": "\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\treset <= ($random & 'h1f) == 0;\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2012_q2fsm", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "canonical_solution": "\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0,B=1,C=2,D=3,E=4,F=5;\n\treg[2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\t\t\n\t\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = w ? B : A;\n\t\t\tB: next = w ? C : D;\n\t\t\tC: next = w ? E : D;\n\t\t\tD: next = w ? F : A;\n\t\t\tE: next = w ? E : D;\n\t\t\tF: next = w ? C : D;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E) || (state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\treset <= ($random & 'h1f) == 0;\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2afsm", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic [3:1] r,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign resetn = ~reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tr <= 0;\n\t\t@(posedge clk);\n\t\t\n\t\tr <= 1;\n\t\treset_test();\n\t\t\n\t\tr <= 0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= ($random & 63) == 0;\n\t\t\tr <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic [3:1] r;\n\tlogic [3:1] g_ref;\n\tlogic [3:1] g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,r,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.r );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { g_ref } === ( { g_ref } ^ { g_dut } ^ { g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2afsm", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput [3:1] r,\n\toutput [3:1] g\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways@(state,r) begin\n\t\tcase (state)\n\t\t\tA: if (r[1]) next = B;\n\t\t\t   else if (r[2]) next = C;\n\t\t\t   else if (r[3]) next = D;\n\t\t\t   else next = A;\n\t\t\tB: next = r[1] ? B : A;\n\t\t\tC: next = r[2] ? C : A;\n\t\t\tD: next = r[3] ? D : A;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign g[1] = (state == B);\t\n\tassign g[2] = (state == C);\t\n\tassign g[3] = (state == D);\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic [3:1] r,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign resetn = ~reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tr <= 0;\n\t\t@(posedge clk);\n\t\t\n\t\tr <= 1;\n\t\treset_test();\n\t\t\n\t\tr <= 0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 0;\n\t\t@(posedge clk) r <= 4;\n\t\t@(posedge clk) r <= 6;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(posedge clk) r <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= ($random & 63) == 0;\n\t\t\tr <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic [3:1] r;\n\tlogic [3:1] g_ref;\n\tlogic [3:1] g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,r,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.r );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.r,\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { g_ref } === ( { g_ref } ^ { g_dut } ^ { g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2bfsm", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n", "canonical_solution": "\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic x, y\n);\n\n\tinitial begin\n\t\tresetn = 0;\n\t\tx = 0;\n\t\ty = 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tresetn = 1;\n\t\trepeat(500) @(negedge clk) begin\n\t\t\tresetn <= ($random & 31) != 0;\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic x;\n\tlogic y;\n\tlogic f_ref;\n\tlogic f_dut;\n\tlogic g_ref;\n\tlogic g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,x,y,f_ref,f_dut,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_ref),\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_dut),\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref, g_ref } === ( { f_ref, g_ref } ^ { f_dut, g_dut } ^ { f_ref, g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2013_q2bfsm", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n", "canonical_solution": "\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput x,\n\tinput y,\n\toutput f,\n\toutput g\n);\n\tparameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;\n\treg [3:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (~resetn) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = B;\n\t\t\tB: next = S0;\n\t\t\tS0: next = x ? S1 : S0;\n\t\t\tS1: next = x ? S1 : S10;\n\t\t\tS10: next = x? G1 : S0;\n\t\t\tG1: next = y ? P1 : G2;\n\t\t\tG2: next = y ? P1 : P0;\n\t\t\tP0: next = P0;\n\t\t\tP1: next = P1;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign f = (state == B);\n\tassign g = (state == G1) || (state == G2) || (state == P1);\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic resetn,\n\toutput logic x, y\n);\n\n\tinitial begin\n\t\tresetn = 0;\n\t\tx = 0;\n\t\ty = 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tresetn = 1;\n\t\trepeat(500) @(negedge clk) begin\n\t\t\tresetn <= ($random & 31) != 0;\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\t\tint errors_g;\n\t\tint errortime_g;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic x;\n\tlogic y;\n\tlogic f_ref;\n\tlogic f_dut;\n\tlogic g_ref;\n\tlogic g_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,x,y,f_ref,f_dut,g_ref,g_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_ref),\n\t\t.g(g_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.x,\n\t\t.y,\n\t\t.f(f_dut),\n\t\t.g(g_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\t\tif (stats1.errors_g) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"g\", stats1.errors_g, stats1.errortime_g);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"g\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref, g_ref } === ( { f_ref, g_ref } ^ { f_dut, g_dut } ^ { f_ref, g_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\t\tif (g_ref !== ( g_ref ^ g_dut ^ g_ref ))\n\t\tbegin if (stats1.errors_g == 0) stats1.errortime_g = $time;\n\t\t\tstats1.errors_g = stats1.errors_g+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3c", "prompt": "module top_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n\n\talways_comb begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic [2:0] y\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= $random;\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y0;\n\t\tint errortime_Y0;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic [2:0] y;\n\tlogic Y0_ref;\n\tlogic Y0_dut;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,y,Y0_ref,Y0_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y0) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y0\", stats1.errors_Y0, stats1.errortime_Y0);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y0\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y0_ref, z_ref } === ( { Y0_ref, z_ref } ^ { Y0_dut, z_dut } ^ { Y0_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y0_ref !== ( Y0_ref ^ Y0_dut ^ Y0_ref ))\n\t\tbegin if (stats1.errors_Y0 == 0) stats1.errortime_Y0 = $time;\n\t\t\tstats1.errors_Y0 = stats1.errors_Y0+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3c", "prompt": "module top_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\tinput [2:0] y,\n\toutput reg Y0,\n\toutput reg z\n);\n\n\talways_comb begin\n\t\tcase ({y[2:0], x})\n\t\t\t4'h0: Y0 = 0;\n\t\t\t4'h1: Y0 = 1;\n\t\t\t4'h2: Y0 = 1;\n\t\t\t4'h3: Y0 = 0;\n\t\t\t4'h4: Y0 = 0;\n\t\t\t4'h5: Y0 = 1;\n\t\t\t4'h6: Y0 = 1;\n\t\t\t4'h7: Y0 = 0;\n\t\t\t4'h8: Y0 = 1;\n\t\t\t4'h9: Y0 = 0;\n\t\t\tdefault: Y0 = 1'bx;\n\t\tendcase\n\t\t\n\t\tcase (y[2:0])\n\t\t\t3'h0: z = 0;\n\t\t\t3'h1: z = 0;\n\t\t\t3'h2: z = 0;\n\t\t\t3'h3: z = 1;\n\t\t\t3'h4: z = 1;\n\t\t\tdefault: z = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic [2:0] y\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= $random;\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y0;\n\t\tint errortime_Y0;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic [2:0] y;\n\tlogic Y0_ref;\n\tlogic Y0_dut;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,y,Y0_ref,Y0_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.y,\n\t\t.Y0(Y0_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y0) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y0\", stats1.errors_Y0, stats1.errortime_Y0);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y0\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y0_ref, z_ref } === ( { Y0_ref, z_ref } ^ { Y0_dut, z_dut } ^ { Y0_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y0_ref !== ( Y0_ref ^ Y0_dut ^ Y0_ref ))\n\t\tbegin if (stats1.errors_Y0 == 0) stats1.errortime_Y0 = $time;\n\t\t\tstats1.errors_Y0 = stats1.errors_Y0+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3fsm", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic s, w,\n\tinput tb_match\n);\n\n\tbit spulse_fail = 0;\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) failed = 1;\n\t\t\n\t\t\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 0;\n\t\tw <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\ts <= 1;\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t@(posedge clk)\t\t\n\t\t\tspulse_fail <= failed;\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= !($random & 63);\n\t\t\ts <= !($random & 7);\n\t\t\tw <= $random;\n\t\tend\n\n\t\tif (failed && !spulse_fail) begin\n\t\t\t$display (\"Hint: Your state machine should ignore input 's' after the state A to B transition.\");\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic s;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q3fsm", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput s,\n\tinput w,\n\toutput reg z\n);\n\tparameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;\n\treg [2:0] state, next;\n\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A;\n\t\telse state <= next;\n\tend\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA: next = s ? B : A;\n\t\t\tB: next = w ? S11 : S10;\n\t\t\tC: next = w ? S11 : S10;\n\t\t\tS10: next = w ? S21 : S20;\n\t\t\tS11: next = w ? S22 : S21;\n\t\t\tS20: next = B;\n\t\t\tS21: next = w ? C : B;\n\t\t\tS22: next = w ? B : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t    \n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic s, w,\n\tinput tb_match\n);\n\n\tbit spulse_fail = 0;\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) failed = 1;\n\t\t\n\t\t\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 0;\n\t\tw <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\ts <= 1;\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\tend\n\t\t\n\t\t@(posedge clk)\t\t\n\t\t\tspulse_fail <= failed;\n\t\t\n\t\trepeat(500) @(negedge clk) begin\n\t\t\treset <= !($random & 63);\n\t\t\ts <= !($random & 7);\n\t\t\tw <= $random;\n\t\tend\n\n\t\tif (failed && !spulse_fail) begin\n\t\t\t$display (\"Hint: Your state machine should ignore input 's' after the state A to B transition.\");\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic s;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q4a", "prompt": "module top_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n", "canonical_solution": "\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic w, R, E, L\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{w,R,E,L} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic w;\n\tlogic R;\n\tlogic E;\n\tlogic L;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,w,R,E,L,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L );\n\treference_module good1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "2014_q4a", "prompt": "module top_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n", "canonical_solution": "\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput w,\n\tinput R,\n\tinput E,\n\tinput L,\n\toutput reg Q\n);\n\n\talways @(posedge clk)\n\t\tif (L)\n\t\t\tQ <= R;\n\t\telse if (E)\n\t\t\tQ <= w;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic w, R, E, L\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{w,R,E,L} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic w;\n\tlogic R;\n\tlogic E;\n\tlogic L;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,w,R,E,L,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L );\n\treference_module good1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.w,\n\t\t.R,\n\t\t.E,\n\t\t.L,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "7420", "prompt": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n", "canonical_solution": "\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg p1a, p1b, p1c, p1d,\n\toutput reg p2a, p2b, p2c, p2d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{p1a,p1b,p1c,p1d} <= 4'h0;\t\t\n\t\t{p2a,p2b,p2c,p2d} <= 4'h0;\t\t\n\t\twavedrom_start(\"Two NAND gates\");\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d} <= count;\t\t\n\t\t\t{p2a,p2b,p2c,p2d} <= count+1;\t\t\n\t\t\tcount = count + 1;\n\t\tend\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk,negedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p1y;\n\t\tint errortime_p1y;\n\t\tint errors_p2y;\n\t\tint errortime_p2y;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic p1a;\n\tlogic p1b;\n\tlogic p1c;\n\tlogic p1d;\n\tlogic p2a;\n\tlogic p2b;\n\tlogic p2c;\n\tlogic p2d;\n\tlogic p1y_ref;\n\tlogic p1y_dut;\n\tlogic p2y_ref;\n\tlogic p2y_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d );\n\treference_module good1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_ref),\n\t\t.p2y(p2y_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_dut),\n\t\t.p2y(p2y_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p1y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p1y\", stats1.errors_p1y, stats1.errortime_p1y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p1y\");\n\t\tif (stats1.errors_p2y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p2y\", stats1.errors_p2y, stats1.errortime_p2y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p2y\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))\n\t\tbegin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;\n\t\t\tstats1.errors_p1y = stats1.errors_p1y+1'b1; end\n\t\tif (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))\n\t\tbegin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;\n\t\t\tstats1.errors_p2y = stats1.errors_p2y+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "7420", "prompt": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n", "canonical_solution": "\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d, \n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = ~&( {p1a, p1b, p1c, p1d} );\n\tassign p2y = ~&( {p2a, p2b, p2c, p2d} );\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg p1a, p1b, p1c, p1d,\n\toutput reg p2a, p2b, p2c, p2d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{p1a,p1b,p1c,p1d} <= 4'h0;\t\t\n\t\t{p2a,p2b,p2c,p2d} <= 4'h0;\t\t\n\t\twavedrom_start(\"Two NAND gates\");\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d} <= count;\t\t\n\t\t\t{p2a,p2b,p2c,p2d} <= count+1;\t\t\n\t\t\tcount = count + 1;\n\t\tend\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk,negedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p1y;\n\t\tint errortime_p1y;\n\t\tint errors_p2y;\n\t\tint errortime_p2y;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic p1a;\n\tlogic p1b;\n\tlogic p1c;\n\tlogic p1d;\n\tlogic p2a;\n\tlogic p2b;\n\tlogic p2c;\n\tlogic p2d;\n\tlogic p1y_ref;\n\tlogic p1y_dut;\n\tlogic p2y_ref;\n\tlogic p2y_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d );\n\treference_module good1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_ref),\n\t\t.p2y(p2y_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_dut),\n\t\t.p2y(p2y_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p1y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p1y\", stats1.errors_p1y, stats1.errortime_p1y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p1y\");\n\t\tif (stats1.errors_p2y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p2y\", stats1.errors_p2y, stats1.errortime_p2y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p2y\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))\n\t\tbegin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;\n\t\t\tstats1.errors_p1y = stats1.errors_p1y+1'b1; end\n\t\tif (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))\n\t\tbegin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;\n\t\t\tstats1.errors_p2y = stats1.errors_p2y+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "7458", "prompt": "module top_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d,\n\tinput p1e,\n\tinput p1f,\n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n", "canonical_solution": "\t\n\tassign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};\n\tassign p2y = &{p2a, p2b} | &{p2c, p2d};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput p1a, \n\tinput p1b, \n\tinput p1c, \n\tinput p1d,\n\tinput p1e,\n\tinput p1f,\n\toutput p1y, \n\tinput p2a, \n\tinput p2b, \n\tinput p2c, \n\tinput p2d, \n\toutput p2y\n);\n\t\n\tassign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};\n\tassign p2y = &{p2a, p2b} | &{p2c, p2d};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg p1a, p1b, p1c, p1d, p1e, p1f,\n\toutput reg p2a, p2b, p2c, p2d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{p1a,p1b,p1c,p1d,p1e,p1f} <= 4'h0;\t\t\n\t\t{p2a,p2b,p2c,p2d} <= 4'h0;\t\t\n\t\twavedrom_start();\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p1e,p1f} <= {count[2:0], count[3:1]};\t\t\n\t\t\t{p2a,p2b,p2c,p2d} <= count;\t\t\n\t\t\tcount = count + 1;\n\t\tend\n\t\twavedrom_stop();\n\n\t\trepeat(400) @(posedge clk,negedge clk) begin\n\t\t\t{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_p1y;\n\t\tint errortime_p1y;\n\t\tint errors_p2y;\n\t\tint errortime_p2y;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic p1a;\n\tlogic p1b;\n\tlogic p1c;\n\tlogic p1d;\n\tlogic p1e;\n\tlogic p1f;\n\tlogic p2a;\n\tlogic p2b;\n\tlogic p2c;\n\tlogic p2d;\n\tlogic p1y_ref;\n\tlogic p1y_dut;\n\tlogic p2y_ref;\n\tlogic p2y_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p1e,p1f,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d );\n\treference_module good1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_ref),\n\t\t.p2y(p2y_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.p1a,\n\t\t.p1b,\n\t\t.p1c,\n\t\t.p1d,\n\t\t.p1e,\n\t\t.p1f,\n\t\t.p2a,\n\t\t.p2b,\n\t\t.p2c,\n\t\t.p2d,\n\t\t.p1y(p1y_dut),\n\t\t.p2y(p2y_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_p1y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p1y\", stats1.errors_p1y, stats1.errortime_p1y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p1y\");\n\t\tif (stats1.errors_p2y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"p2y\", stats1.errors_p2y, stats1.errortime_p2y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"p2y\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))\n\t\tbegin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;\n\t\t\tstats1.errors_p1y = stats1.errors_p1y+1'b1; end\n\t\tif (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))\n\t\tbegin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;\n\t\t\tstats1.errors_p2y = stats1.errors_p2y+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_case", "prompt": "module top_module (\n\tinput [2:0] sel,\n\tinput [3:0] data0,\n\tinput [3:0] data1,\n\tinput [3:0] data2,\n\tinput [3:0] data3,\n\tinput [3:0] data4,\n\tinput [3:0] data5,\n\toutput reg [3:0] out\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\tcase (sel)\n\t\t\t3'h0: out = data0;\n\t\t\t3'h1: out = data1;\n\t\t\t3'h2: out = data2;\n\t\t\t3'h3: out = data3;\n\t\t\t3'h4: out = data4;\n\t\t\t3'h5: out = data5;\n\t\t\tdefault: out = 4'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] sel,\n\tinput [3:0] data0,\n\tinput [3:0] data1,\n\tinput [3:0] data2,\n\tinput [3:0] data3,\n\tinput [3:0] data4,\n\tinput [3:0] data5,\n\toutput reg [3:0] out\n);\n\n\talways @(*) begin\n\t\tcase (sel)\n\t\t\t3'h0: out = data0;\n\t\t\t3'h1: out = data1;\n\t\t\t3'h2: out = data2;\n\t\t\t3'h3: out = data3;\n\t\t\t3'h4: out = data4;\n\t\t\t3'h5: out = data5;\n\t\t\tdefault: out = 4'b0;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] sel, \n\toutput logic [3:0] data0,\n\toutput logic [3:0] data1,\n\toutput logic [3:0] data2,\n\toutput logic [3:0] data3,\n\toutput logic [3:0] data4,\n\toutput logic [3:0] data5,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata0 <= 4'ha;\n\t\tdata1 <= 4'hb;\n\t\tdata2 <= 4'hc;\n\t\tdata3 <= 4'hd;\n\t\tdata4 <= 4'he;\n\t\tdata5 <= 4'hf;\n\t\t{sel} <= 3'b111;\n\t\t@(negedge clk) wavedrom_start(\"<b>Sel</b> chooses one of the data inputs\");\n\t\t\trepeat(8) @(posedge clk) sel <= sel + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{data0, data1, data2, data3} <= $urandom;\n\t\t\t{data4, data5, sel} <= $urandom;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] sel;\n\tlogic [3:0] data0;\n\tlogic [3:0] data1;\n\tlogic [3:0] data2;\n\tlogic [3:0] data3;\n\tlogic [3:0] data4;\n\tlogic [3:0] data5;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,sel,data0,data1,data2,data3,data4,data5,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5 );\n\treference_module good1 (\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.sel,\n\t\t.data0,\n\t\t.data1,\n\t\t.data2,\n\t\t.data3,\n\t\t.data4,\n\t\t.data5,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_casez", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Priority encoder\");\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\trepeat(8) @(posedge clk) in <= in << 1;\n\t\t\tin <= 8'h10;\n\t\t\trepeat(8) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tin <= $urandom;\n\t\tend\n\t\trepeat(260) @(posedge clk, negedge clk) begin\n\t\t\tin <= in + 1;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pos;\n\t\tint errortime_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [2:0] pos_ref;\n\tlogic [2:0] pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.pos(pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.pos(pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pos\", stats1.errors_pos, stats1.errortime_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))\n\t\tbegin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;\n\t\t\tstats1.errors_pos = stats1.errors_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_casez", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput reg [2:0] pos\n);\n\n\talways @(*) begin\n\t\tcasez (in)\n\t\t\tdefault : pos = 2'h0;\n\t\t\t8'bzzzzzzz1: pos = 3'h0;\n\t\t\t8'bzzzzzz1z: pos = 3'h1;\n\t\t\t8'bzzzzz1zz: pos = 3'h2;\n\t\t\t8'bzzzz1zzz: pos = 3'h3;\n\t\t\t8'bzzz1zzzz: pos = 3'h4;\n\t\t\t8'bzz1zzzzz: pos = 3'h5;\n\t\t\t8'bz1zzzzzz: pos = 3'h6;\n\t\t\t8'b1zzzzzzz: pos = 3'h7;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Priority encoder\");\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\trepeat(8) @(posedge clk) in <= in << 1;\n\t\t\tin <= 8'h10;\n\t\t\trepeat(8) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tin <= $urandom;\n\t\tend\n\t\trepeat(260) @(posedge clk, negedge clk) begin\n\t\t\tin <= in + 1;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pos;\n\t\tint errortime_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [2:0] pos_ref;\n\tlogic [2:0] pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.pos(pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.pos(pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pos\", stats1.errors_pos, stats1.errortime_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))\n\t\tbegin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;\n\t\t\tstats1.errors_pos = stats1.errors_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_if", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel_b1,\n\tinput sel_b2,\n\toutput out_assign,\n\toutput reg out_always\n);\n", "canonical_solution": "\n\tassign out_assign = (sel_b1 & sel_b2) ? b : a;\n\talways @(*) out_always = (sel_b1 & sel_b2) ? b : a;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput sel_b1,\n\tinput sel_b2,\n\toutput out_assign,\n\toutput reg out_always\n);\n\n\tassign out_assign = (sel_b1 & sel_b2) ? b : a;\n\talways @(*) out_always = (sel_b1 & sel_b2) ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,sel_b1, sel_b2,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel_b1, sel_b2} <= 4'b000;\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0100;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1000;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1101;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0001;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0110;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1010;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1011;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;\n\t\t\t@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel_b1,sel_b2} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_assign;\n\t\tint errortime_out_assign;\n\t\tint errors_out_always;\n\t\tint errortime_out_always;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sel_b1;\n\tlogic sel_b2;\n\tlogic out_assign_ref;\n\tlogic out_assign_dut;\n\tlogic out_always_ref;\n\tlogic out_always_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel_b1,sel_b2,out_assign_ref,out_assign_dut,out_always_ref,out_always_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2 );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2,\n\t\t.out_assign(out_assign_ref),\n\t\t.out_always(out_always_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel_b1,\n\t\t.sel_b2,\n\t\t.out_assign(out_assign_dut),\n\t\t.out_always(out_always_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_assign) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_assign\", stats1.errors_out_assign, stats1.errortime_out_assign);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_assign\");\n\t\tif (stats1.errors_out_always) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_always\", stats1.errors_out_always, stats1.errortime_out_always);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_always\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_assign_ref, out_always_ref } === ( { out_assign_ref, out_always_ref } ^ { out_assign_dut, out_always_dut } ^ { out_assign_ref, out_always_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))\n\t\tbegin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;\n\t\t\tstats1.errors_out_assign = stats1.errors_out_assign+1'b1; end\n\t\tif (out_always_ref !== ( out_always_ref ^ out_always_dut ^ out_always_ref ))\n\t\tbegin if (stats1.errors_out_always == 0) stats1.errortime_out_always = $time;\n\t\t\tstats1.errors_out_always = stats1.errors_out_always+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_if2", "prompt": "module top_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic cpu_overheated, arrived, gas_tank_empty,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tlogic [2:0] s = 3'b010;\n\tassign {cpu_overheated, arrived, gas_tank_empty} = s;\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t@(posedge clk) s <= 3'b010;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b001;\n\t\t@(posedge clk) s <= 3'b000;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b110;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\ts <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shut_off_computer;\n\t\tint errortime_shut_off_computer;\n\t\tint errors_keep_driving;\n\t\tint errortime_keep_driving;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic cpu_overheated;\n\tlogic arrived;\n\tlogic gas_tank_empty;\n\tlogic shut_off_computer_ref;\n\tlogic shut_off_computer_dut;\n\tlogic keep_driving_ref;\n\tlogic keep_driving_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,cpu_overheated,arrived,gas_tank_empty,shut_off_computer_ref,shut_off_computer_dut,keep_driving_ref,keep_driving_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty );\n\treference_module good1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_ref),\n\t\t.keep_driving(keep_driving_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_dut),\n\t\t.keep_driving(keep_driving_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shut_off_computer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shut_off_computer\", stats1.errors_shut_off_computer, stats1.errortime_shut_off_computer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shut_off_computer\");\n\t\tif (stats1.errors_keep_driving) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"keep_driving\", stats1.errors_keep_driving, stats1.errortime_keep_driving);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"keep_driving\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shut_off_computer_ref, keep_driving_ref } === ( { shut_off_computer_ref, keep_driving_ref } ^ { shut_off_computer_dut, keep_driving_dut } ^ { shut_off_computer_ref, keep_driving_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shut_off_computer_ref !== ( shut_off_computer_ref ^ shut_off_computer_dut ^ shut_off_computer_ref ))\n\t\tbegin if (stats1.errors_shut_off_computer == 0) stats1.errortime_shut_off_computer = $time;\n\t\t\tstats1.errors_shut_off_computer = stats1.errors_shut_off_computer+1'b1; end\n\t\tif (keep_driving_ref !== ( keep_driving_ref ^ keep_driving_dut ^ keep_driving_ref ))\n\t\tbegin if (stats1.errors_keep_driving == 0) stats1.errortime_keep_driving = $time;\n\t\t\tstats1.errors_keep_driving = stats1.errors_keep_driving+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_if2", "prompt": "module top_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput cpu_overheated,\n\toutput reg shut_off_computer,\n\tinput arrived,\n\tinput gas_tank_empty,\n\toutput reg keep_driving\n);\n\n\talways @(*) begin\n\t\tif (cpu_overheated)\n\t\t\tshut_off_computer = 1;\n\t\telse\n\t\t\tshut_off_computer = 0;\n\tend\n\t\n\talways @(*) begin\n\t\tif (~arrived)\n\t\t\tkeep_driving = !gas_tank_empty;\n\t\telse\n\t\t\tkeep_driving = 1'b0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic cpu_overheated, arrived, gas_tank_empty,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tlogic [2:0] s = 3'b010;\n\tassign {cpu_overheated, arrived, gas_tank_empty} = s;\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t@(posedge clk) s <= 3'b010;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b001;\n\t\t@(posedge clk) s <= 3'b000;\n\t\t@(posedge clk) s <= 3'b100;\n\t\t@(posedge clk) s <= 3'b110;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\t@(posedge clk) s <= 3'b111;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\ts <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shut_off_computer;\n\t\tint errortime_shut_off_computer;\n\t\tint errors_keep_driving;\n\t\tint errortime_keep_driving;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic cpu_overheated;\n\tlogic arrived;\n\tlogic gas_tank_empty;\n\tlogic shut_off_computer_ref;\n\tlogic shut_off_computer_dut;\n\tlogic keep_driving_ref;\n\tlogic keep_driving_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,cpu_overheated,arrived,gas_tank_empty,shut_off_computer_ref,shut_off_computer_dut,keep_driving_ref,keep_driving_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty );\n\treference_module good1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_ref),\n\t\t.keep_driving(keep_driving_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.cpu_overheated,\n\t\t.arrived,\n\t\t.gas_tank_empty,\n\t\t.shut_off_computer(shut_off_computer_dut),\n\t\t.keep_driving(keep_driving_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shut_off_computer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shut_off_computer\", stats1.errors_shut_off_computer, stats1.errortime_shut_off_computer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shut_off_computer\");\n\t\tif (stats1.errors_keep_driving) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"keep_driving\", stats1.errors_keep_driving, stats1.errortime_keep_driving);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"keep_driving\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shut_off_computer_ref, keep_driving_ref } === ( { shut_off_computer_ref, keep_driving_ref } ^ { shut_off_computer_dut, keep_driving_dut } ^ { shut_off_computer_ref, keep_driving_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shut_off_computer_ref !== ( shut_off_computer_ref ^ shut_off_computer_dut ^ shut_off_computer_ref ))\n\t\tbegin if (stats1.errors_shut_off_computer == 0) stats1.errortime_shut_off_computer = $time;\n\t\t\tstats1.errors_shut_off_computer = stats1.errors_shut_off_computer+1'b1; end\n\t\tif (keep_driving_ref !== ( keep_driving_ref ^ keep_driving_dut ^ keep_driving_ref ))\n\t\tbegin if (stats1.errors_keep_driving == 0) stats1.errortime_keep_driving = $time;\n\t\t\tstats1.errors_keep_driving = stats1.errors_keep_driving+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "always_nolatches", "prompt": "module top_module (\n\tinput [15:0] scancode,\n\toutput reg left,\n\toutput reg down,\n\toutput reg right,\n\toutput reg up\n);\n", "canonical_solution": "\n\talways @(*) begin\n\t\t{up, left, down, right} = 0;\n\t\tcase (scancode)\n\t\t\t16'he06b: left = 1;\n\t\t\t16'he072: down = 1;\n\t\t\t16'he074: right = 1;\n\t\t\t16'he075: up = 1;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [15:0] scancode,\n\toutput reg left,\n\toutput reg down,\n\toutput reg right,\n\toutput reg up\n);\n\n\talways @(*) begin\n\t\t{up, left, down, right} = 0;\n\t\tcase (scancode)\n\t\t\t16'he06b: left = 1;\n\t\t\t16'he072: down = 1;\n\t\t\t16'he074: right = 1;\n\t\t\t16'he075: up = 1;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [15:0] scancode, \n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Recognize arrow keys\");\n\t\t\t@(posedge clk) scancode <= 16'h0;\n\t\t\t@(posedge clk) scancode <= 16'h1;\n\t\t\t@(posedge clk) scancode <= 16'he075;\n\t\t\t@(posedge clk) scancode <= 16'he06b;\n\t\t\t@(posedge clk) scancode <= 16'he06c;\n\t\t\t@(posedge clk) scancode <= 16'he072;\n\t\t\t@(posedge clk) scancode <= 16'he074;\n\t\t\t@(posedge clk) scancode <= 16'he076;\n\t\t\t@(posedge clk) scancode <= 16'hffff;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(30000) @(posedge clk, negedge clk) begin\n\t\t\tscancode <= $urandom;\n\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_left;\n\t\tint errortime_left;\n\t\tint errors_down;\n\t\tint errortime_down;\n\t\tint errors_right;\n\t\tint errortime_right;\n\t\tint errors_up;\n\t\tint errortime_up;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [15:0] scancode;\n\tlogic left_ref;\n\tlogic left_dut;\n\tlogic down_ref;\n\tlogic down_dut;\n\tlogic right_ref;\n\tlogic right_dut;\n\tlogic up_ref;\n\tlogic up_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,scancode,left_ref,left_dut,down_ref,down_dut,right_ref,right_dut,up_ref,up_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.scancode );\n\treference_module good1 (\n\t\t.scancode,\n\t\t.left(left_ref),\n\t\t.down(down_ref),\n\t\t.right(right_ref),\n\t\t.up(up_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.scancode,\n\t\t.left(left_dut),\n\t\t.down(down_dut),\n\t\t.right(right_dut),\n\t\t.up(up_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"left\", stats1.errors_left, stats1.errortime_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"left\");\n\t\tif (stats1.errors_down) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"down\", stats1.errors_down, stats1.errortime_down);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"down\");\n\t\tif (stats1.errors_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"right\", stats1.errors_right, stats1.errortime_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"right\");\n\t\tif (stats1.errors_up) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"up\", stats1.errors_up, stats1.errortime_up);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"up\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { left_ref, down_ref, right_ref, up_ref } === ( { left_ref, down_ref, right_ref, up_ref } ^ { left_dut, down_dut, right_dut, up_dut } ^ { left_ref, down_ref, right_ref, up_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (left_ref !== ( left_ref ^ left_dut ^ left_ref ))\n\t\tbegin if (stats1.errors_left == 0) stats1.errortime_left = $time;\n\t\t\tstats1.errors_left = stats1.errors_left+1'b1; end\n\t\tif (down_ref !== ( down_ref ^ down_dut ^ down_ref ))\n\t\tbegin if (stats1.errors_down == 0) stats1.errortime_down = $time;\n\t\t\tstats1.errors_down = stats1.errors_down+1'b1; end\n\t\tif (right_ref !== ( right_ref ^ right_dut ^ right_ref ))\n\t\tbegin if (stats1.errors_right == 0) stats1.errortime_right = $time;\n\t\t\tstats1.errors_right = stats1.errors_right+1'b1; end\n\t\tif (up_ref !== ( up_ref ^ up_dut ^ up_ref ))\n\t\tbegin if (stats1.errors_up == 0) stats1.errortime_up = $time;\n\t\t\tstats1.errors_up = stats1.errors_up+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "andgate", "prompt": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "canonical_solution": "\t\n\tassign out = a & b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = a & b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"AND gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "bugs_case", "prompt": "module top_module (\n\tinput [7:0] code,\n\toutput reg [3:0] out,\n\toutput reg valid\n);\n", "canonical_solution": "//\tuhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?\n//  and have one of the entries be wrong? (duplicate case, using different base!) \n\talways @(*) begin\n\t\tout = 0;\n\t\tvalid = 1;\n\t\tcase (code)\n\t\t\t8'h45: out = 0;\n\t\t\t8'h16: out = 1;\n\t\t\t8'h1e: out = 2;\n\t\t\t8'h26: out = 3;\n\t\t\t8'h25: out = 4;\n\t\t\t8'h2e: out = 5;\n\t\t\t8'h36: out = 6;\n\t\t\t8'h3d: out = 7;\n\t\t\t8'h3e: out = 8;\n\t\t\t8'h46: out = 9;\n\t\t\tdefault: valid = 0;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] code,\n\toutput reg [3:0] out,\n\toutput reg valid\n);\n//\tuhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?\n//  and have one of the entries be wrong? (duplicate case, using different base!) \n\talways @(*) begin\n\t\tout = 0;\n\t\tvalid = 1;\n\t\tcase (code)\n\t\t\t8'h45: out = 0;\n\t\t\t8'h16: out = 1;\n\t\t\t8'h1e: out = 2;\n\t\t\t8'h26: out = 3;\n\t\t\t8'h25: out = 4;\n\t\t\t8'h2e: out = 5;\n\t\t\t8'h36: out = 6;\n\t\t\t8'h3d: out = 7;\n\t\t\t8'h3e: out = 8;\n\t\t\t8'h46: out = 9;\n\t\t\tdefault: valid = 0;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] code,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tcode <= 8'h45;\n\t\t@(negedge clk) wavedrom_start(\"Decode scancodes\");\n\t\t\t@(posedge clk) code <= 8'h45;\n\t\t\t@(posedge clk) code <= 8'h03;\n\t\t\t@(posedge clk) code <= 8'h46;\n\t\t\t@(posedge clk) code <= 8'h16;\n\t\t\t@(posedge clk) code <= 8'd26;\n\t\t\t@(posedge clk) code <= 8'h1e;\n\t\t\t@(posedge clk) code <= 8'h25;\n\t\t\t@(posedge clk) code <= 8'h26;\n\t\t\t@(posedge clk) code <= 8'h2e;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= 8'h36;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= 8'h3d;\n\t\t\t@(posedge clk) code <= 8'h3e;\n\t\t\t@(posedge clk) code <= 8'h45;\n\t\t\t@(posedge clk) code <= 8'h46;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\t\t@(posedge clk) code <= $random;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(1000) @(posedge clk, negedge clk) begin\n\t\t\tcode <= $urandom;\n\t\tend\n\t\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_valid;\n\t\tint errortime_valid;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] code;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\tlogic valid_ref;\n\tlogic valid_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,code,out_ref,out_dut,valid_ref,valid_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.code );\n\treference_module good1 (\n\t\t.code,\n\t\t.out(out_ref),\n\t\t.valid(valid_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.code,\n\t\t.out(out_dut),\n\t\t.valid(valid_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_valid) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"valid\", stats1.errors_valid, stats1.errortime_valid);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"valid\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, valid_ref } === ( { out_ref, valid_ref } ^ { out_dut, valid_dut } ^ { out_ref, valid_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (valid_ref !== ( valid_ref ^ valid_dut ^ valid_ref ))\n\t\tbegin if (stats1.errors_valid == 0) stats1.errortime_valid = $time;\n\t\t\tstats1.errors_valid = stats1.errors_valid+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "bugs_mux2", "prompt": "module top_module (\n\tinput sel,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out\n);\n", "canonical_solution": "\n\t// assign out = (~sel & a) | (sel & b);\n    assign out = sel ? a : b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput sel,\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput reg [7:0] out\n);\n\n\t// assign out = (~sel & a) | (sel & b);\n    assign out = sel ? a : b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic sel,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel} <= '0;\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};\n\t\t\t\n\t\t\t@(posedge clk, negedge clk) {a, b} <= {8'hff, 8'h00}; sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b0;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\t\t@(posedge clk, negedge clk) sel <= 1'b1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic sel;\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,sel,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.sel,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.sel,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.sel,\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit1", "prompt": "module top_module (\n\tinput a, \n\tinput b, \n\toutput q\n);\n", "canonical_solution": "\n\tassign q = a&b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\toutput q\n);\n\n\tassign q = a&b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\trepeat(8) @(posedge clk) {a,b} <= {a,b} + 1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit10", "prompt": "module top_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n", "canonical_solution": "\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,\n\toutput logic b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\ta <= 1;\n\t\t@(negedge clk) {a,b} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\trepeat(3) @(posedge clk);\n\t\t\t{a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\ta <= &((5)'($urandom));\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic q_ref;\n\tlogic q_dut;\n\tlogic state_ref;\n\tlogic state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,q_ref,q_dut,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_ref),\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_dut),\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref, state_ref } === ( { q_ref, state_ref } ^ { q_dut, state_dut } ^ { q_ref, state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit10", "prompt": "module top_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n", "canonical_solution": "\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput a,\n\tinput b,\n\toutput q,\n\toutput state\n);\n\n\treg c;\n\talways @(posedge clk)\n\t\tc <= a&b | a&c | b&c;\n\t\n\tassign q = a^b^c;\n\tassign state = c;\n\t\t\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,\n\toutput logic b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\ta <= 1;\n\t\t@(negedge clk) {a,b} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\trepeat(3) @(posedge clk);\n\t\t\t{a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\ta <= &((5)'($urandom));\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic q_ref;\n\tlogic q_dut;\n\tlogic state_ref;\n\tlogic state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,q_ref,q_dut,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_ref),\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.a,\n\t\t.b,\n\t\t.q(q_dut),\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref, state_ref } === ( { q_ref, state_ref } ^ { q_dut, state_dut } ^ { q_ref, state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit3", "prompt": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "canonical_solution": "\n\tassign q = (a|b) & (c|d);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = (a|b) & (c|d);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit4", "prompt": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "canonical_solution": "\n\tassign q = c | b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = c | b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit4", "prompt": "module top_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n", "canonical_solution": "\n\tassign q = c | b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b, \n\tinput c, \n\tinput d,\n\toutput q\n);\n\n\tassign q = c | b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t\trepeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit5", "prompt": "module top_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n", "canonical_solution": "\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] a,b,c,d,e,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'hab0de};\n\t\t\trepeat(18) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h12034};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h56078};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] a;\n\tlogic [3:0] b;\n\tlogic [3:0] c;\n\tlogic [3:0] d;\n\tlogic [3:0] e;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "circuit5", "prompt": "module top_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n", "canonical_solution": "\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] a, \n\tinput [3:0] b, \n\tinput [3:0] c, \n\tinput [3:0] d,\n\tinput [3:0] e,\n\toutput reg [3:0] q\n);\n\n\talways @(*) \n\t\tcase (c)\n\t\t\t0: q = b;\n\t\t\t1: q = e;\n\t\t\t2: q = a;\n\t\t\t3: q = d;\n\t\t\tdefault: q = 4'hf;\n\t\tendcase\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] a,b,c,d,e,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'hab0de};\n\t\t\trepeat(18) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\n\t\t@(negedge clk) wavedrom_start(\"Unknown circuit\");\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h12034};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\t\t@(posedge clk) {a,b,c,d,e} <= {20'h56078};\n\t\t\trepeat(8) @(posedge clk, negedge clk) c <= c + 1;\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $urandom;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] a;\n\tlogic [3:0] b;\n\tlogic [3:0] c;\n\tlogic [3:0] d;\n\tlogic [3:0] e;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "conwaylife", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n", "canonical_solution": "\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\tinput [255:0] q_ref,\n\tinput [255:0] q_dut,\n\toutput reg load,\n\toutput reg[255:0] data\n);\n\n\tlogic errored = 0;\n\tint blinker_cycle = 0;\n\n\tinitial begin\n\t\tdata <= 3'h7;\t\t\t// Simple blinker, period 2\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(5) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The first test case is a blinker (initial state = 256'h7). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h000200010007;\t// Glider, Traveling diagonal down-right.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The second test case is a glider (initial state = 256'h000200010007). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored && blinker_cycle < 20) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h0040001000ce;\t\t\t// Acorn\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random};\t\t// Some random test cases.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random}&\t\t// Random with more zeros.\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random};\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [255:0] data;\n\tlogic [255:0] q_ref;\n\tlogic [255:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "conwaylife", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n", "canonical_solution": "\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [255:0] data,\n\toutput reg [255:0] q);\n\t\n\t\n\tlogic [323:0] q_pad;\n\talways@(*) begin\n\t\tfor (int i=0;i<16;i++)\n\t\t\tq_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];\n\t\tq_pad[1 +: 16] = q[16*15 +: 16];\n\t\tq_pad[18*17+1 +: 16] = q[0 +: 16];\n\t\t\n\t\tfor (int i=0; i<18; i++) begin\n\t\t\tq_pad[i*18] = q_pad[i*18+16];\n\t\t\tq_pad[i*18+17] = q_pad[i*18+1];\n\t\tend\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tfor (int i=0;i<16;i++)\n\t\tfor (int j=0;j<16;j++) begin\n\t\t\tq[i*16+j] <= \n\t\t\t\t((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1]                                + q_pad[(i+1)*18+j+1+1] +\n\t\t\t\tq_pad[(i+1)*18+j+1 -1-18]   + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;\n\t\tend\n\t\t\n\t\tif (load)\n\t\t\tq <= data;\n\t\t\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\tinput [255:0] q_ref,\n\tinput [255:0] q_dut,\n\toutput reg load,\n\toutput reg[255:0] data\n);\n\n\tlogic errored = 0;\n\tint blinker_cycle = 0;\n\n\tinitial begin\n\t\tdata <= 3'h7;\t\t\t// Simple blinker, period 2\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(5) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The first test case is a blinker (initial state = 256'h7). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h000200010007;\t// Glider, Traveling diagonal down-right.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\tdata <= 4'hx;\n\t\terrored = 0;\n\t\tblinker_cycle = 0;\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tblinker_cycle++;\n\t\t\tif (!tb_match) begin\n\t\t\t\tif (!errored) begin\n\t\t\t\t\terrored = 1;\n\t\t\t\t\t$display(\"Hint: The second test case is a glider (initial state = 256'h000200010007). First mismatch occurred at cycle %0d.\\nHint:\", blinker_cycle);\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\t\tif (errored && blinker_cycle < 20) begin\n\t\t\t\t$display (\"Hint: Cycle %0d:         Your game state       Reference game state\", blinker_cycle);\n\t\t\t\tfor (int i=15;i>=0;i--) begin\n\t\t\t\t\t$display(\"Hint:   q[%3d:%3d]     %016b      %016b\", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);\n\t\t\t\tend\n\t\t\t\t$display(\"Hint:\\nHint:\\n\");\n\t\t\tend\n\t\tend\n\n\n\t\tdata <= 48'h0040001000ce;\t\t\t// Acorn\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random};\t\t// Some random test cases.\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\t\tdata <= {$random,$random,$random,$random,$random,$random,$random,$random}&\t\t// Random with more zeros.\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random}&\n\t\t\t\t{$random,$random,$random,$random,$random,$random,$random,$random};\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(200) @(posedge clk);\n\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [255:0] data;\n\tlogic [255:0] q_ref;\n\tlogic [255:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count15", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\tinput tb_match,\n\toutput reg wavedrom_enable,\n\toutput reg[511:0] wavedrom_title\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\treset <= 1;\n\t\t@(negedge clk);\n\t\t\n\t\twavedrom_start(\"Reset and counting\");\n\t\treset_test();\n\t\t\n\t\trepeat(3) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count1to10", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset || q == 10)\n\t\t\tq <= 1;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 10)\n\t\t\tq <= 1;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting.\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count_clock", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n", "canonical_solution": "\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg ena,\n\tinput [7:0] hh_dut, mm_dut, ss_dut,\n\tinput pm_dut,\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\n\tlogic bcd_fail = 0;\n\tlogic reset_fail = 0;\n\t\n\talways @(posedge clk) begin\n\t\tif ((hh_dut[3:0] >= 4'ha) ||\n\t\t\t(hh_dut[7:4] >= 4'ha) ||\n\t\t\t(mm_dut[3:0] >= 4'ha) ||\n\t\t\t(mm_dut[7:4] >= 4'ha) ||\n\t\t\t(ss_dut[3:0] >= 4'ha) ||\n\t\t\t(ss_dut[7:4] >= 4'ha))\n\t\t\tbcd_fail <= 1'b1;\t\t\n\tend\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tena <= 1;\n\t\twavedrom_start(\"Reset and count to 10\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\tena <= 1'b1;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match) begin\n\t\t\t\t$display(\"Hint: Clock seems to reset to %02x:%02x:%02x %s (Should be 12:00:00 AM).\", hh_dut, mm_dut, ss_dut, pm_dut ? \"PM\": \"AM\");\n\t\t\t\treset_fail <= 1'b1;\n\t\t\tend\n\t\t\n\t\treset <= 1'b0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tena <= 1'b0;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match && !reset_fail)\n\t\t\t\t$display(\"Hint: Reset has higher priority than enable and should occur even if not enabled.\");\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tena <= !($random & 3);\n\t\tend\n\t\treset <= 1;\n\t\t@(posedge clk) begin\n\t\t\t{reset, ena} <= 2'b1;\n\t\tend\n\t\t\n\t\trepeat(55) @(posedge clk);\n\t\twavedrom_start(\"Minute roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(3530) @(posedge clk);\n\t\twavedrom_start(\"Hour roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\n\t\trepeat(39590) @(posedge clk);\n\t\twavedrom_start(\"PM roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(132745) @(posedge clk);\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tena <= !($random & 7);\n\t\tend\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t\n\t\t\n\t\tif (bcd_fail)\n\t\t\t$display(\"Hint: Non-BCD values detected. Are you sure you're using two-digit BCD representation for hh, mm, and ss?\");\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pm;\n\t\tint errortime_pm;\n\t\tint errors_hh;\n\t\tint errortime_hh;\n\t\tint errors_mm;\n\t\tint errortime_mm;\n\t\tint errors_ss;\n\t\tint errortime_ss;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic ena;\n\tlogic pm_ref;\n\tlogic pm_dut;\n\tlogic [7:0] hh_ref;\n\tlogic [7:0] hh_dut;\n\tlogic [7:0] mm_ref;\n\tlogic [7:0] mm_dut;\n\tlogic [7:0] ss_ref;\n\tlogic [7:0] ss_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena,pm_ref,pm_dut,hh_ref,hh_dut,mm_ref,mm_dut,ss_ref,ss_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.ena );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_ref),\n\t\t.hh(hh_ref),\n\t\t.mm(mm_ref),\n\t\t.ss(ss_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_dut),\n\t\t.hh(hh_dut),\n\t\t.mm(mm_dut),\n\t\t.ss(ss_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pm\", stats1.errors_pm, stats1.errortime_pm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pm\");\n\t\tif (stats1.errors_hh) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"hh\", stats1.errors_hh, stats1.errortime_hh);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"hh\");\n\t\tif (stats1.errors_mm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mm\", stats1.errors_mm, stats1.errortime_mm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mm\");\n\t\tif (stats1.errors_ss) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ss\", stats1.errors_ss, stats1.errortime_ss);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ss\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pm_ref, hh_ref, mm_ref, ss_ref } === ( { pm_ref, hh_ref, mm_ref, ss_ref } ^ { pm_dut, hh_dut, mm_dut, ss_dut } ^ { pm_ref, hh_ref, mm_ref, ss_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pm_ref !== ( pm_ref ^ pm_dut ^ pm_ref ))\n\t\tbegin if (stats1.errors_pm == 0) stats1.errortime_pm = $time;\n\t\t\tstats1.errors_pm = stats1.errors_pm+1'b1; end\n\t\tif (hh_ref !== ( hh_ref ^ hh_dut ^ hh_ref ))\n\t\tbegin if (stats1.errors_hh == 0) stats1.errortime_hh = $time;\n\t\t\tstats1.errors_hh = stats1.errors_hh+1'b1; end\n\t\tif (mm_ref !== ( mm_ref ^ mm_dut ^ mm_ref ))\n\t\tbegin if (stats1.errors_mm == 0) stats1.errortime_mm = $time;\n\t\t\tstats1.errors_mm = stats1.errors_mm+1'b1; end\n\t\tif (ss_ref !== ( ss_ref ^ ss_dut ^ ss_ref ))\n\t\tbegin if (stats1.errors_ss == 0) stats1.errortime_ss = $time;\n\t\t\tstats1.errors_ss = stats1.errors_ss+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "count_clock", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n", "canonical_solution": "\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput ena,\n\toutput reg pm,\n\toutput reg [7:0] hh,\n\toutput reg [7:0] mm,\n\toutput reg [7:0] ss);\n\t\n\twire [6:0] enable = {\n\t\t{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,\n\t\t{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,\n\t\t{mm[7:0],ss[7:0]}==16'h5959,\n\t\t{mm[3:0],ss[7:0]}==12'h959,\n\t\tss[7:0]==8'h59, \n\t\tss[3:0] == 4'h9, \n\t\t1'b1};\n\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\t{pm,hh,mm,ss} <= 25'h0120000;\n\t\telse if (ena) begin\n\t\t\tif (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;\n\t\t\telse if (enable[0]) ss[3:0] <= ss[3:0] + 1;\n\n\t\t\tif (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;\n\t\t\telse if (enable[1]) ss[7:4] <= ss[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;\n\t\t\telse if (enable[2]) mm[3:0] <= mm[3:0] + 1;\n\n\t\t\tif (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;\n\t\t\telse if (enable[3]) mm[7:4] <= mm[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;\n\t\t\telse if (enable[4]) hh[3:0] <= hh[3:0] + 1;\n\n\t\t\tif (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;\n\t\t\telse if (enable[5]) hh[7:4] <= hh[7:4] + 1;\n\t\t\t\n\t\t\tif (enable[6]) pm <= ~pm;\n\t\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg ena,\n\tinput [7:0] hh_dut, mm_dut, ss_dut,\n\tinput pm_dut,\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\n\tlogic bcd_fail = 0;\n\tlogic reset_fail = 0;\n\t\n\talways @(posedge clk) begin\n\t\tif ((hh_dut[3:0] >= 4'ha) ||\n\t\t\t(hh_dut[7:4] >= 4'ha) ||\n\t\t\t(mm_dut[3:0] >= 4'ha) ||\n\t\t\t(mm_dut[7:4] >= 4'ha) ||\n\t\t\t(ss_dut[3:0] >= 4'ha) ||\n\t\t\t(ss_dut[7:4] >= 4'ha))\n\t\t\tbcd_fail <= 1'b1;\t\t\n\tend\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tena <= 1;\n\t\twavedrom_start(\"Reset and count to 10\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\tena <= 1'b1;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match) begin\n\t\t\t\t$display(\"Hint: Clock seems to reset to %02x:%02x:%02x %s (Should be 12:00:00 AM).\", hh_dut, mm_dut, ss_dut, pm_dut ? \"PM\": \"AM\");\n\t\t\t\treset_fail <= 1'b1;\n\t\t\tend\n\t\t\n\t\treset <= 1'b0;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tena <= 1'b0;\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\t@(posedge clk)\n\t\t\tif (!tb_match && !reset_fail)\n\t\t\t\t$display(\"Hint: Reset has higher priority than enable and should occur even if not enabled.\");\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tena <= !($random & 3);\n\t\tend\n\t\treset <= 1;\n\t\t@(posedge clk) begin\n\t\t\t{reset, ena} <= 2'b1;\n\t\tend\n\t\t\n\t\trepeat(55) @(posedge clk);\n\t\twavedrom_start(\"Minute roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(3530) @(posedge clk);\n\t\twavedrom_start(\"Hour roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\n\n\t\trepeat(39590) @(posedge clk);\n\t\twavedrom_start(\"PM roll-over\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(132745) @(posedge clk);\n\t\trepeat(50) @(posedge clk, negedge clk) begin\n\t\t\tena <= !($random & 7);\n\t\tend\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t\n\t\t\n\t\tif (bcd_fail)\n\t\t\t$display(\"Hint: Non-BCD values detected. Are you sure you're using two-digit BCD representation for hh, mm, and ss?\");\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pm;\n\t\tint errortime_pm;\n\t\tint errors_hh;\n\t\tint errortime_hh;\n\t\tint errors_mm;\n\t\tint errortime_mm;\n\t\tint errors_ss;\n\t\tint errortime_ss;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic ena;\n\tlogic pm_ref;\n\tlogic pm_dut;\n\tlogic [7:0] hh_ref;\n\tlogic [7:0] hh_dut;\n\tlogic [7:0] mm_ref;\n\tlogic [7:0] mm_dut;\n\tlogic [7:0] ss_ref;\n\tlogic [7:0] ss_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena,pm_ref,pm_dut,hh_ref,hh_dut,mm_ref,mm_dut,ss_ref,ss_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.ena );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_ref),\n\t\t.hh(hh_ref),\n\t\t.mm(mm_ref),\n\t\t.ss(ss_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena,\n\t\t.pm(pm_dut),\n\t\t.hh(hh_dut),\n\t\t.mm(mm_dut),\n\t\t.ss(ss_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pm\", stats1.errors_pm, stats1.errortime_pm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pm\");\n\t\tif (stats1.errors_hh) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"hh\", stats1.errors_hh, stats1.errortime_hh);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"hh\");\n\t\tif (stats1.errors_mm) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mm\", stats1.errors_mm, stats1.errortime_mm);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mm\");\n\t\tif (stats1.errors_ss) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ss\", stats1.errors_ss, stats1.errortime_ss);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ss\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pm_ref, hh_ref, mm_ref, ss_ref } === ( { pm_ref, hh_ref, mm_ref, ss_ref } ^ { pm_dut, hh_dut, mm_dut, ss_dut } ^ { pm_ref, hh_ref, mm_ref, ss_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pm_ref !== ( pm_ref ^ pm_dut ^ pm_ref ))\n\t\tbegin if (stats1.errors_pm == 0) stats1.errortime_pm = $time;\n\t\t\tstats1.errors_pm = stats1.errors_pm+1'b1; end\n\t\tif (hh_ref !== ( hh_ref ^ hh_dut ^ hh_ref ))\n\t\tbegin if (stats1.errors_hh == 0) stats1.errortime_hh = $time;\n\t\t\tstats1.errors_hh = stats1.errors_hh+1'b1; end\n\t\tif (mm_ref !== ( mm_ref ^ mm_dut ^ mm_ref ))\n\t\tbegin if (stats1.errors_mm == 0) stats1.errortime_mm = $time;\n\t\t\tstats1.errors_mm = stats1.errors_mm+1'b1; end\n\t\tif (ss_ref !== ( ss_ref ^ ss_dut ^ ss_ref ))\n\t\tbegin if (stats1.errors_ss == 0) stats1.errortime_ss = $time;\n\t\t\tstats1.errors_ss = stats1.errors_ss+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countbcd", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n", "canonical_solution": "\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\treset_test();\n\t\trepeat(2) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Counting\");\n\t\t\trepeat(12) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(71) @(posedge clk);\n\t\t@(negedge clk) wavedrom_start(\"100 rollover\");\n\t\t\trepeat(16) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\treset <= !($random & 31);\n\t\trepeat(19590) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ena;\n\t\tint errortime_ena;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] ena_ref;\n\tlogic [3:1] ena_dut;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena_ref,ena_dut,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_ref),\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_dut),\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ena\", stats1.errors_ena, stats1.errortime_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ena\");\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ena_ref, q_ref } === ( { ena_ref, q_ref } ^ { ena_dut, q_dut } ^ { ena_ref, q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ena_ref !== ( ena_ref ^ ena_dut ^ ena_ref ))\n\t\tbegin if (stats1.errors_ena == 0) stats1.errortime_ena = $time;\n\t\t\tstats1.errors_ena = stats1.errors_ena+1'b1; end\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countbcd", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n", "canonical_solution": "\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput [3:1] ena,\n\toutput reg [15:0] q);\n\t\n\twire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};\n\tassign ena = enable[3:1];\n\talways @(posedge clk)\n\t\tfor (int i=0;i<4;i++) begin\n\t\t\tif (reset || (q[i*4 +:4] == 9 && enable[i]))\n\t\t\t\tq[i*4 +:4] <= 0;\n\t\t\telse if (enable[i])\n\t\t\t\tq[i*4 +:4] <= q[i*4 +:4]+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\treset_test();\n\t\trepeat(2) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Counting\");\n\t\t\trepeat(12) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(71) @(posedge clk);\n\t\t@(negedge clk) wavedrom_start(\"100 rollover\");\n\t\t\trepeat(16) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\treset <= !($random & 31);\n\t\trepeat(19590) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ena;\n\t\tint errortime_ena;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] ena_ref;\n\tlogic [3:1] ena_dut;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena_ref,ena_dut,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_ref),\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.ena(ena_dut),\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ena\", stats1.errors_ena, stats1.errortime_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ena\");\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ena_ref, q_ref } === ( { ena_ref, q_ref } ^ { ena_dut, q_dut } ^ { ena_ref, q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ena_ref !== ( ena_ref ^ ena_dut ^ ena_ref ))\n\t\tbegin if (stats1.errors_ena == 0) stats1.errortime_ena = $time;\n\t\t\tstats1.errors_ena = stats1.errors_ena+1'b1; end\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "counter_2bc", "prompt": "module top_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n", "canonical_solution": "    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n\n\nmodule stimulus_gen(\n\tinput clk,\n\toutput logic areset,\n\toutput logic train_valid,\n\toutput train_taken,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic train_taken_r;\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\t@(posedge clk) reset <= 0;\n\n\t\twavedrom_start(\"Count up, then down\");\n\t\ttrain_taken_r <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_taken_r <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\t\t\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) \n\t\t\t{train_valid, train_taken_r} <= {$urandom} ;\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic [1:0] state_ref;\n\tlogic [1:0] state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,train_valid,train_taken,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { state_ref } === ( { state_ref } ^ { state_dut } ^ { state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "counter_2bc", "prompt": "module top_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n", "canonical_solution": "    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input clk,\n    input areset,\n    input train_valid,\n    input train_taken,\n    output logic [1:0] state\n);\n    always @(posedge clk, posedge areset) begin\n        if (areset)\n            state <= 1;\n        else if (train_valid) begin\n            if(state < 3 && train_taken)\n                state <= state + 1;\n            else if(state > 0 && !train_taken)\n                state <= state - 1;\n        end\n    end\nendmodule\n\n\nmodule stimulus_gen(\n\tinput clk,\n\toutput logic areset,\n\toutput logic train_valid,\n\toutput train_taken,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic train_taken_r;\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\t@(posedge clk) reset <= 0;\n\n\t\twavedrom_start(\"Count up, then down\");\n\t\ttrain_taken_r <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_taken_r <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 1;\n\t\t\t@(posedge clk) train_valid <= 0;\n\t\t\t@(posedge clk) train_valid <= 1;\t\t\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) \n\t\t\t{train_valid, train_taken_r} <= {$urandom} ;\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_state;\n\t\tint errortime_state;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic [1:0] state_ref;\n\tlogic [1:0] state_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,train_valid,train_taken,state_ref,state_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.state(state_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"state\", stats1.errors_state, stats1.errortime_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"state\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { state_ref } === ( { state_ref } ^ { state_dut } ^ { state_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (state_ref !== ( state_ref ^ state_dut ^ state_ref ))\n\t\tbegin if (stats1.errors_state == 0) stats1.errortime_state = $time;\n\t\t\tstats1.errors_state = stats1.errors_state+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countslow", "prompt": "module top_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg slowena,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\t\n\treg hint1;\n\tinitial begin\n\t\treset <= 1;\n\t\tslowena <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting.\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\t//wavedrom_start(\"Testing.\");\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tslowena <= 0;\n\t\t@(negedge clk) hint1 = tb_match;\n\t\trepeat(3) @(posedge clk);\n\t\tif (hint1 && !tb_match) begin\n\t\t\t$display (\"Hint: What is supposed to happen when the counter is 9 and not enabled?\");\n\t\tend\n\t\t//wavedrom_stop();\n\t\tslowena <= 1;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\n\n\t\twavedrom_start(\"Enable/disable\");\n\t\trepeat(15) @(posedge clk) slowena <= !($random & 1);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tslowena <= !($random&3);\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic slowena;\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,slowena,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.slowena,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "countslow", "prompt": "module top_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput slowena,\n\tinput reset,\n\toutput reg [3:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tq <= 0;\n\t\telse if (slowena) begin\n\t\t\tif (q == 9)\n\t\t\t\tq <= 0;\n\t\t\telse\n\t\t\t\tq <= q+1;\n\t\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg slowena,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\t\n\treg hint1;\n\tinitial begin\n\t\treset <= 1;\n\t\tslowena <= 1;\n\t\twavedrom_start(\"Synchronous reset and counting.\");\n\t\treset_test();\n\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\t//wavedrom_start(\"Testing.\");\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tslowena <= 0;\n\t\t@(negedge clk) hint1 = tb_match;\n\t\trepeat(3) @(posedge clk);\n\t\tif (hint1 && !tb_match) begin\n\t\t\t$display (\"Hint: What is supposed to happen when the counter is 9 and not enabled?\");\n\t\tend\n\t\t//wavedrom_stop();\n\t\tslowena <= 1;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\n\n\t\twavedrom_start(\"Enable/disable\");\n\t\trepeat(15) @(posedge clk) slowena <= !($random & 1);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tslowena <= !($random&3);\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic slowena;\n\tlogic reset;\n\tlogic [3:0] q_ref;\n\tlogic [3:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,slowena,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.slowena,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.slowena,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff", "prompt": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n", "canonical_solution": "\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\talways @(posedge clk, negedge clk)\n\t\td <= $urandom;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Positive-edge triggered DFF\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff", "prompt": "module top_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n", "canonical_solution": "\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput d,\n\toutput reg q);\n\t\n\tinitial\n\t\tq = 1'hx;\n\t\t\n\talways @(posedge clk)\n\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\talways @(posedge clk, negedge clk)\n\t\td <= $urandom;\n\t\n\tinitial begin\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Positive-edge triggered DFF\");\n\t\trepeat(10) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(100) @(posedge clk, negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff16e", "prompt": "module top_module(\n\tinput clk,\n\tinput resetn,\n\tinput [1:0] byteena,\n\tinput [15:0] d,\n\toutput reg [15:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk) begin\n\t\tif (!resetn)\n\t\t\tq <= 0;\n\t\telse begin\n\t\t\tif (byteena[0])\n\t\t\t\tq[7:0] <= d[7:0];\n\t\t\tif (byteena[1])\n\t\t\t\tq[15:8] <= d[15:8];\n\t\tend\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput resetn,\n\tinput [1:0] byteena,\n\tinput [15:0] d,\n\toutput reg [15:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (!resetn)\n\t\t\tq <= 0;\n\t\telse begin\n\t\t\tif (byteena[0])\n\t\t\t\tq[7:0] <= d[7:0];\n\t\t\tif (byteena[1])\n\t\t\t\tq[15:8] <= d[15:8];\n\t\tend\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [15:0] d, output reg [1:0] byteena,\n\toutput reg resetn,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign resetn = ~reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tbyteena <= 2'b11;\n\t\td <= 16'habcd;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"Synchronous active-low reset\");\n\t\treset_test(0);\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\tbyteena <= 2'b11;\n\t\td <= $random;\n\t\t@(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"DFF with byte enables\");\n\t\trepeat(10) @(posedge clk) begin\n\t\t\td <= $random;\n\t\t\tbyteena <= byteena + 1;\n\t\tend\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tbyteena[0] <= ($random & 3) != 0;\n\t\t\tbyteena[1] <= ($random & 3) != 0;\n\t\t\td <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic [1:0] byteena;\n\tlogic [15:0] d;\n\tlogic [15:0] q_ref;\n\tlogic [15:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,byteena,d,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.byteena,\n\t\t.d,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "dff8ar", "prompt": "module top_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput areset,\n\toutput reg [7:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk, posedge areset)\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] d,\n\tinput areset,\n\toutput reg [7:0] q);\n\t\n\talways @(posedge clk, posedge areset)\n\t\tif (areset)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [7:0] d, output areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\t\n);\n\n\treg reset;\n\tassign areset = reset;\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\td <= $random;\n\t\t@(negedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Asynchronous active-high reset\");\n\t\treset_test(1);\n\t\trepeat(7) @(negedge clk) d <= $random;\n\t\t@(posedge clk) reset <= 1;\n\t\t@(negedge clk) reset <= 0; d <= $random;\n\t\trepeat(2) @(negedge clk) d <= $random;\n\t\twavedrom_stop();\n\n\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 15);\n\t\t\td <= $random;\n\t\tend\n\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] d;\n\tlogic areset;\n\tlogic [7:0] q_ref;\n\tlogic [7:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,areset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.areset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.areset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q12", "prompt": "module top_module (\n\tinput clk,\n\tinput enable,\n\tinput S,\n\tinput A,\n\tinput B,\n\tinput C,\n\toutput reg Z\n);\n", "canonical_solution": "\n\treg [7:0] q;\n\talways @(posedge clk) begin\n\t\tif (enable)\n\t\t\tq <= {q[6:0], S};\n\tend\n\t\n\tassign Z = q[ {A, B, C} ];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput enable,\n\tinput S,\n\tinput A,\n\tinput B,\n\tinput C,\n\toutput reg Z\n);\n\n\treg [7:0] q;\n\talways @(posedge clk) begin\n\t\tif (enable)\n\t\t\tq <= {q[6:0], S};\n\tend\n\t\n\tassign Z = q[ {A, B, C} ];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic S, enable,\n\toutput logic A, B, C,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tenable <= 0;\n\t\t{A,B,C} <= 0;\n\t\tS <= 1'bx;\n\t\t@(negedge clk) wavedrom_start(\"A 3-input AND gate\");\n\t\t\t@(posedge clk);\n\t\t\t@(posedge clk) enable <= 1; S <= 1;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) S <= 0;\n\t\t\t@(posedge clk) enable <= 0; S <= 1'bx;\n\t\t\t{A,B,C} <= 5;\n\t\t\t@(posedge clk) {A,B,C} <= 6;\n\t\t\t@(posedge clk) {A,B,C} <= 7;\n\t\t\t@(posedge clk) {A,B,C} <= 0;\n\t\t\t@(posedge clk) {A,B,C} <= 1;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\trepeat(500) @(posedge clk, negedge clk) begin\n\t\t\t{A,B,C,S} <= $random;\n\t\t\tenable <= ($random&3) == 0;\n\t\tend\n\t\t\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Z;\n\t\tint errortime_Z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic enable;\n\tlogic S;\n\tlogic A;\n\tlogic B;\n\tlogic C;\n\tlogic Z_ref;\n\tlogic Z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,enable,S,A,B,C,Z_ref,Z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C );\n\treference_module good1 (\n\t\t.clk,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C,\n\t\t.Z(Z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.enable,\n\t\t.S,\n\t\t.A,\n\t\t.B,\n\t\t.C,\n\t\t.Z(Z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Z\", stats1.errors_Z, stats1.errortime_Z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Z_ref } === ( { Z_ref } ^ { Z_dut } ^ { Z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Z_ref !== ( Z_ref ^ Z_dut ^ Z_ref ))\n\t\tbegin if (stats1.errors_Z == 0) stats1.errortime_Z = $time;\n\t\t\tstats1.errors_Z = stats1.errors_Z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q2", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n", "canonical_solution": "\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tbit fail = 0;\n\tbit fail1 = 0;\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match)\n\t\t\tfail = 1;\n\n\tinitial begin\n\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t@(posedge clk) {a,b,c,d} <= 1;\n\t\t@(posedge clk) {a,b,c,d} <= 2;\n\t\t@(posedge clk) {a,b,c,d} <= 4;\n\t\t@(posedge clk) {a,b,c,d} <= 5;\n\t\t@(posedge clk) {a,b,c,d} <= 6;\n\t\t@(posedge clk) {a,b,c,d} <= 7;\n\t\t@(posedge clk) {a,b,c,d} <= 9;\n\t\t@(posedge clk) {a,b,c,d} <= 10;\n\t\t@(posedge clk) {a,b,c,d} <= 13;\n\t\t@(posedge clk) {a,b,c,d} <= 14;\n\t\t@(posedge clk) {a,b,c,d} <= 15;\n\t\t@(posedge clk) fail1 = fail;\n\t\t\n\t\t\n\t\t\t\t\n\t\t\n\t\t//@(negedge clk) wavedrom_start();\n\t\t\tfor (int i=0;i<16;i++)\n\t\t\t\t@(posedge clk)\n\t\t\t\t\t{a,b,c,d} <= i;\n\t\t//@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $random;\n\t\t\t\n\t\tif (fail && ~fail1)\n\t\t\t$display(\"Hint: Your circuit passes on the 12 required input combinations, but doesn't match the don't-care cases. Are you using minimal SOP and POS?\");\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_sop;\n\t\tint errortime_out_sop;\n\t\tint errors_out_pos;\n\t\tint errortime_out_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_sop_ref;\n\tlogic out_sop_dut;\n\tlogic out_pos_ref;\n\tlogic out_pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_sop_ref,out_sop_dut,out_pos_ref,out_pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_ref),\n\t\t.out_pos(out_pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_dut),\n\t\t.out_pos(out_pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_sop) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_sop\", stats1.errors_out_sop, stats1.errortime_out_sop);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_sop\");\n\t\tif (stats1.errors_out_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_pos\", stats1.errors_out_pos, stats1.errortime_out_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_sop_ref, out_pos_ref } === ( { out_sop_ref, out_pos_ref } ^ { out_sop_dut, out_pos_dut } ^ { out_sop_ref, out_pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_sop_ref !== ( out_sop_ref ^ out_sop_dut ^ out_sop_ref ))\n\t\tbegin if (stats1.errors_out_sop == 0) stats1.errortime_out_sop = $time;\n\t\t\tstats1.errors_out_sop = stats1.errors_out_sop+1'b1; end\n\t\tif (out_pos_ref !== ( out_pos_ref ^ out_pos_dut ^ out_pos_ref ))\n\t\tbegin if (stats1.errors_out_pos == 0) stats1.errortime_out_pos = $time;\n\t\t\tstats1.errors_out_pos = stats1.errors_out_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q2", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n", "canonical_solution": "\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out_sop,\n\toutput out_pos\n);\n\t\n\twire pos0, pos1;\n\tassign out_sop = c&d | ~a&~b&c;\n\tassign pos0 = c & (~b|d)&(~a|b);\n\tassign pos1 = c & (~b|d)&(~a|d);\n\t\n\tassign out_pos = (pos0 == pos1) ? pos0 : 1'bx;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tbit fail = 0;\n\tbit fail1 = 0;\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match)\n\t\t\tfail = 1;\n\n\tinitial begin\n\t\t@(posedge clk) {a,b,c,d} <= 0;\n\t\t@(posedge clk) {a,b,c,d} <= 1;\n\t\t@(posedge clk) {a,b,c,d} <= 2;\n\t\t@(posedge clk) {a,b,c,d} <= 4;\n\t\t@(posedge clk) {a,b,c,d} <= 5;\n\t\t@(posedge clk) {a,b,c,d} <= 6;\n\t\t@(posedge clk) {a,b,c,d} <= 7;\n\t\t@(posedge clk) {a,b,c,d} <= 9;\n\t\t@(posedge clk) {a,b,c,d} <= 10;\n\t\t@(posedge clk) {a,b,c,d} <= 13;\n\t\t@(posedge clk) {a,b,c,d} <= 14;\n\t\t@(posedge clk) {a,b,c,d} <= 15;\n\t\t@(posedge clk) fail1 = fail;\n\t\t\n\t\t\n\t\t\t\t\n\t\t\n\t\t//@(negedge clk) wavedrom_start();\n\t\t\tfor (int i=0;i<16;i++)\n\t\t\t\t@(posedge clk)\n\t\t\t\t\t{a,b,c,d} <= i;\n\t\t//@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d} <= $random;\n\t\t\t\n\t\tif (fail && ~fail1)\n\t\t\t$display(\"Hint: Your circuit passes on the 12 required input combinations, but doesn't match the don't-care cases. Are you using minimal SOP and POS?\");\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_sop;\n\t\tint errortime_out_sop;\n\t\tint errors_out_pos;\n\t\tint errortime_out_pos;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_sop_ref;\n\tlogic out_sop_dut;\n\tlogic out_pos_ref;\n\tlogic out_pos_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_sop_ref,out_sop_dut,out_pos_ref,out_pos_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_ref),\n\t\t.out_pos(out_pos_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out_sop(out_sop_dut),\n\t\t.out_pos(out_pos_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_sop) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_sop\", stats1.errors_out_sop, stats1.errortime_out_sop);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_sop\");\n\t\tif (stats1.errors_out_pos) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_pos\", stats1.errors_out_pos, stats1.errortime_out_pos);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_pos\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_sop_ref, out_pos_ref } === ( { out_sop_ref, out_pos_ref } ^ { out_sop_dut, out_pos_dut } ^ { out_sop_ref, out_pos_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_sop_ref !== ( out_sop_ref ^ out_sop_dut ^ out_sop_ref ))\n\t\tbegin if (stats1.errors_out_sop == 0) stats1.errortime_out_sop = $time;\n\t\t\tstats1.errors_out_sop = stats1.errors_out_sop+1'b1; end\n\t\tif (out_pos_ref !== ( out_pos_ref ^ out_pos_dut ^ out_pos_ref ))\n\t\tbegin if (stats1.errors_out_pos == 0) stats1.errortime_out_pos = $time;\n\t\t\tstats1.errors_out_pos = stats1.errors_out_pos+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q4", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n", "canonical_solution": "\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic [3:1] s,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\twire [3:0][2:0] val = { 3'h7, 3'h3, 3'h1, 3'h0 };\n\tinteger sval;\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 1;\n\t\treset_test();\n\t\t\n\t\t\n\t\t@(posedge clk) s <= 0;\n\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Water rises to highest level, then down to lowest level.\");\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\tsval = 0;\n\t\trepeat(1000) begin\n\t\t\t@(posedge clk);\n\t\t\t\tsval = sval + (sval == 3 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\t\t@(negedge clk);\n\t\t\t\tsval = sval - (sval == 0 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\tend\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_fr3;\n\t\tint errortime_fr3;\n\t\tint errors_fr2;\n\t\tint errortime_fr2;\n\t\tint errors_fr1;\n\t\tint errortime_fr1;\n\t\tint errors_dfr;\n\t\tint errortime_dfr;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] s;\n\tlogic fr3_ref;\n\tlogic fr3_dut;\n\tlogic fr2_ref;\n\tlogic fr2_dut;\n\tlogic fr1_ref;\n\tlogic fr1_dut;\n\tlogic dfr_ref;\n\tlogic dfr_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,fr3_ref,fr3_dut,fr2_ref,fr2_dut,fr1_ref,fr1_dut,dfr_ref,dfr_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_ref),\n\t\t.fr2(fr2_ref),\n\t\t.fr1(fr1_ref),\n\t\t.dfr(dfr_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_dut),\n\t\t.fr2(fr2_dut),\n\t\t.fr1(fr1_dut),\n\t\t.dfr(dfr_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_fr3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr3\", stats1.errors_fr3, stats1.errortime_fr3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr3\");\n\t\tif (stats1.errors_fr2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr2\", stats1.errors_fr2, stats1.errortime_fr2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr2\");\n\t\tif (stats1.errors_fr1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr1\", stats1.errors_fr1, stats1.errortime_fr1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr1\");\n\t\tif (stats1.errors_dfr) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"dfr\", stats1.errors_dfr, stats1.errortime_dfr);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"dfr\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } === ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ^ { fr3_dut, fr2_dut, fr1_dut, dfr_dut } ^ { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (fr3_ref !== ( fr3_ref ^ fr3_dut ^ fr3_ref ))\n\t\tbegin if (stats1.errors_fr3 == 0) stats1.errortime_fr3 = $time;\n\t\t\tstats1.errors_fr3 = stats1.errors_fr3+1'b1; end\n\t\tif (fr2_ref !== ( fr2_ref ^ fr2_dut ^ fr2_ref ))\n\t\tbegin if (stats1.errors_fr2 == 0) stats1.errortime_fr2 = $time;\n\t\t\tstats1.errors_fr2 = stats1.errors_fr2+1'b1; end\n\t\tif (fr1_ref !== ( fr1_ref ^ fr1_dut ^ fr1_ref ))\n\t\tbegin if (stats1.errors_fr1 == 0) stats1.errortime_fr1 = $time;\n\t\t\tstats1.errors_fr1 = stats1.errors_fr1+1'b1; end\n\t\tif (dfr_ref !== ( dfr_ref ^ dfr_dut ^ dfr_ref ))\n\t\tbegin if (stats1.errors_dfr == 0) stats1.errortime_dfr = $time;\n\t\t\tstats1.errors_dfr = stats1.errors_dfr+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2013_q4", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n", "canonical_solution": "\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput [3:1] s,\n\toutput reg fr3,\n\toutput reg fr2,\n\toutput reg fr1,\n\toutput reg dfr\n);\n\tparameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= A2;\n\t\telse state <= next;\n\tend\n\t\n\talways@(*) begin\n\t\tcase (state)\n\t\t\tA2: next = s[1] ? B1 : A2;\n\t\t\tB1: next = s[2] ? C1 : (s[1] ? B1 : A2);\n\t\t\tB2: next = s[2] ? C1 : (s[1] ? B2 : A2);\n\t\t\tC1: next = s[3] ? D1 : (s[2] ? C1 : B2);\n\t\t\tC2: next = s[3] ? D1 : (s[2] ? C2 : B2);\n\t\t\tD1: next = s[3] ? D1 : C2;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\treg [3:0] fr;\n\tassign {fr3, fr2, fr1, dfr} = fr;\n\talways_comb begin\n\t\tcase (state)\n\t\t\tA2: fr = 4'b1111;\n\t\t\tB1: fr = 4'b0110;\n\t\t\tB2: fr = 4'b0111;\n\t\t\tC1: fr = 4'b0010;\n\t\t\tC2: fr = 4'b0011;\n\t\t\tD1: fr = 4'b0000;\n\t\t\tdefault: fr = 'x;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic [3:1] s,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\twire [3:0][2:0] val = { 3'h7, 3'h3, 3'h1, 3'h0 };\n\tinteger sval;\n\tinitial begin\n\t\treset <= 1;\n\t\ts <= 1;\n\t\treset_test();\n\t\t\n\t\t\n\t\t@(posedge clk) s <= 0;\n\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_start(\"Water rises to highest level, then down to lowest level.\");\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 7;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 3;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 1;\n\t\t\t@(posedge clk) s <= 0;\n\t\t\t@(posedge clk) s <= 0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\tsval = 0;\n\t\trepeat(1000) begin\n\t\t\t@(posedge clk);\n\t\t\t\tsval = sval + (sval == 3 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\t\t@(negedge clk);\n\t\t\t\tsval = sval - (sval == 0 ? 0 : $random&1);\n\t\t\t\ts <= val[sval];\n\t\tend\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_fr3;\n\t\tint errortime_fr3;\n\t\tint errors_fr2;\n\t\tint errortime_fr2;\n\t\tint errors_fr1;\n\t\tint errortime_fr1;\n\t\tint errors_dfr;\n\t\tint errortime_dfr;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [3:1] s;\n\tlogic fr3_ref;\n\tlogic fr3_dut;\n\tlogic fr2_ref;\n\tlogic fr2_dut;\n\tlogic fr1_ref;\n\tlogic fr1_dut;\n\tlogic dfr_ref;\n\tlogic dfr_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,fr3_ref,fr3_dut,fr2_ref,fr2_dut,fr1_ref,fr1_dut,dfr_ref,dfr_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.s );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_ref),\n\t\t.fr2(fr2_ref),\n\t\t.fr1(fr1_ref),\n\t\t.dfr(dfr_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.s,\n\t\t.fr3(fr3_dut),\n\t\t.fr2(fr2_dut),\n\t\t.fr1(fr1_dut),\n\t\t.dfr(dfr_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_fr3) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr3\", stats1.errors_fr3, stats1.errortime_fr3);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr3\");\n\t\tif (stats1.errors_fr2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr2\", stats1.errors_fr2, stats1.errortime_fr2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr2\");\n\t\tif (stats1.errors_fr1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fr1\", stats1.errors_fr1, stats1.errortime_fr1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fr1\");\n\t\tif (stats1.errors_dfr) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"dfr\", stats1.errors_dfr, stats1.errortime_dfr);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"dfr\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } === ( { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ^ { fr3_dut, fr2_dut, fr1_dut, dfr_dut } ^ { fr3_ref, fr2_ref, fr1_ref, dfr_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (fr3_ref !== ( fr3_ref ^ fr3_dut ^ fr3_ref ))\n\t\tbegin if (stats1.errors_fr3 == 0) stats1.errortime_fr3 = $time;\n\t\t\tstats1.errors_fr3 = stats1.errors_fr3+1'b1; end\n\t\tif (fr2_ref !== ( fr2_ref ^ fr2_dut ^ fr2_ref ))\n\t\tbegin if (stats1.errors_fr2 == 0) stats1.errortime_fr2 = $time;\n\t\t\tstats1.errors_fr2 = stats1.errors_fr2+1'b1; end\n\t\tif (fr1_ref !== ( fr1_ref ^ fr1_dut ^ fr1_ref ))\n\t\tbegin if (stats1.errors_fr1 == 0) stats1.errortime_fr1 = $time;\n\t\t\tstats1.errors_fr1 = stats1.errors_fr1+1'b1; end\n\t\tif (dfr_ref !== ( dfr_ref ^ dfr_dut ^ dfr_ref ))\n\t\tbegin if (stats1.errors_dfr == 0) stats1.errortime_dfr = $time;\n\t\t\tstats1.errors_dfr = stats1.errors_dfr+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q1c", "prompt": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n", "canonical_solution": "\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {a, b} <= 16'h0;\n\t\t\t@(posedge clk) {a, b} <= 16'h0070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7090;\n\t\t\t@(posedge clk) {a, b} <= 16'h9070;\n\t\t\t@(posedge clk) {a, b} <= 16'h9090;\n\t\t\t@(posedge clk) {a, b} <= 16'h90ff;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_s;\n\t\tint errortime_s;\n\t\tint errors_overflow;\n\t\tint errortime_overflow;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] s_ref;\n\tlogic [7:0] s_dut;\n\tlogic overflow_ref;\n\tlogic overflow_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_ref),\n\t\t.overflow(overflow_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_dut),\n\t\t.overflow(overflow_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_s) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"s\", stats1.errors_s, stats1.errortime_s);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"s\");\n\t\tif (stats1.errors_overflow) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"overflow\", stats1.errors_overflow, stats1.errortime_overflow);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"overflow\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (s_ref !== ( s_ref ^ s_dut ^ s_ref ))\n\t\tbegin if (stats1.errors_s == 0) stats1.errortime_s = $time;\n\t\t\tstats1.errors_s = stats1.errors_s+1'b1; end\n\t\tif (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))\n\t\tbegin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;\n\t\t\tstats1.errors_overflow = stats1.errors_overflow+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q1c", "prompt": "module top_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n", "canonical_solution": "\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] a,\n\tinput [7:0] b,\n\toutput [7:0] s,\n\toutput overflow\n);\n\t\n\twire [8:0] sum = a+b;\n\tassign s = sum[7:0];\n\tassign overflow = !(a[7]^b[7]) && (a[7] != s[7]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {a, b} <= 16'h0;\n\t\t\t@(posedge clk) {a, b} <= 16'h0070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7070;\n\t\t\t@(posedge clk) {a, b} <= 16'h7090;\n\t\t\t@(posedge clk) {a, b} <= 16'h9070;\n\t\t\t@(posedge clk) {a, b} <= 16'h9090;\n\t\t\t@(posedge clk) {a, b} <= 16'h90ff;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_s;\n\t\tint errortime_s;\n\t\tint errors_overflow;\n\t\tint errortime_overflow;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] a;\n\tlogic [7:0] b;\n\tlogic [7:0] s_ref;\n\tlogic [7:0] s_dut;\n\tlogic overflow_ref;\n\tlogic overflow_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_ref),\n\t\t.overflow(overflow_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.s(s_dut),\n\t\t.overflow(overflow_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_s) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"s\", stats1.errors_s, stats1.errortime_s);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"s\");\n\t\tif (stats1.errors_overflow) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"overflow\", stats1.errors_overflow, stats1.errortime_overflow);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"overflow\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (s_ref !== ( s_ref ^ s_dut ^ s_ref ))\n\t\tbegin if (stats1.errors_s == 0) stats1.errortime_s = $time;\n\t\t\tstats1.errors_s = stats1.errors_s+1'b1; end\n\t\tif (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))\n\t\tbegin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;\n\t\t\tstats1.errors_overflow = stats1.errors_overflow+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q3", "prompt": "module top_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n", "canonical_solution": "\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{c, d} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {c, d} <= 2'h0;\n\t\t\t@(posedge clk) {c, d} <= 2'h1;\n\t\t\t@(posedge clk) {c, d} <= 2'h2;\n\t\t\t@(posedge clk) {c, d} <= 2'h3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{c,d} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_mux_in;\n\t\tint errortime_mux_in;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic c;\n\tlogic d;\n\tlogic [3:0] mux_in_ref;\n\tlogic [3:0] mux_in_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,c,d,mux_in_ref,mux_in_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_mux_in) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mux_in\", stats1.errors_mux_in, stats1.errortime_mux_in);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mux_in\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { mux_in_ref } === ( { mux_in_ref } ^ { mux_in_dut } ^ { mux_in_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (mux_in_ref !== ( mux_in_ref ^ mux_in_dut ^ mux_in_ref ))\n\t\tbegin if (stats1.errors_mux_in == 0) stats1.errortime_mux_in = $time;\n\t\t\tstats1.errors_mux_in = stats1.errors_mux_in+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q3", "prompt": "module top_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n", "canonical_solution": "\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput c,\n\tinput d,\n\toutput [3:0] mux_in\n);\n\t\n\tassign mux_in[0] = c | d;\n\tassign mux_in[1] = 0;\n\tassign mux_in[2] = ~d;\t\n\tassign mux_in[3] = c&d;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{c, d} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {c, d} <= 2'h0;\n\t\t\t@(posedge clk) {c, d} <= 2'h1;\n\t\t\t@(posedge clk) {c, d} <= 2'h2;\n\t\t\t@(posedge clk) {c, d} <= 2'h3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(50) @(posedge clk, negedge clk)\n\t\t\t{c,d} <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_mux_in;\n\t\tint errortime_mux_in;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic c;\n\tlogic d;\n\tlogic [3:0] mux_in_ref;\n\tlogic [3:0] mux_in_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,c,d,mux_in_ref,mux_in_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.c,\n\t\t.d,\n\t\t.mux_in(mux_in_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_mux_in) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"mux_in\", stats1.errors_mux_in, stats1.errortime_mux_in);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"mux_in\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { mux_in_ref } === ( { mux_in_ref } ^ { mux_in_dut } ^ { mux_in_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (mux_in_ref !== ( mux_in_ref ^ mux_in_dut ^ mux_in_ref ))\n\t\tbegin if (stats1.errors_mux_in == 0) stats1.errortime_mux_in = $time;\n\t\t\tstats1.errors_mux_in = stats1.errors_mux_in+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q4", "prompt": "module top_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tx <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q4", "prompt": "module top_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput x,\n\toutput z\n);\n\t\n\treg [2:0] s = 0;\n\t\n\talways @(posedge clk) begin\n\t\ts <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };\t\t\n\tend\n\t\n\tassign z = ~|s;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h0;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t\t@(posedge clk) x <= 2'h1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tx <= $random;\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5a", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5a", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1,C=2;\n\treg [1:0] state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? C : A;\n\t\t\t\tB: state <= x ? B : C;\n\t\t\t\tC: state <= x ? B : C;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == C);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5b", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ece241_2014_q5b", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n", "canonical_solution": "\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput x,\n\toutput z\n);\n\n\tparameter A=0,B=1;\n\treg state;\n\talways @(posedge clk, posedge areset) begin\n\t\tif (areset)\n\t\t\tstate <= A;\n\t\telse begin\n\t\t\tcase (state)\n\t\t\t\tA: state <= x ? B : A;\n\t\t\t\tB: state <= B;\n\t\t\tendcase\n\t\tend\n\tend\n\t\n\tassign z = (state == A && x==1) | (state == B && x==0);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n\tinitial begin\n\t\tx <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0; x <= 1;\n\t\t@(posedge clk) x <= 0;\n\t\treset_test(1);\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {reset,x} <= 2'h2;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h1;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t\t@(posedge clk) {reset,x} <= 2'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk)\n\t\t\t{reset,x} <= {($random&31) == 0, ($random&1)==0 };\n\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic x;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.x );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.x,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgecapture", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n", "canonical_solution": "\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [31:0] in,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 1;\n\t\tin = 0;\n\t\t@(negedge clk) wavedrom_start(\"Example\");\n\t\trepeat(1) @(posedge clk);\n\t\treset = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(4) @(posedge clk);\n\t\tin = 32'he;\n\t\trepeat(2) @(posedge clk);\n\t\tin = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(2) @(posedge clk);\n\t\treset = 1;\n\t\t@(posedge clk);\n\t\treset = 0; in = 0;\n\t\trepeat(3) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\n\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(1) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 32'h10;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\treset <= 1;\n\t\trepeat(1) @(posedge clk);\n\t\tin <= 32'h0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 1;\n\t\tin <= 32'h20;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\tin <= 32'h00;\n\t\n\t\trepeat(2) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) begin\n\t\t\t\tin <= $random;\n\t\t\t\treset <= !($random & 15);\n\t\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgecapture", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n", "canonical_solution": "\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput [31:0] in,\n\toutput reg [31:0] out);\n\t\n\treg [31:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tif (reset)\n\t\t\tout <= '0;\n\t\telse\n\t\t\tout <= out | (~in & d_last);\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [31:0] in,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\treset <= 1;\n\t\t@(posedge clk);\n\t\treset <= 1;\n\t\tin = 0;\n\t\t@(negedge clk) wavedrom_start(\"Example\");\n\t\trepeat(1) @(posedge clk);\n\t\treset = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(4) @(posedge clk);\n\t\tin = 32'he;\n\t\trepeat(2) @(posedge clk);\n\t\tin = 0;\n\t\t@(posedge clk) in = 32'h2;\n\t\trepeat(2) @(posedge clk);\n\t\treset = 1;\n\t\t@(posedge clk);\n\t\treset = 0; in = 0;\n\t\trepeat(3) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\n\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(1) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 32'h10;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\treset <= 1;\n\t\trepeat(1) @(posedge clk);\n\t\tin <= 32'h0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 1;\n\t\tin <= 32'h20;\n\t\trepeat(1) @(posedge clk);\n\t\treset <= 0;\n\t\tin <= 32'h00;\n\t\n\t\trepeat(2) @(posedge clk);\n\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) begin\n\t\t\t\tin <= $random;\n\t\t\t\treset <= !($random & 15);\n\t\t\tend\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgedetect", "prompt": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n", "canonical_solution": "\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(4) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) in <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pedge;\n\t\tint errortime_pedge;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] pedge_ref;\n\tlogic [7:0] pedge_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,pedge_ref,pedge_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pedge) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pedge\", stats1.errors_pedge, stats1.errortime_pedge);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pedge\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pedge_ref } === ( { pedge_ref } ^ { pedge_dut } ^ { pedge_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pedge_ref !== ( pedge_ref ^ pedge_dut ^ pedge_ref ))\n\t\tbegin if (stats1.errors_pedge == 0) stats1.errortime_pedge = $time;\n\t\t\tstats1.errors_pedge = stats1.errors_pedge+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgedetect", "prompt": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n", "canonical_solution": "\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] pedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tpedge <= in & ~d_last;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\twavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(4) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) in <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_pedge;\n\t\tint errortime_pedge;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] pedge_ref;\n\tlogic [7:0] pedge_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,pedge_ref,pedge_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.pedge(pedge_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_pedge) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"pedge\", stats1.errors_pedge, stats1.errortime_pedge);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"pedge\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { pedge_ref } === ( { pedge_ref } ^ { pedge_dut } ^ { pedge_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (pedge_ref !== ( pedge_ref ^ pedge_dut ^ pedge_ref ))\n\t\tbegin if (stats1.errors_pedge == 0) stats1.errortime_pedge = $time;\n\t\t\tstats1.errors_pedge = stats1.errors_pedge+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "edgedetect2", "prompt": "module top_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] anyedge);\n", "canonical_solution": "\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tanyedge <= in ^ d_last;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput [7:0] in,\n\toutput reg [7:0] anyedge);\n\t\n\treg [7:0] d_last;\t\n\t\t\t\n\talways @(posedge clk) begin\n\t\td_last <= in;\n\t\tanyedge <= in ^ d_last;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput reg [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\t@(negedge clk) wavedrom_start(\"\");\n\t\trepeat(2) @(posedge clk);\n\t\tin <= 1;\n\t\trepeat(4) @(posedge clk);\n\t\tin <= 0;\n\t\trepeat(4) @(negedge clk);\n\t\tin <= 6;\n\t\trepeat(2) @(negedge clk);\n\t\tin <= 0;\t\t\n\t\trepeat(2) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) in <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_anyedge;\n\t\tint errortime_anyedge;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] anyedge_ref;\n\tlogic [7:0] anyedge_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,anyedge_ref,anyedge_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.anyedge(anyedge_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.anyedge(anyedge_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_anyedge) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"anyedge\", stats1.errors_anyedge, stats1.errortime_anyedge);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"anyedge\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { anyedge_ref } === ( { anyedge_ref } ^ { anyedge_dut } ^ { anyedge_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (anyedge_ref !== ( anyedge_ref ^ anyedge_dut ^ anyedge_ref ))\n\t\tbegin if (stats1.errors_anyedge == 0) stats1.errortime_anyedge = $time;\n\t\t\tstats1.errors_anyedge = stats1.errors_anyedge+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fadd", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n", "canonical_solution": "\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,cin,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start();\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b010;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b100;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b110;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b001;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b011;\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{a,b,cin} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic cin;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,cin,cout_ref,cout_dut,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.cin );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_ref),\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_dut),\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { cout_ref, sum_ref } === ( { cout_ref, sum_ref } ^ { cout_dut, sum_dut } ^ { cout_ref, sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fadd", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n", "canonical_solution": "\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput cin,\n\toutput cout,\n\toutput sum\n);\n\n\tassign {cout, sum} = a+b+cin;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,cin,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start();\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b010;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b100;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b110;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b000;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b001;\n\t\t\t@(posedge clk) {a,b,cin} <= 3'b011;\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{a,b,cin} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic cin;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,cin,cout_ref,cout_dut,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.cin );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_ref),\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.cin,\n\t\t.cout(cout_dut),\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { cout_ref, sum_ref } === ( { cout_ref, sum_ref } ^ { cout_dut, sum_dut } ^ { cout_ref, sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(1);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(1);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1s", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(0);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm1s", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? A : B;\n\t\t\tB: next = in ? B : A;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= B;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0; in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\treset_test(0);\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2", "prompt": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test(1);\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2", "prompt": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test(1);\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2s", "prompt": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test();\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm2s", "prompt": "module top_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput j,\n\tinput k,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = j ? B : A;\n\t\t\tB: next = k ? A : B;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==B);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic j, k,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\treg [0:11][1:0] d = 24'b000101010010101111111111;\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tj <= 0;\n\t\tk <= 0;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tj <= 1;\n\t\t@(posedge clk);\n\t\tj <= 0;\n\t\twavedrom_start(\"Reset and transitions\");\n\t\treset_test();\n\t\tfor (int i=0;i<12;i++)\n\t\t\t@(posedge clk) {k, j} <= d[i];\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{j,k} <= $random;\n\t\t\treset <= !($random & 7);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic j;\n\tlogic k;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.j,\n\t\t.k,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.j,\n\t\t.k,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput areset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic areset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic areset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.areset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.areset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3comb", "prompt": "module top_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [1:0] state\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [1:0] state;\n\tlogic [1:0] next_state_ref;\n\tlogic [1:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3comb", "prompt": "module top_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [1:0] state,\n\toutput reg [1:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next_state = in ? B : A;\n\t\t\tB: next_state = in ? B : C;\n\t\t\tC: next_state = in ? D : A;\n\t\t\tD: next_state = in ? B : C;\n\t\tendcase\n    end\n    \n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [1:0] state\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [1:0] state;\n\tlogic [1:0] next_state_ref;\n\tlogic [1:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3onehot", "prompt": "module top_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [3:0] state,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 4);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [3:0] state;\n\tlogic [3:0] next_state_ref;\n\tlogic [3:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3onehot", "prompt": "module top_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [3:0] state,\n\toutput reg [3:0] next_state,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n    \n    assign next_state[A] = (state[A] | state[C]) & ~in;\n    assign next_state[B] = (state[A] | state[B] | state[D]) & in;\n    assign next_state[C] = (state[B] | state[D]) & ~in;\n    assign next_state[D] = state[C] & in;\n    \n\tassign out = (state[D]);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [3:0] state,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 4);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [3:0] state;\n\tlogic [3:0] next_state_ref;\n\tlogic [3:0] next_state_dut;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3s", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm3s", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput out\n);\n\tparameter A=0, B=1, C=2, D=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tA: next = in ? B : A;\n\t\t\tB: next = in ? B : C;\n\t\t\tC: next = in ? D : A;\n\t\t\tD: next = in ? B : C;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= A;\n        else state <= next;\n\tend\n\t\t\n\tassign out = (state==D);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk) reset <= 0; in <= 1;\n\t\t@(posedge clk) in <= 0;\n\t\t@(posedge clk) in <= 1;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk);\n\t\t\t@(negedge clk) reset <= 1;\n\t\t\t@(posedge clk) reset <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 0;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t\t@(posedge clk) in <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_hdlc", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n", "canonical_solution": "\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset, in\n);\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tin <= |($random&7);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_disc;\n\t\tint errortime_disc;\n\t\tint errors_flag;\n\t\tint errortime_flag;\n\t\tint errors_err;\n\t\tint errortime_err;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic in;\n\tlogic disc_ref;\n\tlogic disc_dut;\n\tlogic flag_ref;\n\tlogic flag_dut;\n\tlogic err_ref;\n\tlogic err_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,disc_ref,disc_dut,flag_ref,flag_dut,err_ref,err_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_ref),\n\t\t.flag(flag_ref),\n\t\t.err(err_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_dut),\n\t\t.flag(flag_dut),\n\t\t.err(err_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_disc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"disc\", stats1.errors_disc, stats1.errortime_disc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"disc\");\n\t\tif (stats1.errors_flag) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"flag\", stats1.errors_flag, stats1.errortime_flag);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"flag\");\n\t\tif (stats1.errors_err) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"err\", stats1.errors_err, stats1.errortime_err);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"err\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { disc_ref, flag_ref, err_ref } === ( { disc_ref, flag_ref, err_ref } ^ { disc_dut, flag_dut, err_dut } ^ { disc_ref, flag_ref, err_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (disc_ref !== ( disc_ref ^ disc_dut ^ disc_ref ))\n\t\tbegin if (stats1.errors_disc == 0) stats1.errortime_disc = $time;\n\t\t\tstats1.errors_disc = stats1.errors_disc+1'b1; end\n\t\tif (flag_ref !== ( flag_ref ^ flag_dut ^ flag_ref ))\n\t\tbegin if (stats1.errors_flag == 0) stats1.errortime_flag = $time;\n\t\t\tstats1.errors_flag = stats1.errors_flag+1'b1; end\n\t\tif (err_ref !== ( err_ref ^ err_dut ^ err_ref ))\n\t\tbegin if (stats1.errors_err == 0) stats1.errortime_err = $time;\n\t\t\tstats1.errors_err = stats1.errors_err+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_hdlc", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n", "canonical_solution": "\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput in,\n\toutput disc,\n\toutput flag,\n\toutput err);\n\t\n\tparameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;\n\treg [3:0] state, next;\n\n\tassign disc = state == SDISC;\n\tassign flag = state == SFLAG;\n\tassign err = state == SERR;\n\t\n\talways @(posedge clk) begin\n\t\tcase (state)\n\t\t\tS0: state <= in ? S1 : S0;\n\t\t\tS1: state <= in ? S2 : S0;\n\t\t\tS2: state <= in ? S3 : S0;\n\t\t\tS3: state <= in ? S4 : S0;\n\t\t\tS4: state <= in ? S5 : S0;\n\t\t\tS5: state <= in ? S6 : SDISC;\n\t\t\tS6: state <= in ? SERR : SFLAG;\n\t\t\tSERR: state <= in ? SERR : S0;\n\t\t\tSFLAG: state <= in ? S1 : S0;\n\t\t\tSDISC: state <= in ? S1 : S0;\n\t\t\tdefault: state <= 'x;\n\t\tendcase\n\t\t\n\t\tif (reset) state <= S0;\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset, in\n);\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 0;\n\t\t@(posedge clk);\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tin <= |($random&7);\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_disc;\n\t\tint errortime_disc;\n\t\tint errors_flag;\n\t\tint errortime_flag;\n\t\tint errors_err;\n\t\tint errortime_err;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic in;\n\tlogic disc_ref;\n\tlogic disc_dut;\n\tlogic flag_ref;\n\tlogic flag_dut;\n\tlogic err_ref;\n\tlogic err_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,disc_ref,disc_dut,flag_ref,flag_dut,err_ref,err_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_ref),\n\t\t.flag(flag_ref),\n\t\t.err(err_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.in,\n\t\t.disc(disc_dut),\n\t\t.flag(flag_dut),\n\t\t.err(err_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_disc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"disc\", stats1.errors_disc, stats1.errortime_disc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"disc\");\n\t\tif (stats1.errors_flag) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"flag\", stats1.errors_flag, stats1.errortime_flag);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"flag\");\n\t\tif (stats1.errors_err) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"err\", stats1.errors_err, stats1.errortime_err);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"err\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { disc_ref, flag_ref, err_ref } === ( { disc_ref, flag_ref, err_ref } ^ { disc_dut, flag_dut, err_dut } ^ { disc_ref, flag_ref, err_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (disc_ref !== ( disc_ref ^ disc_dut ^ disc_ref ))\n\t\tbegin if (stats1.errors_disc == 0) stats1.errortime_disc = $time;\n\t\t\tstats1.errors_disc = stats1.errors_disc+1'b1; end\n\t\tif (flag_ref !== ( flag_ref ^ flag_dut ^ flag_ref ))\n\t\tbegin if (stats1.errors_flag == 0) stats1.errortime_flag = $time;\n\t\t\tstats1.errors_flag = stats1.errors_flag+1'b1; end\n\t\tif (err_ref !== ( err_ref ^ err_dut ^ err_ref ))\n\t\tbegin if (stats1.errors_err == 0) stats1.errortime_err = $time;\n\t\t\tstats1.errors_err = stats1.errors_err+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_onehot", "prompt": "module top_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n", "canonical_solution": "\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [9:0] state,\n\tinput tb_match,\n\tinput [9:0] next_state_ref,\n\tinput [9:0] next_state_dut,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tint errored1 = 0;\n\tint errored2 = 0;\n\tint onehot_error = 0;\n\treg [9:0] state_error = 10'h0;\n\t\n\tinitial begin\n\t\trepeat(2) @(posedge clk);\n\t\tforever @(posedge clk, negedge clk)\n\t\t\tstate_error <= state_error | (next_state_ref^next_state_dut);\n\tend\n\t\t\n\tinitial begin\n\t\tstate <= 0;\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 0;\n\t\tend\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 1;\n\t\tend\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\n\t\t// Two-hot.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= (1<< ($unsigned($random) % 10)) | (1<< ($unsigned($random) % 10));\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\t\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with two-hot inputs.\");\n\t\t\n\t\t// Random.\n\t\terrored2 = 0;\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored2++;\n\t\tend\n\t\tif (!onehot_error && errored2) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && (errored1 || errored2))\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\t\n\t\tfor (int i=0;i<$bits(state_error);i++)\n\t\t\t$display(\"Hint: next_state[%0d] is %s.\", i, (state_error[i] === 1'b0) ? \"correct\": \"incorrect\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out1;\n\t\tint errortime_out1;\n\t\tint errors_out2;\n\t\tint errortime_out2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [9:0] state;\n\tlogic [9:0] next_state_ref;\n\tlogic [9:0] next_state_dut;\n\tlogic out1_ref;\n\tlogic out1_dut;\n\tlogic out2_ref;\n\tlogic out2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out1_ref,out1_dut,out2_ref,out2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out1(out1_ref),\n\t\t.out2(out2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out1(out1_dut),\n\t\t.out2(out2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out1\", stats1.errors_out1, stats1.errortime_out1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out1\");\n\t\tif (stats1.errors_out2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out2\", stats1.errors_out2, stats1.errortime_out2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out1_ref, out2_ref } === ( { next_state_ref, out1_ref, out2_ref } ^ { next_state_dut, out1_dut, out2_dut } ^ { next_state_ref, out1_ref, out2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out1_ref !== ( out1_ref ^ out1_dut ^ out1_ref ))\n\t\tbegin if (stats1.errors_out1 == 0) stats1.errortime_out1 = $time;\n\t\t\tstats1.errors_out1 = stats1.errors_out1+1'b1; end\n\t\tif (out2_ref !== ( out2_ref ^ out2_dut ^ out2_ref ))\n\t\tbegin if (stats1.errors_out2 == 0) stats1.errortime_out2 = $time;\n\t\t\tstats1.errors_out2 = stats1.errors_out2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_onehot", "prompt": "module top_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n", "canonical_solution": "\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in,\n\tinput [9:0] state,\n\toutput [9:0] next_state,\n\toutput out1,\n\toutput out2);\n\t\n\tassign out1 = state[8] | state[9];\n\tassign out2 = state[7] | state[9];\n\n\tassign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);\n\tassign next_state[1] = in && (state[0] | state[8] | state[9]);\n\tassign next_state[2] = in && state[1];\n\tassign next_state[3] = in && state[2];\n\tassign next_state[4] = in && state[3];\n\tassign next_state[5] = in && state[4];\n\tassign next_state[6] = in && state[5];\n\tassign next_state[7] = in && (state[6] | state[7]);\n\tassign next_state[8] = !in && state[5];\n\tassign next_state[9] = !in && state[6];\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic [9:0] state,\n\tinput tb_match,\n\tinput [9:0] next_state_ref,\n\tinput [9:0] next_state_dut,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tint errored1 = 0;\n\tint errored2 = 0;\n\tint onehot_error = 0;\n\treg [9:0] state_error = 10'h0;\n\t\n\tinitial begin\n\t\trepeat(2) @(posedge clk);\n\t\tforever @(posedge clk, negedge clk)\n\t\t\tstate_error <= state_error | (next_state_ref^next_state_dut);\n\tend\n\t\t\n\tinitial begin\n\t\tstate <= 0;\n\t\t\n\t\t@(negedge clk) wavedrom_start();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 0;\n\t\tend\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(negedge clk, posedge clk);\n\t\t\tstate <= 1<< i;\n\t\t\tin <= 1;\n\t\tend\t\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\t\tin <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\n\t\t// Two-hot.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tstate <= (1<< ($unsigned($random) % 10)) | (1<< ($unsigned($random) % 10));\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\t\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with two-hot inputs.\");\n\t\t\n\t\t// Random.\n\t\terrored2 = 0;\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tstate <= $random;\n\t\t\tin <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored2++;\n\t\tend\n\t\tif (!onehot_error && errored2) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\n\t\tif (!onehot_error && (errored1 || errored2))\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\t\n\t\tfor (int i=0;i<$bits(state_error);i++)\n\t\t\t$display(\"Hint: next_state[%0d] is %s.\", i, (state_error[i] === 1'b0) ? \"correct\": \"incorrect\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_next_state;\n\t\tint errortime_next_state;\n\t\tint errors_out1;\n\t\tint errortime_out1;\n\t\tint errors_out2;\n\t\tint errortime_out2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic [9:0] state;\n\tlogic [9:0] next_state_ref;\n\tlogic [9:0] next_state_dut;\n\tlogic out1_ref;\n\tlogic out1_dut;\n\tlogic out2_ref;\n\tlogic out2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out1_ref,out1_dut,out2_ref,out2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.state );\n\treference_module good1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_ref),\n\t\t.out1(out1_ref),\n\t\t.out2(out2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.state,\n\t\t.next_state(next_state_dut),\n\t\t.out1(out1_dut),\n\t\t.out2(out2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_next_state) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"next_state\", stats1.errors_next_state, stats1.errortime_next_state);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"next_state\");\n\t\tif (stats1.errors_out1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out1\", stats1.errors_out1, stats1.errortime_out1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out1\");\n\t\tif (stats1.errors_out2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out2\", stats1.errors_out2, stats1.errortime_out2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { next_state_ref, out1_ref, out2_ref } === ( { next_state_ref, out1_ref, out2_ref } ^ { next_state_dut, out1_dut, out2_dut } ^ { next_state_ref, out1_ref, out2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))\n\t\tbegin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;\n\t\t\tstats1.errors_next_state = stats1.errors_next_state+1'b1; end\n\t\tif (out1_ref !== ( out1_ref ^ out1_dut ^ out1_ref ))\n\t\tbegin if (stats1.errors_out1 == 0) stats1.errortime_out1 = $time;\n\t\t\tstats1.errors_out1 = stats1.errors_out1+1'b1; end\n\t\tif (out2_ref !== ( out2_ref ^ out2_dut ^ out2_ref ))\n\t\tbegin if (stats1.errors_out2 == 0) stats1.errortime_out2 = $time;\n\t\t\tstats1.errors_out2 = stats1.errors_out2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2", "prompt": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n", "canonical_solution": "\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2", "prompt": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n", "canonical_solution": "\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2data", "prompt": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n", "canonical_solution": "\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\treset <= 1'b0;\n\t\tin <= '0;\n\t\trepeat(10) @(posedge clk);\n\t\t\n\t\trepeat(200) begin\n\t\t\tin <= $random;\n\t\t\tin[3] <= 1'b1;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_bytes;\n\t\tint errortime_out_bytes;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic [23:0] out_bytes_ref;\n\tlogic [23:0] out_bytes_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_bytes_ref,out_bytes_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_bytes) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_bytes\", stats1.errors_out_bytes, stats1.errortime_out_bytes);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_bytes\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_bytes_ref, done_ref } === ( { out_bytes_ref, done_ref } ^ { out_bytes_dut, done_dut } ^ { out_bytes_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_bytes_ref !== ( out_bytes_ref ^ out_bytes_dut ^ out_bytes_ref ))\n\t\tbegin if (stats1.errors_out_bytes == 0) stats1.errortime_out_bytes = $time;\n\t\t\tstats1.errors_out_bytes = stats1.errors_out_bytes+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_ps2data", "prompt": "module top_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n", "canonical_solution": "\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput [7:0] in,\n\tinput reset,\n\toutput [23:0] out_bytes,\n\toutput done\n);\n\tparameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    wire in3 = in[3];\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tBYTE1: next = in3 ? BYTE2 : BYTE1;\n\t\t\tBYTE2: next = BYTE3;\n\t\t\tBYTE3: next = DONE;\n\t\t\tDONE: next = in3 ? BYTE2 : BYTE1;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= BYTE1;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\n\treg [23:0] out_bytes_r;\n\talways @(posedge clk)\n\t\tout_bytes_r <= {out_bytes_r[15:0], in};\n\t\n\t// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.\t\n\tassign out_bytes = done ? out_bytes_r : 'x;\t\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\trepeat(200) @(negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\treset <= 1'b0;\n\t\tin <= '0;\n\t\trepeat(10) @(posedge clk);\n\t\t\n\t\trepeat(200) begin\n\t\t\tin <= $random;\n\t\t\tin[3] <= 1'b1;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\t\tin <= $random;\n\t\t\t@(posedge clk);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_bytes;\n\t\tint errortime_out_bytes;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic reset;\n\tlogic [23:0] out_bytes_ref;\n\tlogic [23:0] out_bytes_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_bytes_ref,out_bytes_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_bytes(out_bytes_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_bytes) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_bytes\", stats1.errors_out_bytes, stats1.errortime_out_bytes);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_bytes\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_bytes_ref, done_ref } === ( { out_bytes_ref, done_ref } ^ { out_bytes_dut, done_dut } ^ { out_bytes_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_bytes_ref !== ( out_bytes_ref ^ out_bytes_dut ^ out_bytes_ref ))\n\t\tbegin if (stats1.errors_out_bytes == 0) stats1.errortime_out_bytes = $time;\n\t\t\tstats1.errors_out_bytes = stats1.errors_out_bytes+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serial", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n", "canonical_solution": "\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serial", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n", "canonical_solution": "\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\t\n\tassign done = (state==DONE);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serialdata", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n", "canonical_solution": "\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_byte;\n\t\tint errortime_out_byte;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic [7:0] out_byte_ref;\n\tlogic [7:0] out_byte_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_byte_ref,out_byte_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_byte) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_byte\", stats1.errors_out_byte, stats1.errortime_out_byte);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_byte\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_byte_ref, done_ref } === ( { out_byte_ref, done_ref } ^ { out_byte_dut, done_dut } ^ { out_byte_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_byte_ref !== ( out_byte_ref ^ out_byte_dut ^ out_byte_ref ))\n\t\tbegin if (stats1.errors_out_byte == 0) stats1.errortime_out_byte = $time;\n\t\t\tstats1.errors_out_byte = stats1.errors_out_byte+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "fsm_serialdata", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n", "canonical_solution": "\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\tinput reset,\n\toutput [7:0] out_byte,\n\toutput done\n);\n\tparameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;\n\treg [3:0] state;\n\treg [3:0] next;\n    \n    reg [9:0] byte_r;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tSTART: next = in ? START : B0;\t// start bit is 0\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = B4;\n\t\t\tB4: next = B5;\n\t\t\tB5: next = B6;\n\t\t\tB6: next = B7;\n\t\t\tB7: next = STOP;\n\t\t\tSTOP: next = in ? DONE : ERR;  // stop bit is 1. Idle state is 1.\n\t\t\tDONE: next = in ? START : B0;\n\t\t\tERR: next = in ? START : ERR;\n\t\tendcase\n    end\n    \n    always @(posedge clk) begin\n\t\tif (reset) state <= START;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tbyte_r <= {in, byte_r[9:1]};\n\tend\n\t\t\n\tassign done = (state==DONE);\n\tassign out_byte = done ? byte_r[8:1] : 8'hx;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in,\n\toutput logic reset\n);\n\n\tinitial begin\n\t\treset <= 1;\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(10) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\tin <= 0;\n\t\trepeat(9) @(posedge clk);\n\t\tin <= 1;\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(800) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_byte;\n\t\tint errortime_out_byte;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic reset;\n\tlogic [7:0] out_byte_ref;\n\tlogic [7:0] out_byte_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_byte_ref,out_byte_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.reset,\n\t\t.out_byte(out_byte_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_byte) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_byte\", stats1.errors_out_byte, stats1.errortime_out_byte);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_byte\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_byte_ref, done_ref } === ( { out_byte_ref, done_ref } ^ { out_byte_dut, done_dut } ^ { out_byte_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_byte_ref !== ( out_byte_ref ^ out_byte_dut ^ out_byte_ref ))\n\t\tbegin if (stats1.errors_out_byte == 0) stats1.errortime_out_byte = $time;\n\t\t\tstats1.errors_out_byte = stats1.errors_out_byte+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor,\n\toutput out_nand,\n\toutput out_nor,\n\toutput out_xnor,\n\toutput out_anotb\n);\n", "canonical_solution": "\n\tassign out_and = a&b;\n\tassign out_or = a|b;\n\tassign out_xor = a^b;\n\tassign out_nand = ~(a&b);\n\tassign out_nor = ~(a|b);\n\tassign out_xnor = a^~b;\n\tassign out_anotb = a & ~b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor,\n\toutput out_nand,\n\toutput out_nor,\n\toutput out_xnor,\n\toutput out_anotb\n);\n\n\tassign out_and = a&b;\n\tassign out_or = a|b;\n\tassign out_xor = a^b;\n\tassign out_nand = ~(a&b);\n\tassign out_nor = ~(a|b);\n\tassign out_xnor = a^~b;\n\tassign out_anotb = a & ~b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\t\n\tinitial begin\n\t\t@(negedge clk) {a,b} <= 0;\n\t\twavedrom_start();\n\t\t\t@(posedge clk) {a,b} <= 0;\n\t\t\t@(posedge clk) {a,b} <= 1;\n\t\t\t@(posedge clk) {a,b} <= 2;\n\t\t\t@(posedge clk) {a,b} <= 3;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t{a,b} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\t\tint errors_out_nand;\n\t\tint errortime_out_nand;\n\t\tint errors_out_nor;\n\t\tint errortime_out_nor;\n\t\tint errors_out_xnor;\n\t\tint errortime_out_xnor;\n\t\tint errors_out_anotb;\n\t\tint errortime_out_anotb;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\tlogic out_nand_ref;\n\tlogic out_nand_dut;\n\tlogic out_nor_ref;\n\tlogic out_nor_dut;\n\tlogic out_xnor_ref;\n\tlogic out_xnor_dut;\n\tlogic out_anotb_ref;\n\tlogic out_anotb_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut,out_nand_ref,out_nand_dut,out_nor_ref,out_nor_dut,out_xnor_ref,out_xnor_dut,out_anotb_ref,out_anotb_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref),\n\t\t.out_nand(out_nand_ref),\n\t\t.out_nor(out_nor_ref),\n\t\t.out_xnor(out_xnor_ref),\n\t\t.out_anotb(out_anotb_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut),\n\t\t.out_nand(out_nand_dut),\n\t\t.out_nor(out_nor_dut),\n\t\t.out_xnor(out_xnor_dut),\n\t\t.out_anotb(out_anotb_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\t\tif (stats1.errors_out_nand) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_nand\", stats1.errors_out_nand, stats1.errortime_out_nand);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_nand\");\n\t\tif (stats1.errors_out_nor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_nor\", stats1.errors_out_nor, stats1.errortime_out_nor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_nor\");\n\t\tif (stats1.errors_out_xnor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xnor\", stats1.errors_out_xnor, stats1.errortime_out_xnor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xnor\");\n\t\tif (stats1.errors_out_anotb) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_anotb\", stats1.errors_out_anotb, stats1.errortime_out_anotb);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_anotb\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } === ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ^ { out_and_dut, out_or_dut, out_xor_dut, out_nand_dut, out_nor_dut, out_xnor_dut, out_anotb_dut } ^ { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\t\tif (out_nand_ref !== ( out_nand_ref ^ out_nand_dut ^ out_nand_ref ))\n\t\tbegin if (stats1.errors_out_nand == 0) stats1.errortime_out_nand = $time;\n\t\t\tstats1.errors_out_nand = stats1.errors_out_nand+1'b1; end\n\t\tif (out_nor_ref !== ( out_nor_ref ^ out_nor_dut ^ out_nor_ref ))\n\t\tbegin if (stats1.errors_out_nor == 0) stats1.errortime_out_nor = $time;\n\t\t\tstats1.errors_out_nor = stats1.errors_out_nor+1'b1; end\n\t\tif (out_xnor_ref !== ( out_xnor_ref ^ out_xnor_dut ^ out_xnor_ref ))\n\t\tbegin if (stats1.errors_out_xnor == 0) stats1.errortime_out_xnor = $time;\n\t\t\tstats1.errors_out_xnor = stats1.errors_out_xnor+1'b1; end\n\t\tif (out_anotb_ref !== ( out_anotb_ref ^ out_anotb_dut ^ out_anotb_ref ))\n\t\tbegin if (stats1.errors_out_anotb == 0) stats1.errortime_out_anotb = $time;\n\t\t\tstats1.errors_out_anotb = stats1.errors_out_anotb+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates100", "prompt": "module top_module (\n\tinput [99:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n", "canonical_solution": "\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [99:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treg [3:0] count; count = 0;\n\t\tin <= 100'h0;\n\t\t// AND gate uses huge numbers and creates a sparse waveform.\n\t\t@(negedge clk) wavedrom_start(\"Test AND gate\");\n\t\t\t@(posedge clk,negedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h0;\t\t// Test AND gate\n\t\t\t@(posedge clk,negedge clk); in <= 100'h3ffff;\t\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h3ffff;\t\n\t\t\t@(posedge clk,negedge clk); in <= 100'h80;\t\t\n\t\t\t@(posedge clk,negedge clk); in <= ~100'h80;\t\t\n\t\twavedrom_stop();\n\n\t\t@(negedge clk) wavedrom_start(\"Test OR and XOR gates\");\n\t\t\t@(posedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t\t@(posedge clk); in <= 100'h7;\t\t// Test AND gate\n\t\t\trepeat(10) @(posedge clk, negedge clk) begin\n\t\t\t\tin <= count;\t\t\n\t\t\t\tcount <= count + 1;\n\t\t\tend\n\t\t\t@(posedge clk) in <= 100'h0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\tfor (int i=0;i<100;i++) begin\n\t\t\t@(negedge clk) in <= 100'h1<<i;\n\t\t\t@(posedge clk) in <= ~(100'h1<<i);\n\t\tend\n\t\t@(posedge clk) in <= 100'h0;\t\t// Test OR gate\n\t\t@(posedge clk); in <= ~100'h0;\t\t// Test AND gate\n\t\t@(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gates4", "prompt": "module top_module (\n\tinput [3:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n", "canonical_solution": "\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput out_and,\n\toutput out_or,\n\toutput out_xor\n);\n\n\tassign out_and = &in;\n\tassign out_or = |in;\n\tassign out_xor = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(negedge clk) wavedrom_start(\"All combinations\");\n\t\t\t@(posedge clk);\n\t\t\trepeat(15) @(posedge clk) in <= in + 1;\n\t\t@(negedge clk) wavedrom_stop();\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_and;\n\t\tint errortime_out_and;\n\t\tint errors_out_or;\n\t\tint errortime_out_or;\n\t\tint errors_out_xor;\n\t\tint errortime_out_xor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic out_and_ref;\n\tlogic out_and_dut;\n\tlogic out_or_ref;\n\tlogic out_or_dut;\n\tlogic out_xor_ref;\n\tlogic out_xor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_and(out_and_ref),\n\t\t.out_or(out_or_ref),\n\t\t.out_xor(out_xor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_and(out_and_dut),\n\t\t.out_or(out_or_dut),\n\t\t.out_xor(out_xor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_and) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_and\", stats1.errors_out_and, stats1.errortime_out_and);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_and\");\n\t\tif (stats1.errors_out_or) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or\", stats1.errors_out_or, stats1.errortime_out_or);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or\");\n\t\tif (stats1.errors_out_xor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_xor\", stats1.errors_out_xor, stats1.errortime_out_xor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_xor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))\n\t\tbegin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;\n\t\t\tstats1.errors_out_and = stats1.errors_out_and+1'b1; end\n\t\tif (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))\n\t\tbegin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;\n\t\t\tstats1.errors_out_or = stats1.errors_out_or+1'b1; end\n\t\tif (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))\n\t\tbegin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;\n\t\t\tstats1.errors_out_xor = stats1.errors_out_xor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv", "prompt": "module top_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n", "canonical_solution": "\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [3:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tin <= 4'h3;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 3;\n\t\t\t@(posedge clk) in <= 6;\n\t\t\t@(posedge clk) in <= 12;\n\t\t\t@(posedge clk) in <= 9;\n\t\t\t@(posedge clk) in <= 5;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic [2:0] out_both_ref;\n\tlogic [2:0] out_both_dut;\n\tlogic [3:1] out_any_ref;\n\tlogic [3:1] out_any_dut;\n\tlogic [3:0] out_different_ref;\n\tlogic [3:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv", "prompt": "module top_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n", "canonical_solution": "\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] in,\n\toutput [2:0] out_both,\n\toutput [3:1] out_any,\n\toutput [3:0] out_different\n);\n\n\tassign out_both = in[2:0] & in[3:1];\n\tassign out_any = in[2:0] | in[3:1];\n\tassign out_different = in^{in[0], in[3:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [3:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tin <= 4'h3;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\t@(posedge clk) in <= 3;\n\t\t\t@(posedge clk) in <= 6;\n\t\t\t@(posedge clk) in <= 12;\n\t\t\t@(posedge clk) in <= 9;\n\t\t\t@(posedge clk) in <= 5;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] in;\n\tlogic [2:0] out_both_ref;\n\tlogic [2:0] out_both_dut;\n\tlogic [3:1] out_any_ref;\n\tlogic [3:1] out_any_dut;\n\tlogic [3:0] out_different_ref;\n\tlogic [3:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv100", "prompt": "module top_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n", "canonical_solution": "\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [99:0] in\n);\n\n\tinitial begin\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [98:0] out_both_ref;\n\tlogic [98:0] out_both_dut;\n\tlogic [99:1] out_any_ref;\n\tlogic [99:1] out_any_dut;\n\tlogic [99:0] out_different_ref;\n\tlogic [99:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gatesv100", "prompt": "module top_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n", "canonical_solution": "\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput [98:0] out_both,\n\toutput [99:1] out_any,\n\toutput [99:0] out_different\n);\n\n\tassign out_both = in & in[99:1];\n\tassign out_any = in | in[99:1];\n\tassign out_different = in^{in[0], in[99:1]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\tinput tb_match,\n\toutput logic [99:0] in\n);\n\n\tinitial begin\n\t\tin <= $random;\n\t\trepeat(100) begin\n\t\t\t@(negedge clk) in <= $random;\n\t\t\t@(posedge clk) in <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_both;\n\t\tint errortime_out_both;\n\t\tint errors_out_any;\n\t\tint errortime_out_any;\n\t\tint errors_out_different;\n\t\tint errortime_out_different;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [98:0] out_both_ref;\n\tlogic [98:0] out_both_dut;\n\tlogic [99:1] out_any_ref;\n\tlogic [99:1] out_any_dut;\n\tlogic [99:0] out_different_ref;\n\tlogic [99:0] out_different_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out_both(out_both_ref),\n\t\t.out_any(out_any_ref),\n\t\t.out_different(out_different_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out_both(out_both_dut),\n\t\t.out_any(out_any_dut),\n\t\t.out_different(out_different_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_both) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_both\", stats1.errors_out_both, stats1.errortime_out_both);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_both\");\n\t\tif (stats1.errors_out_any) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_any\", stats1.errors_out_any, stats1.errortime_out_any);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_any\");\n\t\tif (stats1.errors_out_different) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_different\", stats1.errors_out_different, stats1.errortime_out_different);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_different\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))\n\t\tbegin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;\n\t\t\tstats1.errors_out_both = stats1.errors_out_both+1'b1; end\n\t\tif (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))\n\t\tbegin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;\n\t\t\tstats1.errors_out_any = stats1.errors_out_any+1'b1; end\n\t\tif (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))\n\t\tbegin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;\n\t\t\tstats1.errors_out_different = stats1.errors_out_different+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gshare", "prompt": "module top_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n", "canonical_solution": "\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n\n\nmodule stimulus_gen\n#(parameter N=7)\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput [N-1:0] predict_pc,\n\t\n\toutput logic train_valid,\n\toutput train_taken,\n\toutput train_mispredicted,\n\toutput [N-1:0] train_history,\n\toutput [N-1:0] train_pc,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\t\n\tlogic [N-1:0] predict_pc_r;\n\tlogic train_taken_r;\n\tlogic train_mispredicted_r;\n\tlogic [N-1:0] train_history_r;\n\tlogic [N-1:0] train_pc_r;\n\t\n\tassign predict_pc = predict_valid ? predict_pc_r : {N{1'bx}};\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\tassign train_mispredicted = train_valid ? train_mispredicted_r : 1'bx;\n\tassign train_history = train_valid ? train_history_r : {N{1'bx}};\n\tassign train_pc = train_valid ? train_pc_r : {N{1'bx}};\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted_r <= 1;\n\t\ttrain_history_r <= 7'h7f;\n\t\ttrain_pc_r <= 7'h4;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\tpredict_valid <= 1;\n\t\tpredict_pc_r <= 4;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Training entries (pc = 0xa, history = 0 and 2)\");\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 0;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_history_r <= 7'h2;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(8) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk);\n\n\t\twavedrom_start(\"History register recovery on misprediction\");\n\t\treset <= 1;\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 1;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h10;\n\t\ttrain_taken_r <= 0;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h20;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(3) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_pc_r, train_pc_r, train_taken_r, train_valid} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted_r <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_taken;\n\t\tint errortime_predict_taken;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic [6:0] predict_pc;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic train_mispredicted;\n\tlogic [6:0] train_history;\n\tlogic [6:0] train_pc;\n\tlogic predict_taken_ref;\n\tlogic predict_taken_dut;\n\tlogic [6:0] predict_history_ref;\n\tlogic [6:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_pc,train_valid,train_taken,train_mispredicted,train_history,train_pc,predict_taken_ref,predict_taken_dut,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_ref),\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_dut),\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_taken) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_taken\", stats1.errors_predict_taken, stats1.errortime_predict_taken);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_taken\");\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_taken_ref, predict_history_ref } === ( { predict_taken_ref, predict_history_ref } ^ { predict_taken_dut, predict_history_dut } ^ { predict_taken_ref, predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_taken_ref !== ( predict_taken_ref ^ predict_taken_dut ^ predict_taken_ref ))\n\t\tbegin if (stats1.errors_predict_taken == 0) stats1.errortime_predict_taken = $time;\n\t\t\tstats1.errors_predict_taken = stats1.errors_predict_taken+1'b1; end\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "gshare", "prompt": "module top_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n", "canonical_solution": "\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput areset, \n\n\tinput predict_valid,\n\tinput [6:0] predict_pc,\n\toutput predict_taken, \n\toutput [6:0] predict_history,\n\n\tinput train_valid,\n\tinput train_taken,\n\tinput train_mispredicted,\n\tinput [6:0] train_history, \n\tinput [6:0] train_pc\n);\n\tparameter n = 7;\n\tlogic [1:0] pht [2**n-1:0];\n\n\tparameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;\n\n\tlogic [n-1:0] predict_history_r;\n\twire [n-1:0] predict_index = predict_history_r ^ predict_pc;\n\twire [n-1:0] train_index = train_history ^ train_pc;\n\t\n\talways@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (integer i=0; i<2**n; i=i+1)\n\t\t\t\tpht[i] = LNT;\n\t\t\tpredict_history_r = 0;\n        end\telse begin\n\t\t\tif (predict_valid)\n\t\t\t\tpredict_history_r <= {predict_history_r, predict_taken};\n\t\t\tif(train_valid) begin\n\t\t\t\tif(pht[train_index] < 3 && train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] + 1;\n\t\t\t\telse if(pht[train_index] > 0 && !train_taken)\n\t\t\t\t\tpht[train_index] <= pht[train_index] - 1;\n\t\t\t\tif (train_mispredicted)\n\t\t\t\t\tpredict_history_r <= {train_history, train_taken};\n\t\t\tend\n\t\tend\n\n\tassign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;\n\tassign predict_history = predict_valid ? predict_history_r : {n{1'bx}};\nendmodule\n\n\nmodule stimulus_gen\n#(parameter N=7)\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput [N-1:0] predict_pc,\n\t\n\toutput logic train_valid,\n\toutput train_taken,\n\toutput train_mispredicted,\n\toutput [N-1:0] train_history,\n\toutput [N-1:0] train_pc,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\t\n\tlogic [N-1:0] predict_pc_r;\n\tlogic train_taken_r;\n\tlogic train_mispredicted_r;\n\tlogic [N-1:0] train_history_r;\n\tlogic [N-1:0] train_pc_r;\n\t\n\tassign predict_pc = predict_valid ? predict_pc_r : {N{1'bx}};\n\tassign train_taken = train_valid ? train_taken_r : 1'bx;\n\tassign train_mispredicted = train_valid ? train_mispredicted_r : 1'bx;\n\tassign train_history = train_valid ? train_history_r : {N{1'bx}};\n\tassign train_pc = train_valid ? train_pc_r : {N{1'bx}};\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted_r <= 1;\n\t\ttrain_history_r <= 7'h7f;\n\t\ttrain_pc_r <= 7'h4;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 1;\n\t\tpredict_valid <= 1;\n\t\tpredict_pc_r <= 4;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Training entries (pc = 0xa, history = 0 and 2)\");\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 0;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_history_r <= 7'h2;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(8) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk);\n\n\t\twavedrom_start(\"History register recovery on misprediction\");\n\t\treset <= 1;\n\t\tpredict_pc_r <= 7'ha;\n\t\tpredict_valid <= 1;\n\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_pc_r <= 7'ha;\n\t\ttrain_taken_r <= 1;\n\t\ttrain_valid <= 0;\n\t\ttrain_mispredicted_r <= 1;\n\t\t\n\t\t@(negedge clk) reset <= 0;\n\t\t@(posedge clk);\n\t\t@(posedge clk) train_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h10;\n\t\ttrain_taken_r <= 0;\n\t\t@(posedge clk) train_valid <= 0;\n\n\t\trepeat(4) @(posedge clk);\n\t\ttrain_history_r <= 7'h0;\n\t\ttrain_taken_r <= 0;\n\t\ttrain_valid <= 1;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t@(posedge clk) train_valid <= 1;\n\t\ttrain_history_r <= 7'h20;\n\t\t@(posedge clk) train_valid <= 0;\n\t\t\n\t\trepeat(3) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\trepeat(1000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_pc_r, train_pc_r, train_taken_r, train_valid} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted_r <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_taken;\n\t\tint errortime_predict_taken;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic [6:0] predict_pc;\n\tlogic train_valid;\n\tlogic train_taken;\n\tlogic train_mispredicted;\n\tlogic [6:0] train_history;\n\tlogic [6:0] train_pc;\n\tlogic predict_taken_ref;\n\tlogic predict_taken_dut;\n\tlogic [6:0] predict_history_ref;\n\tlogic [6:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_pc,train_valid,train_taken,train_mispredicted,train_history,train_pc,predict_taken_ref,predict_taken_dut,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_ref),\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_pc,\n\t\t.train_valid,\n\t\t.train_taken,\n\t\t.train_mispredicted,\n\t\t.train_history,\n\t\t.train_pc,\n\t\t.predict_taken(predict_taken_dut),\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_taken) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_taken\", stats1.errors_predict_taken, stats1.errortime_predict_taken);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_taken\");\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_taken_ref, predict_history_ref } === ( { predict_taken_ref, predict_history_ref } ^ { predict_taken_dut, predict_history_dut } ^ { predict_taken_ref, predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_taken_ref !== ( predict_taken_ref ^ predict_taken_dut ^ predict_taken_ref ))\n\t\tbegin if (stats1.errors_predict_taken == 0) stats1.errortime_predict_taken = $time;\n\t\t\tstats1.errors_predict_taken = stats1.errors_predict_taken+1'b1; end\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "hadd", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n", "canonical_solution": "\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{a,b} <= $random;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sum_ref,sum_dut,cout_ref,cout_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_ref),\n\t\t.cout(cout_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_dut),\n\t\t.cout(cout_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref, cout_ref } === ( { sum_ref, cout_ref } ^ { sum_dut, cout_dut } ^ { sum_ref, cout_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "hadd", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n", "canonical_solution": "\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\toutput sum,\n\toutput cout\n);\n\n\tassign {cout, sum} = a+b;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{a,b} <= $random;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\t\tint errors_cout;\n\t\tint errortime_cout;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sum_ref;\n\tlogic sum_dut;\n\tlogic cout_ref;\n\tlogic cout_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sum_ref,sum_dut,cout_ref,cout_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_ref),\n\t\t.cout(cout_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sum(sum_dut),\n\t\t.cout(cout_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\t\tif (stats1.errors_cout) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"cout\", stats1.errors_cout, stats1.errortime_cout);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"cout\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref, cout_ref } === ( { sum_ref, cout_ref } ^ { sum_dut, cout_dut } ^ { sum_ref, cout_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\t\tif (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))\n\t\tbegin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;\n\t\t\tstats1.errors_cout = stats1.errors_cout+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "history_shift", "prompt": "module top_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n", "canonical_solution": "    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n\n\n\nmodule stimulus_gen\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput predict_taken,\n\t\n\toutput logic train_mispredicted,\n\toutput train_taken,\n\toutput [31:0] train_history,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic predict_taken_r;\n\tassign predict_taken = predict_valid ? predict_taken_r : 1'bx;\n\t\n\tlogic train_taken_r;\n\tlogic [31:0] train_history_r;\n\tassign train_taken = train_mispredicted ? train_taken_r : 1'bx;\n\tassign train_history = train_mispredicted ? train_history_r : 32'hx;\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_taken_r <= 1;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 0;\n\t\ttrain_history_r <= 32'h5;\n\t\ttrain_taken_r <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Predictions: Shift in\");\n\t\trepeat(2) @(posedge clk) {predict_valid, predict_taken_r} <= {$urandom};\n\t\treset <= 0;\n\t\tpredict_valid <= 1;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 0;\n\t\trepeat(3) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 1;\n\t\t@(posedge clk) train_mispredicted <= 0;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\twavedrom_stop();\n\n\t\trepeat(2000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_taken_r, train_taken_r} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic predict_taken;\n\tlogic train_mispredicted;\n\tlogic train_taken;\n\tlogic [31:0] train_history;\n\tlogic [31:0] predict_history_ref;\n\tlogic [31:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_taken,train_mispredicted,train_taken,train_history,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_history_ref } === ( { predict_history_ref } ^ { predict_history_dut } ^ { predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "history_shift", "prompt": "module top_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n", "canonical_solution": "    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module\n(\n    input clk,\n    input areset,\n    input predict_valid,\n    input predict_taken,\n    output logic [31:0] predict_history,\n    \n    input train_mispredicted,\n    input train_taken,\n    input [31:0] train_history\n);\n    always@(posedge clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tpredict_history = 0;\n        end\telse begin\n\t\t\tif (train_mispredicted)\n\t\t\t\tpredict_history <= {train_history, train_taken};\n\t\t\telse if (predict_valid)\n\t\t\t\tpredict_history <= {predict_history, predict_taken};\n\t\tend\nendmodule\n\n\n\nmodule stimulus_gen\n(\n\tinput clk,\n\toutput logic areset,\n\t\n\toutput logic predict_valid,\n\toutput predict_taken,\n\t\n\toutput logic train_mispredicted,\n\toutput train_taken,\n\toutput [31:0] train_history,\n\n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\treg reset;\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\t\n\tassign areset = reset;\n\tlogic predict_taken_r;\n\tassign predict_taken = predict_valid ? predict_taken_r : 1'bx;\n\t\n\tlogic train_taken_r;\n\tlogic [31:0] train_history_r;\n\tassign train_taken = train_mispredicted ? train_taken_r : 1'bx;\n\tassign train_history = train_mispredicted ? train_history_r : 32'hx;\n\t\n\t\n\tinitial begin\n\t\t@(posedge clk) reset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tpredict_taken_r <= 1;\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 0;\n\t\ttrain_history_r <= 32'h5;\n\t\ttrain_taken_r <= 1;\n\t\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\t\treset_test(1); // Test for asynchronous reset\n\t\twavedrom_stop();\n\t\t@(posedge clk) reset <= 1;\n\t\tpredict_valid <= 0;\n\n\t\twavedrom_start(\"Predictions: Shift in\");\n\t\trepeat(2) @(posedge clk) {predict_valid, predict_taken_r} <= {$urandom};\n\t\treset <= 0;\n\t\tpredict_valid <= 1;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 0;\n\t\trepeat(3) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\tpredict_valid <= 1;\n\t\ttrain_mispredicted <= 1;\n\t\t@(posedge clk) train_mispredicted <= 0;\n\t\trepeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};\n\t\twavedrom_stop();\n\n\t\trepeat(2000) @(posedge clk,negedge clk) begin\n\t\t\t{predict_valid, predict_taken_r, train_taken_r} <= {$urandom};\n\t\t\ttrain_history_r <= $urandom;\n\t\t\ttrain_mispredicted <= !($urandom_range(0,31));\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_predict_history;\n\t\tint errortime_predict_history;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic predict_valid;\n\tlogic predict_taken;\n\tlogic train_mispredicted;\n\tlogic train_taken;\n\tlogic [31:0] train_history;\n\tlogic [31:0] predict_history_ref;\n\tlogic [31:0] predict_history_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_taken,train_mispredicted,train_taken,train_history,predict_history_ref,predict_history_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.predict_valid,\n\t\t.predict_taken,\n\t\t.train_mispredicted,\n\t\t.train_taken,\n\t\t.train_history,\n\t\t.predict_history(predict_history_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_predict_history) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"predict_history\", stats1.errors_predict_history, stats1.errortime_predict_history);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"predict_history\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { predict_history_ref } === ( { predict_history_ref } ^ { predict_history_dut } ^ { predict_history_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))\n\t\tbegin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;\n\t\t\tstats1.errors_predict_history = stats1.errors_predict_history+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap2", "prompt": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out\n);\n", "canonical_solution": "\t\n\tassign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out\n);\n\t\n\tassign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap3", "prompt": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n", "canonical_solution": "\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 0;\n            4'h3: out = 1;\n            4'h2: out = 1;\n            4'h4: out = 1'bx;\n            4'h5: out = 0;\n            4'h7: out = 0;\n            4'h6: out = 0;\n            4'hc: out = 1;\n            4'hd: out = 1'bx;\n            4'hf: out = 1;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 1'bx;\n            4'hb: out = 1;\n            4'ha: out = 1;\n        endcase\n    end\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 0;\n            4'h3: out = 1;\n            4'h2: out = 1;\n            4'h4: out = 1'bx;\n            4'h5: out = 0;\n            4'h7: out = 0;\n            4'h6: out = 0;\n            4'hc: out = 1;\n            4'hd: out = 1'bx;\n            4'hf: out = 1;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 1'bx;\n            4'hb: out = 1;\n            4'ha: out = 1;\n        endcase\n    end\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "kmap4", "prompt": "module top_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n", "canonical_solution": "\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 1;\n            4'h3: out = 0;\n            4'h2: out = 1;\n            4'h4: out = 1;\n            4'h5: out = 0;\n            4'h7: out = 1;\n            4'h6: out = 0;\n            4'hc: out = 0;\n            4'hd: out = 1;\n            4'hf: out = 0;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 0;\n            4'hb: out = 1;\n            4'ha: out = 0;\n        endcase\n    end\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a, \n\tinput b,\n\tinput c,\n\tinput d,\n\toutput reg out\n);\n\t\n    always @(*) begin\n        case({a,b,c,d})\n            4'h0: out = 0;\n            4'h1: out = 1;\n            4'h3: out = 0;\n            4'h2: out = 1;\n            4'h4: out = 1;\n            4'h5: out = 0;\n            4'h7: out = 1;\n            4'h6: out = 0;\n            4'hc: out = 0;\n            4'hd: out = 1;\n            4'hf: out = 0;\n            4'he: out = 1;\n            4'h8: out = 1;\n            4'h9: out = 0;\n            4'hb: out = 1;\n            4'ha: out = 0;\n        endcase\n    end\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b, c, d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b,c,d} <= 4'b0;\n\t\twavedrom_start();\n\t\trepeat(16) @(posedge clk)\n\t\t\t{a,b,c,d} <= count++;\t\t\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= $urandom;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings1", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n", "canonical_solution": "\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_right, bump_left} <= 3'h3;\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\treset_test(1);\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref } === ( { walk_left_ref, walk_right_ref } ^ { walk_left_dut, walk_right_dut } ^ { walk_left_ref, walk_right_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings1", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n", "canonical_solution": "\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\toutput walk_left,\n\toutput walk_right\n);\n\tparameter WL=0, WR=1;\n\treg state;\n\treg next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = bump_left ? WR : WL;\n\t\t\tWR: next = bump_right ? WL: WR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_right, bump_left} <= 3'h3;\n\t\twavedrom_start(\"Asynchronous reset\");\n\t\treset_test(1);\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk);\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref } === ( { walk_left_ref, walk_right_ref } ^ { walk_left_dut, walk_right_dut } ^ { walk_left_ref, walk_right_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings2", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground} <= 3'h1;\n\t\treset_test(1);\n\t\t{bump_right, bump_left} <= 3'h0;\n\t\twavedrom_start(\"Falling\");\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 3;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\t\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings2", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3;\n\treg [1:0] state;\n\treg [1:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: next = ground ? (bump_left ? WR : WL) : FALLL;\n\t\t\tWR: next = ground ? (bump_right ? WL: WR) : FALLR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground} <= 3'h1;\n\t\treset_test(1);\n\t\t{bump_right, bump_left} <= 3'h0;\n\t\twavedrom_start(\"Falling\");\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 3;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_right, bump_left, ground} <= 1;\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\t\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings3", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\twire [0:13][3:0] d = {\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'ha,\n\t\t4'h2,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2\n\t};\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground, dig} <= 4'h2;\n\t\treset_test(1);\n\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Digging\");\n\t\tfor (int i=0;i<14;i++)\n\t\t\t@(posedge clk) {bump_left, bump_right, ground, dig} <= d[i];\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings3", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? WL : FALLL;\n\t\t\tFALLR: next = ground ? WR : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\twire [0:13][3:0] d = {\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'ha,\n\t\t4'h2,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h0,\n\t\t4'h3,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2,\n\t\t4'h2\n\t};\n\t\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t{bump_left, bump_right, ground, dig} <= 4'h2;\n\t\treset_test(1);\n\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Digging\");\n\t\tfor (int i=0;i<14;i++)\n\t\t\t@(posedge clk) {bump_left, bump_right, ground, dig} <= d[i];\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings4", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 10;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(4) @(posedge clk);\n\t\t\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(20) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Survive\n\t\trepeat(1) @(posedge clk);\n\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling left\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\tbump_left <= 1;\n\t\trepeat(5) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling right\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\twavedrom_start(\"Splat?\");\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(24) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (24-cycles)\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(35) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 5-bit non-saturating counter)\n\t\trepeat(2) @(posedge clk);\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\treset <= 0;\t\t// Resurrect.\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(67) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 6-bit non-saturating counter)\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lemmings4", "prompt": "module top_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n", "canonical_solution": "\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput areset,\n\tinput bump_left,\n\tinput bump_right,\n\tinput ground,\n\tinput dig,\n\toutput walk_left,\n\toutput walk_right,\n\toutput aaah,\n\toutput digging\n);\n\tparameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;\n\treg [2:0] state;\n\treg [2:0] next;\n    \n    reg [4:0] fall_counter;\n    \n    always_comb begin\n\t\tcase (state)\n\t\t\tWL: if (!ground) next = FALLL;\n\t\t\t\telse if (dig) next = DIGL;\n\t\t\t\telse if (bump_left) next = WR;\n\t\t\t\telse next = WL;\n\t\t\tWR: \n\t\t\t\tif (!ground) next = FALLR;\n\t\t\t\telse if (dig) next = DIGR;\n\t\t\t\telse if (bump_right) next = WL;\n\t\t\t\telse next = WR;\n\t\t\tFALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;\n\t\t\tFALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;\n\t\t\tDIGL: next = ground ? DIGL : FALLL;\n\t\t\tDIGR: next = ground ? DIGR : FALLR;\n\t\t\tDEAD: next = DEAD;\n\t\tendcase\n    end\n    \n    always @(posedge clk, posedge areset) begin\n\t\tif (areset) state <= WL;\n        else state <= next;\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (state == FALLL || state == FALLR) begin\n\t\t\tif (fall_counter < 20)\n\t\t\t\tfall_counter <= fall_counter + 1'b1;\n\t\tend\n\t\telse\n\t\t\tfall_counter <= 0;\n\tend\n\t\t\n\tassign walk_left = (state==WL);\n\tassign walk_right = (state==WR);\n\tassign aaah = (state == FALLL) || (state == FALLR);\n\tassign digging = (state == DIGL) || (state == DIGR);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic areset,\n\toutput logic bump_left,\n\toutput logic bump_right,\n\toutput logic dig,\n\toutput logic ground,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\treg reset;\n\tassign areset = reset;\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\treset <= 1'b1;\n\t\t@(posedge clk);\n\t\treset <= 0;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(2) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 10;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 3;\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\n\t\trepeat(4) @(posedge clk);\n\t\t\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(20) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Survive\n\t\trepeat(1) @(posedge clk);\n\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling left\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\tbump_left <= 1;\n\t\trepeat(5) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(21) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat after falling right\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\twavedrom_start(\"Splat?\");\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(24) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (24-cycles)\n\t\trepeat(2) @(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\treset <= 1;\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(35) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 5-bit non-saturating counter)\n\t\trepeat(2) @(posedge clk);\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\t\t\n\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk);\n\t\treset <= 0;\t\t// Resurrect.\n\t\t@(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 0;\t\t// Fall\n\t\trepeat(67) @(posedge clk);\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Splat? (Test for 6-bit non-saturating counter)\n\t\trepeat(20) @(posedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\t// See if it's handled correctly.\n\t\t\tground <= |($random & 7);\n\t\tend\n\t\t\n\t\treset <= 1;\n\t\t{bump_left, bump_right, ground, dig} <= 2;\t\t// Normal\n\t\t@(posedge clk)\n\t\treset <= 0;\t\t// Resurrect.\n\t\t\n\t\t\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\t{dig, bump_right, bump_left} <= $random & $random;\n\t\t\tground <= |($random & 7);\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_walk_left;\n\t\tint errortime_walk_left;\n\t\tint errors_walk_right;\n\t\tint errortime_walk_right;\n\t\tint errors_aaah;\n\t\tint errortime_aaah;\n\t\tint errors_digging;\n\t\tint errortime_digging;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic areset;\n\tlogic bump_left;\n\tlogic bump_right;\n\tlogic ground;\n\tlogic dig;\n\tlogic walk_left_ref;\n\tlogic walk_left_dut;\n\tlogic walk_right_ref;\n\tlogic walk_right_dut;\n\tlogic aaah_ref;\n\tlogic aaah_dut;\n\tlogic digging_ref;\n\tlogic digging_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig );\n\treference_module good1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_ref),\n\t\t.walk_right(walk_right_ref),\n\t\t.aaah(aaah_ref),\n\t\t.digging(digging_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.areset,\n\t\t.bump_left,\n\t\t.bump_right,\n\t\t.ground,\n\t\t.dig,\n\t\t.walk_left(walk_left_dut),\n\t\t.walk_right(walk_right_dut),\n\t\t.aaah(aaah_dut),\n\t\t.digging(digging_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_walk_left) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_left\", stats1.errors_walk_left, stats1.errortime_walk_left);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_left\");\n\t\tif (stats1.errors_walk_right) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"walk_right\", stats1.errors_walk_right, stats1.errortime_walk_right);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"walk_right\");\n\t\tif (stats1.errors_aaah) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aaah\", stats1.errors_aaah, stats1.errortime_aaah);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aaah\");\n\t\tif (stats1.errors_digging) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"digging\", stats1.errors_digging, stats1.errortime_digging);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"digging\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))\n\t\tbegin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;\n\t\t\tstats1.errors_walk_left = stats1.errors_walk_left+1'b1; end\n\t\tif (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))\n\t\tbegin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;\n\t\t\tstats1.errors_walk_right = stats1.errors_walk_right+1'b1; end\n\t\tif (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))\n\t\tbegin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;\n\t\t\tstats1.errors_aaah = stats1.errors_aaah+1'b1; end\n\t\tif (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))\n\t\tbegin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;\n\t\t\tstats1.errors_digging = stats1.errors_digging+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr32", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n", "canonical_solution": "\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(200000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] q_ref;\n\tlogic [31:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr32", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n", "canonical_solution": "\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [31:0] q);\n\t\n\tlogic [31:0] q_next;\n\talways@(q) begin\n\t\tq_next = q[31:1];\n\t\tq_next[31] = q[0];\n\t\tq_next[21] ^= q[0];\n\t\tq_next[1] ^= q[0];\n\t\tq_next[0] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 32'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(200000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [31:0] q_ref;\n\tlogic [31:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr5", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n", "canonical_solution": "\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\treset_test();\n\t\t\trepeat(8) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(2000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [4:0] q_ref;\n\tlogic [4:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "lfsr5", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n", "canonical_solution": "\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [4:0] q);\n\t\n\tlogic [4:0] q_next;\n\talways @(q) begin\n\t\tq_next = q[4:1];\n\t\tq_next[4] = q[0];\n\t\tq_next[2] ^= q[0];\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset)\n\t\t\tq <= 5'h1;\n\t\telse\n\t\t\tq <= q_next;\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\t\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\treset_test();\n\t\t\trepeat(8) @(posedge clk);\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\t\t@(posedge clk) reset <= 1'b0;\n\t\trepeat(2000) @(posedge clk);\n\t\treset <= 1'b1;\n\t\trepeat(5) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [4:0] q_ref;\n\tlogic [4:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q3", "prompt": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q3", "prompt": "module top_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n", "canonical_solution": "\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:1] x,\n\toutput logic f\n);\n\n\talways_comb begin\n\t\tcase (x) \n\t\t\t4'h0: f = 1'bx;\n\t\t\t4'h1: f = 1'bx;\n\t\t\t4'h2: f = 0;\n\t\t\t4'h3: f = 1'bx;\n\t\t\t4'h4: f = 1;\n\t\t\t4'h5: f = 1'bx;\n\t\t\t4'h6: f = 1;\n\t\t\t4'h7: f = 0;\n\t\t\t4'h8: f = 0;\n\t\t\t4'h9: f = 0;\n\t\t\t4'ha: f = 1'bx;\n\t\t\t4'hb: f = 1;\n\t\t\t4'hc: f = 1;\n\t\t\t4'hd: f = 1'bx;\n\t\t\t4'he: f = 1;\n\t\t\t4'hf: f = 1'bx;\n\t\tendcase\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:1] x\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tx <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:1] x;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x );\n\treference_module good1 (\n\t\t.x,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4b", "prompt": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput ar,\n\toutput logic q\n);\n", "canonical_solution": "\n\talways@(posedge clk or posedge ar) begin\n\t\tif (ar)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput d,\n\tinput ar,\n\toutput logic q\n);\n\n\talways@(posedge clk or posedge ar) begin\n\t\tif (ar)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic d, ar\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{d,ar} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic ar;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,ar,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.ar );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.ar,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.ar,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4c", "prompt": "module top_module (\n\tinput clk,\n\tinput d,\n\tinput r,\n\toutput logic q\n);\n", "canonical_solution": "\n\talways@(posedge clk) begin\n\t\tif (r)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput d,\n\tinput r,\n\toutput logic q\n);\n\n\talways@(posedge clk) begin\n\t\tif (r)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= d;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic d, r\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{d,r} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic r;\n\tlogic q_ref;\n\tlogic q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,r,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.r );\n\treference_module good1 (\n\t\t.clk,\n\t\t.d,\n\t\t.r,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.d,\n\t\t.r,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4d", "prompt": "module top_module (\n\tinput clk,\n\tinput in,\n\toutput logic out\n);\n", "canonical_solution": "\n\tinitial\n\t\tout = 0;\n\t\t\n\talways@(posedge clk) begin\n\t\tout <= in ^ out;\n\tend\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput in,\n\toutput logic out\n);\n\n\tinitial\n\t\tout = 0;\n\t\t\n\talways@(posedge clk) begin\n\t\tout <= in ^ out;\n\tend\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4f", "prompt": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n", "canonical_solution": "\n\tassign out = in1 & ~in2;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = in1 & ~in2;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4f", "prompt": "module top_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n", "canonical_solution": "\n\tassign out = in1 & ~in2;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\toutput logic out\n);\n\n\tassign out = in1 & ~in2;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4g", "prompt": "module top_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n", "canonical_solution": "\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2, in3\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2, in3} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic in3;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,in3,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2,\n\t\t.in3 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4g", "prompt": "module top_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n", "canonical_solution": "\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput in1,\n\tinput in2,\n\tinput in3,\n\toutput logic out\n);\n\n\tassign out = (~(in1 ^ in2)) ^ in3;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in1, in2, in3\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{in1, in2, in3} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in1;\n\tlogic in2;\n\tlogic in3;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,in3,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in1,\n\t\t.in2,\n\t\t.in3 );\n\treference_module good1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in1,\n\t\t.in2,\n\t\t.in3,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4i", "prompt": "module top_module(\n\toutput out);\n", "canonical_solution": "\t\n\tassign out = 1'b0;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput out);\n\t\n\tassign out = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4i", "prompt": "module top_module(\n\toutput out);\n", "canonical_solution": "\t\n\tassign out = 1'b0;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput out);\n\t\n\tassign out = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4j", "prompt": "module top_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n", "canonical_solution": "\n\tassign sum = x+y;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n\n\tassign sum = x+y;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] x,y\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] x;\n\tlogic [3:0] y;\n\tlogic [4:0] sum_ref;\n\tlogic [4:0] sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref } === ( { sum_ref } ^ { sum_dut } ^ { sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4j", "prompt": "module top_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n", "canonical_solution": "\n\tassign sum = x+y;\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [3:0] x,\n\tinput [3:0] y,\n\toutput [4:0] sum\n);\n\n\tassign sum = x+y;\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [3:0] x,y\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{x,y} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_sum;\n\t\tint errortime_sum;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:0] x;\n\tlogic [3:0] y;\n\tlogic [4:0] sum_ref;\n\tlogic [4:0] sum_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,sum_ref,sum_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.sum(sum_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_sum) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"sum\", stats1.errors_sum, stats1.errortime_sum);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"sum\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { sum_ref } === ( { sum_ref } ^ { sum_dut } ^ { sum_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))\n\t\tbegin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;\n\t\t\tstats1.errors_sum = stats1.errors_sum+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4k", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n", "canonical_solution": "\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in, resetn\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q4k", "prompt": "module top_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n", "canonical_solution": "\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput resetn,\n\tinput in,\n\toutput out\n);\n\n\treg [3:0] sr;\n\talways @(posedge clk) begin\n\t\tif (~resetn)\n\t\t\tsr <= '0;\n\t\telse \n\t\t\tsr <= {sr[2:0], in};\n\tend\n\t\n\tassign out = sr[3];\n\t\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic in, resetn\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\tin <= $random;\n\t\t\tresetn <= ($random & 7) != 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic resetn;\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.resetn,\n\t\t.in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.resetn,\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\t\treset <= ($random & 15) == 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6", "prompt": "module top_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n", "canonical_solution": "\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput clk,\n\tinput reset,\n\tinput w,\n\toutput z\n);\n\tparameter A=0, B=1, C=2, D=3, E=4, F=5;\n\treg [2:0] state, next;\n\t\n\talways @(posedge clk)\n\t\tif (reset)\n\t\t\tstate <= A;\n\t\telse \n\t\t\tstate <= next;\n\t\t\t\n\t\t\t\n\talways_comb begin\n\t\tcase(state)\n\t\t\tA: next = w ? A : B;\n\t\t\tB: next = w ? D : C;\n\t\t\tC: next = w ? D : E;\n\t\t\tD: next = w ? A : F;\n\t\t\tE: next = w ? D : E;\n\t\t\tF: next = w ? D : C;\n\t\t\tdefault: next = 'x;\n\t\tendcase\n\tend\n\t\n\tassign z = (state == E || state == F);\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic reset,\n\toutput logic w\n);\n\n\tinitial begin\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\tw <= $random;\n\t\t\treset <= ($random & 15) == 0;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic w;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.w );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.w,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6b", "prompt": "module top_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n", "canonical_solution": "\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [3:1] y,\n\toutput reg w\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{y,w} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref } === ( { Y2_ref } ^ { Y2_dut } ^ { Y2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6b", "prompt": "module top_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n", "canonical_solution": "\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [3:1] y,\n\tinput w,\n\toutput reg Y2);\n\t\n\talways_comb begin\n\t\tcase ({y, w})\n\t\t\t4'h0: Y2 = 1'b0;\n\t\t\t4'h1: Y2 = 1'b0;\n\t\t\t4'h2: Y2 = 1'b1;\n\t\t\t4'h3: Y2 = 1'b1;\n\t\t\t4'h4: Y2 = 1'b0;\n\t\t\t4'h5: Y2 = 1'b1;\n\t\t\t4'h6: Y2 = 1'b0;\n\t\t\t4'h7: Y2 = 1'b0;\n\t\t\t4'h8: Y2 = 1'b0;\n\t\t\t4'h9: Y2 = 1'b1;\n\t\t\t4'ha: Y2 = 1'b1;\n\t\t\t4'hb: Y2 = 1'b1;\n\t\t\tdefault: Y2 = 1'bx;\n\t\tendcase\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [3:1] y,\n\toutput reg w\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{y,w} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [3:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref } === ( { Y2_ref } ^ { Y2_dut } ^ { Y2_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6c", "prompt": "module top_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n", "canonical_solution": "\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[6:1] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );\t\n\t\t\t// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.\n\n\t\t\ty[6:1] <= temp[6:1];\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\t\tint errors_Y4;\n\t\tint errortime_Y4;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [6:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\tlogic Y4_ref;\n\tlogic Y4_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut,Y4_ref,Y4_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref),\n\t\t.Y4(Y4_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut),\n\t\t.Y4(Y4_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\t\tif (stats1.errors_Y4) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y4\", stats1.errors_Y4, stats1.errortime_Y4);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y4\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref, Y4_ref } === ( { Y2_ref, Y4_ref } ^ { Y2_dut, Y4_dut } ^ { Y2_ref, Y4_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\t\tif (Y4_ref !== ( Y4_ref ^ Y4_dut ^ Y4_ref ))\n\t\tbegin if (stats1.errors_Y4 == 0) stats1.errortime_Y4 = $time;\n\t\t\tstats1.errors_Y4 = stats1.errors_Y4+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "m2014_q6c", "prompt": "module top_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n", "canonical_solution": "\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [6:1] y,\n\tinput w,\n\toutput Y2,\n\toutput Y4\n);\n\tassign Y2 = y[1]&~w;\n\tassign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;\n\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic[6:1] y,\n\toutput logic w,\n\tinput tb_match\n);\n\n\tint errored1 = 0;\n\tint onehot_error = 0;\n\tint temp;\n\t\n\tinitial begin\n\t\t// Test the one-hot cases first.\n\t\trepeat(200) @(posedge clk, negedge clk) begin\n\t\t\ty <= 1<< ($unsigned($random) % 6);\n\t\t\tw <= $random;\n\t\t\tif (!tb_match) onehot_error++;\n\t\tend\n\t\t\t\n\t\t\t\n\t\t// Random.\n\t\terrored1 = 0;\n\t\trepeat(400) @(posedge clk, negedge clk) begin\n\t\t\tdo \n\t\t\t\ttemp = $random;\n\t\t\twhile ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );\t\n\t\t\t// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.\n\n\t\t\ty[6:1] <= temp[6:1];\n\t\t\tw <= $random;\n\t\t\tif (!tb_match)\n\t\t\t\terrored1++;\n\t\tend\n\t\tif (!onehot_error && errored1) \n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.\");\n\n\t\tif (!onehot_error && errored1)\n\t\t\t$display(\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Y2;\n\t\tint errortime_Y2;\n\t\tint errors_Y4;\n\t\tint errortime_Y4;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [6:1] y;\n\tlogic w;\n\tlogic Y2_ref;\n\tlogic Y2_dut;\n\tlogic Y4_ref;\n\tlogic Y4_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut,Y4_ref,Y4_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.y,\n\t\t.w );\n\treference_module good1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_ref),\n\t\t.Y4(Y4_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.y,\n\t\t.w,\n\t\t.Y2(Y2_dut),\n\t\t.Y4(Y4_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Y2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y2\", stats1.errors_Y2, stats1.errortime_Y2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y2\");\n\t\tif (stats1.errors_Y4) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Y4\", stats1.errors_Y4, stats1.errortime_Y4);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Y4\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Y2_ref, Y4_ref } === ( { Y2_ref, Y4_ref } ^ { Y2_dut, Y4_dut } ^ { Y2_ref, Y4_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))\n\t\tbegin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;\n\t\t\tstats1.errors_Y2 = stats1.errors_Y2+1'b1; end\n\t\tif (Y4_ref !== ( Y4_ref ^ Y4_dut ^ Y4_ref ))\n\t\tbegin if (stats1.errors_Y4 == 0) stats1.errortime_Y4 = $time;\n\t\t\tstats1.errors_Y4 = stats1.errors_Y4+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_eq2", "prompt": "module top_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n", "canonical_solution": "\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 1k. 2-bit equality comparator.\n*/\nmodule reference_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1:0] A,\n\toutput logic [1:0] B\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{A, B} <= $random % 16;\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1:0] A;\n\tlogic [1:0] B;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,A,B,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.A,\n\t\t.B );\n\treference_module good1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_eq2", "prompt": "module top_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n", "canonical_solution": "\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 1k. 2-bit equality comparator.\n*/\nmodule reference_module(\n\tinput [1:0] A,\n\tinput [1:0] B,\n\toutput z);\n\n\tassign z = A[1:0]==B[1:0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1:0] A,\n\toutput logic [1:0] B\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{A, B} <= $random % 16;\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1:0] A;\n\tlogic [1:0] B;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,A,B,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.A,\n\t\t.B );\n\treference_module good1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.A,\n\t\t.B,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_muxdff", "prompt": "module top_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n", "canonical_solution": "\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.\n*/\nmodule reference_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic L,\n\toutput logic r_in,\n\toutput logic q_in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{L, r_in, q_in} <= $random % 8;\n\t\n\tinitial begin\n\t\trepeat(100) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic L;\n\tlogic q_in;\n\tlogic r_in;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,L,q_in,r_in,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_muxdff", "prompt": "module top_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n", "canonical_solution": "\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n/*\n\tMidterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.\n*/\nmodule reference_module(\n\tinput clk,\n\tinput L,\n\tinput q_in,\n\tinput r_in,\n\toutput reg Q);\n\n\tinitial Q=0;\n\talways @(posedge clk)\n\t\tQ <= L ? r_in : q_in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic L,\n\toutput logic r_in,\n\toutput logic q_in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{L, r_in, q_in} <= $random % 8;\n\t\n\tinitial begin\n\t\trepeat(100) @(posedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_Q;\n\t\tint errortime_Q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic L;\n\tlogic q_in;\n\tlogic r_in;\n\tlogic Q_ref;\n\tlogic Q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,L,q_in,r_in,Q_ref,Q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in );\n\treference_module good1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.L,\n\t\t.q_in,\n\t\t.r_in,\n\t\t.Q(Q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_Q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Q\", stats1.errors_Q, stats1.errortime_Q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))\n\t\tbegin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;\n\t\t\tstats1.errors_Q = stats1.errors_Q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4", "prompt": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "canonical_solution": "\n\tassign z = x|~y;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = x|~y;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{x, y} <= $random % 4;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4", "prompt": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "canonical_solution": "\n\tassign z = x|~y;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = x|~y;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y\n);\n\n\talways @(posedge clk, negedge clk)\n\t\t{x, y} <= $random % 4;\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4b", "prompt": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "canonical_solution": "\n\tassign z = ~(x^y);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = ~(x^y);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x,y} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {y,x} <= 0;\n\t\t\t@(posedge clk) {y,x} <= 1;\n\t\t\t@(posedge clk) {y,x} <= 2;\n\t\t\t@(posedge clk) {y,x} <= 3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{x, y} <= $random % 4;\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mt2015_q4b", "prompt": "module top_module(\n\tinput x,\n\tinput y,\n\toutput z);\n", "canonical_solution": "\n\tassign z = ~(x^y);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput x,\n\tinput y,\n\toutput z);\n\n\tassign z = ~(x^y);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic x,\n\toutput logic y,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x,y} <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) {y,x} <= 0;\n\t\t\t@(posedge clk) {y,x} <= 1;\n\t\t\t@(posedge clk) {y,x} <= 2;\n\t\t\t@(posedge clk) {y,x} <= 3;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{x, y} <= $random % 4;\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x;\n\tlogic y;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x,\n\t\t.y );\n\treference_module good1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x,\n\t\t.y,\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1", "prompt": "module top_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n", "canonical_solution": "\n\tassign out = in[sel];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n\n\tassign out = in[sel];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [255:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<8; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [255:0] in;\n\tlogic [7:0] sel;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1", "prompt": "module top_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n", "canonical_solution": "\n\tassign out = in[sel];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [255:0] in,\n\tinput [7:0] sel,\n\toutput  out\n);\n\n\tassign out = in[sel];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [255:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<8; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [255:0] in;\n\tlogic [7:0] sel;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1v", "prompt": "module top_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n", "canonical_solution": "\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1023:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<32; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1023:0] in;\n\tlogic [7:0] sel;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux256to1v", "prompt": "module top_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n", "canonical_solution": "\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [1023:0] in,\n\tinput [7:0] sel,\n\toutput [3:0] out\n);\n\n\tassign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [1023:0] in,\n\toutput logic [7:0] sel\n);\n\n\talways @(posedge clk, negedge clk) begin\n\t\tfor (int i=0;i<32; i++)\n\t\t\tin[i*32+:32] <= $random;\n\t\tsel <= $random;\n\tend\n\t\n\tinitial begin\n\t\trepeat(1000) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [1023:0] in;\n\tlogic [7:0] sel;\n\tlogic [3:0] out_ref;\n\tlogic [3:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in,\n\t\t.sel );\n\treference_module good1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux2to1", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput sel,\n\toutput out\n);\n", "canonical_solution": "\n\tassign out = sel ? b : a;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput sel,\n\toutput out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a,b,sel,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a, b, sel} <= 3'b000;\n\t\t@(negedge clk) wavedrom_start(\"<b>Sel</b> chooses between <b>a</b> and <b>b</b>\");\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b000;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b100;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b110;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b111;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b011;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b001;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b100;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b101;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b110;\n\t\t\t@(posedge clk) {a, b, sel} <= 3'b111;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic sel;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "mux2to1v", "prompt": "module top_module (\n\tinput [99:0] a,\n\tinput [99:0] b,\n\tinput sel,\n\toutput [99:0] out\n);\n", "canonical_solution": "\n\tassign out = sel ? b : a;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] a,\n\tinput [99:0] b,\n\tinput sel,\n\toutput [99:0] out\n);\n\n\tassign out = sel ? b : a;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [99:0] a,b,\n\toutput logic sel,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\ta <= 'hdeadbeef;\n\t\tb <= 'h5eaf00d;\n\t\tsel <= 0;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Beef or seafood?\");\n\t\t\trepeat(6) @(posedge clk) sel <= ~sel;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,sel} <= {$random, $random, $random, $random, $random, $random, $random};\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] a;\n\tlogic [99:0] b;\n\tlogic sel;\n\tlogic [99:0] out_ref;\n\tlogic [99:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.sel );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.sel,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "norgate", "prompt": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "canonical_solution": "\t\n\tassign out = ~(a | b);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a | b);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"NOR gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "norgate", "prompt": "module top_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n", "canonical_solution": "\t\n\tassign out = ~(a | b);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput a, \n\tinput b,\n\toutput out\n);\n\t\n\tassign out = ~(a | b);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{a,b} <= 1'b0;\n\t\twavedrom_start(\"NOR gate\");\n\t\trepeat(10) @(posedge clk)\n\t\t\t{a,b} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "notgate", "prompt": "module top_module(\n\tinput in,\n\toutput out\n);\n", "canonical_solution": "\t\n\tassign out = ~in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput in,\n\toutput out\n);\n\t\n\tassign out = ~in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tin <= 1'b0;\n\t\twavedrom_start(\"Inversion\");\n\t\trepeat(20) @(posedge clk)\n\t\t\tin <= $random;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic in;\n\tlogic out_ref;\n\tlogic out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount255", "prompt": "module top_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n", "canonical_solution": "\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [254:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 255'h0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h7;\n\t\t@(posedge clk, negedge clk) in <= 255'haaaa;\n\t\t@(posedge clk, negedge clk) in <= 255'hf00000;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\twavedrom_stop();\n\t\trepeat (200) @(posedge clk, negedge clk) begin\n\t\t\tin <= {$random, $random, $random, $random, $random, $random, $random, $random};\n\t\tend\n\t\t@(posedge clk);\n\t\tin <= '0;\n\t\t@(posedge clk)\n\t\tin <= '1;\n\t\t@(posedge clk)\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [254:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount255", "prompt": "module top_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n", "canonical_solution": "\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [254:0] in,\n\toutput reg [7:0] out\n);\n\n\talways_comb  begin\n\t\tout = 0;\n\t\tfor (int i=0;i<255;i++)\n\t\t\tout = out + in[i];\n\tend\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [254:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tin <= 255'h0;\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h1;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h3;\n\t\t@(posedge clk, negedge clk) in <= 255'h7;\n\t\t@(posedge clk, negedge clk) in <= 255'haaaa;\n\t\t@(posedge clk, negedge clk) in <= 255'hf00000;\n\t\t@(posedge clk, negedge clk) in <= 255'h0;\n\t\twavedrom_stop();\n\t\trepeat (200) @(posedge clk, negedge clk) begin\n\t\t\tin <= {$random, $random, $random, $random, $random, $random, $random, $random};\n\t\tend\n\t\t@(posedge clk);\n\t\tin <= '0;\n\t\t@(posedge clk)\n\t\tin <= '1;\n\t\t@(posedge clk)\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [254:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount3", "prompt": "module top_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n", "canonical_solution": "\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\tin <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\trepeat(9) @(posedge clk) in <= in + 1'b1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] in;\n\tlogic [1:0] out_ref;\n\tlogic [1:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "popcount3", "prompt": "module top_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n", "canonical_solution": "\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [2:0] in,\n\toutput [1:0] out\n);\n\n\tassign out = in[0]+in[1]+in[2];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [2:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\t\n\tinitial begin\n\t\tin <= 7;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\t\trepeat(9) @(posedge clk) in <= in + 1'b1;\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] in;\n\tlogic [1:0] out_ref;\n\tlogic [1:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "reduction", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput parity\n);\n", "canonical_solution": "\n\tassign parity = ^in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput parity\n);\n\n\tassign parity = ^in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_parity;\n\t\tint errortime_parity;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic parity_ref;\n\tlogic parity_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,parity_ref,parity_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.parity(parity_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.parity(parity_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_parity) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"parity\", stats1.errors_parity, stats1.errortime_parity);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"parity\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { parity_ref } === ( { parity_ref } ^ { parity_dut } ^ { parity_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (parity_ref !== ( parity_ref ^ parity_dut ^ parity_ref ))\n\t\tbegin if (stats1.errors_parity == 0) stats1.errortime_parity = $time;\n\t\t\tstats1.errors_parity = stats1.errors_parity+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_count1k", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset\");\n\t\treset_test();\n\t\trepeat(5) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\treset <= 0;\n\t\t\n\t\trepeat(989) @(negedge clk);\n\t\twavedrom_start(\"Wrap around behaviour\");\n\t\trepeat(14)@(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\n\t\t\n\t\trepeat(2000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 127);\n\t\tend\n\t\treset <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [9:0] q_ref;\n\tlogic [9:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_count1k", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput reg [9:0] q);\n\t\n\talways @(posedge clk)\n\t\tif (reset || q == 999)\n\t\t\tq <= 0;\n\t\telse\n\t\t\tq <= q+1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\twavedrom_start(\"Synchronous reset\");\n\t\treset_test();\n\t\trepeat(5) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\treset <= 0;\n\t\t\n\t\trepeat(989) @(negedge clk);\n\t\twavedrom_start(\"Wrap around behaviour\");\n\t\trepeat(14)@(posedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\n\t\t\n\t\trepeat(2000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 127);\n\t\tend\n\t\treset <= 0;\n\t\trepeat(2000) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic [9:0] q_ref;\n\tlogic [9:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fancytimer", "prompt": "module top_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n", "canonical_solution": "\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n`default_nettype none\nmodule reference_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput wire clk,\n\toutput reg reset,\n\toutput reg data, \n\toutput reg ack,\n\tinput wire tb_match,\n\tinput wire counting_dut\n);\n\tbit failed = 0;\n\tint counting_cycles = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\t\t\n\talways @(posedge clk)\n\t\tif (counting_dut)\n\t\t\tcounting_cycles++;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(2000) @(posedge clk);\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\tif (counting_cycles != 2000)\n\t\t\t$display(\"Hint: The first test case should count for 2000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b0;\n\t\trepeat(14800) @(posedge clk);\n\t\tack <= 1'b0;\n\t\trepeat(400) @(posedge clk);\n\n\t\tif (counting_cycles != 15000)\n\t\t\t$display(\"Hint: The second test case should count for 15000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(1000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\t\trepeat(100000) @(posedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_count;\n\t\tint errortime_count;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic ack;\n\tlogic [3:0] count_ref;\n\tlogic [3:0] count_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,ack,count_ref,count_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_count) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"count\", stats1.errors_count, stats1.errortime_count);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"count\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { count_ref, counting_ref, done_ref } === ( { count_ref, counting_ref, done_ref } ^ { count_dut, counting_dut, done_dut } ^ { count_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (count_ref !== ( count_ref ^ count_dut ^ count_ref ))\n\t\tbegin if (stats1.errors_count == 0) stats1.errortime_count = $time;\n\t\t\tstats1.errors_count = stats1.errors_count+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fancytimer", "prompt": "module top_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n", "canonical_solution": "\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n`default_nettype none\nmodule reference_module(\n\tinput wire clk,\n\tinput wire reset,\n\tinput wire data,\n    output wire [3:0] count,\n    output reg counting,\n    output reg done,\n    input wire ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\treg shift_ena;\n\treg [9:0] fcount;\n\treg [3:0] scount;\n\twire done_counting = (scount == 0) && (fcount == 999);\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\t\t\n\tend\n\t\n\t\n\t// Shift register\n\talways @(posedge clk) begin\n\t\tif (shift_ena)\n\t\t\tscount <= {scount[2:0], data};\n\t\telse if (counting && fcount == 999)\n\t\t\tscount <= scount - 1'b1;\n\tend\n\t\n\t// Fast counter\n\talways @(posedge clk)\n\t\tif (!counting)\n\t\t\tfcount <= 10'h0;\n\t\telse if (fcount == 999)\n\t\t\tfcount <= 10'h0;\n\t\telse\n\t\t\tfcount <= fcount + 1'b1;\n\t\n\tassign count = counting ? scount : 'x;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput wire clk,\n\toutput reg reset,\n\toutput reg data, \n\toutput reg ack,\n\tinput wire tb_match,\n\tinput wire counting_dut\n);\n\tbit failed = 0;\n\tint counting_cycles = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\t\t\n\talways @(posedge clk)\n\t\tif (counting_dut)\n\t\t\tcounting_cycles++;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(2000) @(posedge clk);\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\tif (counting_cycles != 2000)\n\t\t\t$display(\"Hint: The first test case should count for 2000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b1;\n\t\t@(posedge clk);\tdata <= 1'b0;\n\t\trepeat(14800) @(posedge clk);\n\t\tack <= 1'b0;\n\t\trepeat(400) @(posedge clk);\n\n\t\tif (counting_cycles != 15000)\n\t\t\t$display(\"Hint: The second test case should count for 15000 cycles. Your circuit counted %0d\", counting_cycles);\n\t\tcounting_cycles <= 0;\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(1000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\t\trepeat(100000) @(posedge clk) begin\n\t\t\treset <= !($random & 8191);\n\t\t\tdata <= $random;\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_count;\n\t\tint errortime_count;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic ack;\n\tlogic [3:0] count_ref;\n\tlogic [3:0] count_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,ack,count_ref,count_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.ack,\n\t\t.count(count_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_count) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"count\", stats1.errors_count, stats1.errortime_count);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"count\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { count_ref, counting_ref, done_ref } === ( { count_ref, counting_ref, done_ref } ^ { count_dut, counting_dut, done_dut } ^ { count_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (count_ref !== ( count_ref ^ count_dut ^ count_ref ))\n\t\tbegin if (stats1.errors_count == 0) stats1.errortime_count = $time;\n\t\t\tstats1.errors_count = stats1.errors_count+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsm", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n", "canonical_solution": "\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg data, done_counting, ack,\n\tinput tb_match\n);\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tdone_counting <= 1'bx;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdone_counting <= 1'bx;\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(5000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 255);\n\t\t\tdata <= $random;\n\t\t\tdone_counting <= !($random & 31);\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,done_counting,ack,shift_ena_ref,shift_ena_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref, counting_ref, done_ref } === ( { shift_ena_ref, counting_ref, done_ref } ^ { shift_ena_dut, counting_dut, done_dut } ^ { shift_ena_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsm", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n", "canonical_solution": "\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n    output reg shift_ena,\n    output reg counting,\n    input done_counting,\n    output reg done,\n    input ack );\n\n\ttypedef enum logic[3:0] {\n\t\tS, S1, S11, S110, B0, B1, B2, B3, Count, Wait\n\t} States;\n\t\n\tStates state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = States'(data ? S1: S);\n\t\t\tS1: next = States'(data ? S11: S);\n\t\t\tS11: next = States'(data ? S11 : S110);\n\t\t\tS110: next = States'(data ? B0 : S);\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Count;\n\t\t\tCount: next = States'(done_counting ? Wait : Count);\n\t\t\tWait: next = States'(ack ? S : Wait);\n\t\t\tdefault: next = States'(4'bx);\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk) begin\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\tend\n\t\t\n\talways_comb begin\n\t\tshift_ena = 0; counting = 0; done = 0;\n\t\tif (state == B0 || state == B1 || state == B2 || state == B3)\n\t\t\tshift_ena = 1;\n\t\tif (state == Count)\n\t\t\tcounting = 1;\n\t\tif (state == Wait)\n\t\t\tdone = 1;\n\n\t\tif (|state === 1'bx) begin\n\t\t\t{shift_ena, counting, done} = 'x;\n\t\tend\n\t\t\n\tend\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset,\n\toutput reg data, done_counting, ack,\n\tinput tb_match\n);\n\tbit failed = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\n\t\t@(posedge clk);\n\t\tfailed <= 0;\n\t\treset <= 1;\n\t\tdata <= 0;\n\t\tdone_counting <= 1'bx;\n\t\tack <= 1'bx;\n\t\t@(posedge clk) \n\t\t\tdata <= 1;\n\t\t\treset <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk) data <= 0;\n\t\t@(posedge clk) data <= 1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdone_counting <= 1'bx;\n\t\t\tack <= 1'b0;\n\t\trepeat(3) @(posedge clk);\n\t\t\tack <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'b0;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tack <= 1'bx;\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b0;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'b1;\n\t\t@(posedge clk);\n\t\t\tdata <= 1'bx;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b0;\n\t\trepeat(4) @(posedge clk);\n\t\t\tdone_counting <= 1'b1;\n\t\t@(posedge clk);\n\n\t\tif (failed)\n\t\t\t$display(\"Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?\");\n\t\t\n\t\t\n\t\n\t\trepeat(5000) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 255);\n\t\t\tdata <= $random;\n\t\t\tdone_counting <= !($random & 31);\n\t\t\tack <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_done;\n\t\tint errortime_done;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,done_counting,ack,shift_ena_ref,shift_ena_dut,counting_ref,counting_dut,done_ref,done_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_ref),\n\t\t.counting(counting_ref),\n\t\t.done(done_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.shift_ena(shift_ena_dut),\n\t\t.counting(counting_dut),\n\t\t.done(done_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref, counting_ref, done_ref } === ( { shift_ena_ref, counting_ref, done_ref } ^ { shift_ena_dut, counting_dut, done_dut } ^ { shift_ena_ref, counting_ref, done_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmonehot", "prompt": "module top_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n", "canonical_solution": " \n\t parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n \n\t parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d, done_counting, ack,\n\toutput reg [9:0] state,\n\tinput tb_match\n);\n\tbit failed = 0;\n\tbit fail_onehot = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\t\t{d, done_counting, ack} <= 3'h0;\n\t\tstate <= 10'h0;\n\t\t\n\t\trepeat(300) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\tend\n\n\t\t@(posedge clk) fail_onehot <= failed;\n\n\t\trepeat(3000) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t\n\t\t@(posedge clk);\n\t\tif (!fail_onehot && failed) begin\n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\t\t\t$display (\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_B3_next;\n\t\tint errortime_B3_next;\n\t\tint errors_S_next;\n\t\tint errortime_S_next;\n\t\tint errors_S1_next;\n\t\tint errortime_S1_next;\n\t\tint errors_Count_next;\n\t\tint errortime_Count_next;\n\t\tint errors_Wait_next;\n\t\tint errortime_Wait_next;\n\t\tint errors_done;\n\t\tint errortime_done;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic [9:0] state;\n\tlogic B3_next_ref;\n\tlogic B3_next_dut;\n\tlogic S_next_ref;\n\tlogic S_next_dut;\n\tlogic S1_next_ref;\n\tlogic S1_next_dut;\n\tlogic Count_next_ref;\n\tlogic Count_next_dut;\n\tlogic Wait_next_ref;\n\tlogic Wait_next_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,d,done_counting,ack,state,B3_next_ref,B3_next_dut,S_next_ref,S_next_dut,S1_next_ref,S1_next_dut,Count_next_ref,Count_next_dut,Wait_next_ref,Wait_next_dut,done_ref,done_dut,counting_ref,counting_dut,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state );\n\treference_module good1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_ref),\n\t\t.S_next(S_next_ref),\n\t\t.S1_next(S1_next_ref),\n\t\t.Count_next(Count_next_ref),\n\t\t.Wait_next(Wait_next_ref),\n\t\t.done(done_ref),\n\t\t.counting(counting_ref),\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_dut),\n\t\t.S_next(S_next_dut),\n\t\t.S1_next(S1_next_dut),\n\t\t.Count_next(Count_next_dut),\n\t\t.Wait_next(Wait_next_dut),\n\t\t.done(done_dut),\n\t\t.counting(counting_dut),\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_B3_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"B3_next\", stats1.errors_B3_next, stats1.errortime_B3_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"B3_next\");\n\t\tif (stats1.errors_S_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S_next\", stats1.errors_S_next, stats1.errortime_S_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S_next\");\n\t\tif (stats1.errors_S1_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S1_next\", stats1.errors_S1_next, stats1.errortime_S1_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S1_next\");\n\t\tif (stats1.errors_Count_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Count_next\", stats1.errors_Count_next, stats1.errortime_Count_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Count_next\");\n\t\tif (stats1.errors_Wait_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Wait_next\", stats1.errors_Wait_next, stats1.errortime_Wait_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Wait_next\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } === ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ^ { B3_next_dut, S_next_dut, S1_next_dut, Count_next_dut, Wait_next_dut, done_dut, counting_dut, shift_ena_dut } ^ { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (B3_next_ref !== ( B3_next_ref ^ B3_next_dut ^ B3_next_ref ))\n\t\tbegin if (stats1.errors_B3_next == 0) stats1.errortime_B3_next = $time;\n\t\t\tstats1.errors_B3_next = stats1.errors_B3_next+1'b1; end\n\t\tif (S_next_ref !== ( S_next_ref ^ S_next_dut ^ S_next_ref ))\n\t\tbegin if (stats1.errors_S_next == 0) stats1.errortime_S_next = $time;\n\t\t\tstats1.errors_S_next = stats1.errors_S_next+1'b1; end\n\t\tif (S1_next_ref !== ( S1_next_ref ^ S1_next_dut ^ S1_next_ref ))\n\t\tbegin if (stats1.errors_S1_next == 0) stats1.errortime_S1_next = $time;\n\t\t\tstats1.errors_S1_next = stats1.errors_S1_next+1'b1; end\n\t\tif (Count_next_ref !== ( Count_next_ref ^ Count_next_dut ^ Count_next_ref ))\n\t\tbegin if (stats1.errors_Count_next == 0) stats1.errortime_Count_next = $time;\n\t\t\tstats1.errors_Count_next = stats1.errors_Count_next+1'b1; end\n\t\tif (Wait_next_ref !== ( Wait_next_ref ^ Wait_next_dut ^ Wait_next_ref ))\n\t\tbegin if (stats1.errors_Wait_next == 0) stats1.errortime_Wait_next = $time;\n\t\t\tstats1.errors_Wait_next = stats1.errors_Wait_next+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmonehot", "prompt": "module top_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n", "canonical_solution": " \n\t parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n    input d,\n    input done_counting,\n    input ack,\n    input [9:0] state,    // 10-bit one-hot current state\n    output B3_next,\n    output S_next,\n    output S1_next,\n    output Count_next,\n    output Wait_next,\n    output done,\n    output counting,\n    output shift_ena\n );\n \n\t parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;\n\n\tassign B3_next = state[B2];\n\tassign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;\n\tassign S1_next = state[S]&d;\n\tassign Count_next = state[B3] | state[Count]&~done_counting;\n\tassign Wait_next = state[Count]&done_counting | state[Wait]&~ack;\n\n\tassign done = state[Wait];\n\tassign counting = state[Count];\n\tassign shift_ena = |state[B3:B0];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg d, done_counting, ack,\n\toutput reg [9:0] state,\n\tinput tb_match\n);\n\tbit failed = 0;\n\tbit fail_onehot = 0;\n\t\n\talways @(posedge clk, negedge clk)\n\t\tif (!tb_match) \n\t\t\tfailed <= 1;\n\t\n\tinitial begin\n\t\t{d, done_counting, ack} <= 3'h0;\n\t\tstate <= 10'h0;\n\t\t\n\t\trepeat(300) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= 1<< ($unsigned($random) % 10);\n\t\tend\n\n\t\t@(posedge clk) fail_onehot <= failed;\n\n\t\trepeat(3000) @(posedge clk, negedge clk) begin\n\t\t\t{d, done_counting, ack} = $random;\n\t\t\tstate <= $random;\n\t\tend\n\n\t\t\n\t\t@(posedge clk);\n\t\tif (!fail_onehot && failed) begin\n\t\t\t$display (\"Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.\");\n\t\t\t$display (\"Hint: Are you doing something more complicated than deriving state transition equations by inspection?\\n\");\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_B3_next;\n\t\tint errortime_B3_next;\n\t\tint errors_S_next;\n\t\tint errortime_S_next;\n\t\tint errors_S1_next;\n\t\tint errortime_S1_next;\n\t\tint errors_Count_next;\n\t\tint errortime_Count_next;\n\t\tint errors_Wait_next;\n\t\tint errortime_Wait_next;\n\t\tint errors_done;\n\t\tint errortime_done;\n\t\tint errors_counting;\n\t\tint errortime_counting;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic d;\n\tlogic done_counting;\n\tlogic ack;\n\tlogic [9:0] state;\n\tlogic B3_next_ref;\n\tlogic B3_next_dut;\n\tlogic S_next_ref;\n\tlogic S_next_dut;\n\tlogic S1_next_ref;\n\tlogic S1_next_dut;\n\tlogic Count_next_ref;\n\tlogic Count_next_dut;\n\tlogic Wait_next_ref;\n\tlogic Wait_next_dut;\n\tlogic done_ref;\n\tlogic done_dut;\n\tlogic counting_ref;\n\tlogic counting_dut;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,d,done_counting,ack,state,B3_next_ref,B3_next_dut,S_next_ref,S_next_dut,S1_next_ref,S1_next_dut,Count_next_ref,Count_next_dut,Wait_next_ref,Wait_next_dut,done_ref,done_dut,counting_ref,counting_dut,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state );\n\treference_module good1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_ref),\n\t\t.S_next(S_next_ref),\n\t\t.S1_next(S1_next_ref),\n\t\t.Count_next(Count_next_ref),\n\t\t.Wait_next(Wait_next_ref),\n\t\t.done(done_ref),\n\t\t.counting(counting_ref),\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.d,\n\t\t.done_counting,\n\t\t.ack,\n\t\t.state,\n\t\t.B3_next(B3_next_dut),\n\t\t.S_next(S_next_dut),\n\t\t.S1_next(S1_next_dut),\n\t\t.Count_next(Count_next_dut),\n\t\t.Wait_next(Wait_next_dut),\n\t\t.done(done_dut),\n\t\t.counting(counting_dut),\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_B3_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"B3_next\", stats1.errors_B3_next, stats1.errortime_B3_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"B3_next\");\n\t\tif (stats1.errors_S_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S_next\", stats1.errors_S_next, stats1.errortime_S_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S_next\");\n\t\tif (stats1.errors_S1_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"S1_next\", stats1.errors_S1_next, stats1.errortime_S1_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"S1_next\");\n\t\tif (stats1.errors_Count_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Count_next\", stats1.errors_Count_next, stats1.errortime_Count_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Count_next\");\n\t\tif (stats1.errors_Wait_next) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"Wait_next\", stats1.errors_Wait_next, stats1.errortime_Wait_next);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"Wait_next\");\n\t\tif (stats1.errors_done) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"done\", stats1.errors_done, stats1.errortime_done);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"done\");\n\t\tif (stats1.errors_counting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"counting\", stats1.errors_counting, stats1.errortime_counting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"counting\");\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } === ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ^ { B3_next_dut, S_next_dut, S1_next_dut, Count_next_dut, Wait_next_dut, done_dut, counting_dut, shift_ena_dut } ^ { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (B3_next_ref !== ( B3_next_ref ^ B3_next_dut ^ B3_next_ref ))\n\t\tbegin if (stats1.errors_B3_next == 0) stats1.errortime_B3_next = $time;\n\t\t\tstats1.errors_B3_next = stats1.errors_B3_next+1'b1; end\n\t\tif (S_next_ref !== ( S_next_ref ^ S_next_dut ^ S_next_ref ))\n\t\tbegin if (stats1.errors_S_next == 0) stats1.errortime_S_next = $time;\n\t\t\tstats1.errors_S_next = stats1.errors_S_next+1'b1; end\n\t\tif (S1_next_ref !== ( S1_next_ref ^ S1_next_dut ^ S1_next_ref ))\n\t\tbegin if (stats1.errors_S1_next == 0) stats1.errortime_S1_next = $time;\n\t\t\tstats1.errors_S1_next = stats1.errors_S1_next+1'b1; end\n\t\tif (Count_next_ref !== ( Count_next_ref ^ Count_next_dut ^ Count_next_ref ))\n\t\tbegin if (stats1.errors_Count_next == 0) stats1.errortime_Count_next = $time;\n\t\t\tstats1.errors_Count_next = stats1.errors_Count_next+1'b1; end\n\t\tif (Wait_next_ref !== ( Wait_next_ref ^ Wait_next_dut ^ Wait_next_ref ))\n\t\tbegin if (stats1.errors_Wait_next == 0) stats1.errortime_Wait_next = $time;\n\t\t\tstats1.errors_Wait_next = stats1.errors_Wait_next+1'b1; end\n\t\tif (done_ref !== ( done_ref ^ done_dut ^ done_ref ))\n\t\tbegin if (stats1.errors_done == 0) stats1.errortime_done = $time;\n\t\t\tstats1.errors_done = stats1.errors_done+1'b1; end\n\t\tif (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))\n\t\tbegin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;\n\t\t\tstats1.errors_counting = stats1.errors_counting+1'b1; end\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmseq", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n", "canonical_solution": "\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset, data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\twire [0:9] d = 10'b1110110011;\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tdata <= 1;\n\t\trepeat(2) @(posedge clk) ;\n\t\tdata <= 0;\n\t\t@(posedge clk);\n\t\tdata <= 1;\n\t\t@(posedge clk);\n\t\tdata <= 0;\n\t\n\t\twavedrom_start(\"Reset and sequence detect\");\n\t\treset_test();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(posedge clk) data <= d[i];\n\t\tend\n\t\twavedrom_stop();\n\t\trepeat(600) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tdata <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_start_shifting;\n\t\tint errortime_start_shifting;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic start_shifting_ref;\n\tlogic start_shifting_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,start_shifting_ref,start_shifting_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_start_shifting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"start_shifting\", stats1.errors_start_shifting, stats1.errortime_start_shifting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"start_shifting\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { start_shifting_ref } === ( { start_shifting_ref } ^ { start_shifting_dut } ^ { start_shifting_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (start_shifting_ref !== ( start_shifting_ref ^ start_shifting_dut ^ start_shifting_ref ))\n\t\tbegin if (stats1.errors_start_shifting == 0) stats1.errortime_start_shifting = $time;\n\t\t\tstats1.errors_start_shifting = stats1.errors_start_shifting+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmseq", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n", "canonical_solution": "\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\tinput data,\n\toutput start_shifting);\n\n\tparameter S=0, S1=1, S11=2, S110=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tS: next = data ? S1: S;\n\t\t\tS1: next = data ? S11: S;\n\t\t\tS11: next = data ? S11 : S110;\n\t\t\tS110: next = data ? Done : S;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= S;\n\t\telse state <= next;\n\t\t\n\tassign start_shifting = state == Done;\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset, data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\tinput tb_match\n);\n\n\ttask reset_test(input async=0);\n\t\tbit arfail, srfail, datafail;\n\t\n\t\t@(posedge clk);\n\t\t@(posedge clk) reset <= 0;\n\t\trepeat(3) @(posedge clk);\n\t\n\t\t@(negedge clk) begin datafail = !tb_match ; reset <= 1; end\n\t\t@(posedge clk) arfail = !tb_match;\n\t\t@(posedge clk) begin\n\t\t\tsrfail = !tb_match;\n\t\t\treset <= 0;\n\t\tend\n\t\tif (srfail)\n\t\t\t$display(\"Hint: Your reset doesn't seem to be working.\");\n\t\telse if (arfail && (async || !datafail))\n\t\t\t$display(\"Hint: Your reset should be %0s, but doesn't appear to be.\", async ? \"asynchronous\" : \"synchronous\");\n\t\t// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely\n\t\t// a functionality error than the reset being implemented asynchronously.\n\t\n\tendtask\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\twire [0:9] d = 10'b1110110011;\n\t\n\t\n\tinitial begin\n\t\treset <= 1;\n\t\t@(posedge clk) reset <= 0;\n\t\tdata <= 1;\n\t\trepeat(2) @(posedge clk) ;\n\t\tdata <= 0;\n\t\t@(posedge clk);\n\t\tdata <= 1;\n\t\t@(posedge clk);\n\t\tdata <= 0;\n\t\n\t\twavedrom_start(\"Reset and sequence detect\");\n\t\treset_test();\n\t\tfor (int i=0;i<10;i++) begin\n\t\t\t@(posedge clk) data <= d[i];\n\t\tend\n\t\twavedrom_stop();\n\t\trepeat(600) @(posedge clk, negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\t\tdata <= $random;\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_start_shifting;\n\t\tint errortime_start_shifting;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic data;\n\tlogic start_shifting_ref;\n\tlogic start_shifting_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,start_shifting_ref,start_shifting_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.data,\n\t\t.start_shifting(start_shifting_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_start_shifting) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"start_shifting\", stats1.errors_start_shifting, stats1.errortime_start_shifting);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"start_shifting\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { start_shifting_ref } === ( { start_shifting_ref } ^ { start_shifting_dut } ^ { start_shifting_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (start_shifting_ref !== ( start_shifting_ref ^ start_shifting_dut ^ start_shifting_ref ))\n\t\tbegin if (stats1.errors_start_shifting == 0) stats1.errortime_start_shifting = $time;\n\t\t\tstats1.errors_start_shifting = stats1.errors_start_shifting+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmshift", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n", "canonical_solution": "\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref } === ( { shift_ena_ref } ^ { shift_ena_dut } ^ { shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "review2015_fsmshift", "prompt": "module top_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n", "canonical_solution": "\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput reset,\n\toutput shift_ena);\n\n\tparameter B0=0, B1=1, B2=2, B3=3, Done=4;\n\t\n\treg [2:0] state, next;\n\t\n\talways_comb begin\n\t\tcase (state)\n\t\t\tB0: next = B1;\n\t\t\tB1: next = B2;\n\t\t\tB2: next = B3;\n\t\t\tB3: next = Done;\n\t\t\tDone: next = Done;\n\t\tendcase\n\tend\n\t\n\talways @(posedge clk)\n\t\tif (reset) state <= B0;\n\t\telse state <= next;\n\t\t\n\tassign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);\n\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg reset\n);\n\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk) begin\n\t\t\treset <= !($random & 31);\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_shift_ena;\n\t\tint errortime_shift_ena;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic reset;\n\tlogic shift_ena_ref;\n\tlogic shift_ena_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,shift_ena_ref,shift_ena_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.reset );\n\treference_module good1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.reset,\n\t\t.shift_ena(shift_ena_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_shift_ena) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"shift_ena\", stats1.errors_shift_ena, stats1.errortime_shift_ena);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"shift_ena\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { shift_ena_ref } === ( { shift_ena_ref } ^ { shift_ena_dut } ^ { shift_ena_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))\n\t\tbegin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;\n\t\t\tstats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ringer", "prompt": "module top_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n", "canonical_solution": "\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg ring, vibrate_mode,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{vibrate_mode,ring} <= 1'b0;\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\t{vibrate_mode,ring} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ringer;\n\t\tint errortime_ringer;\n\t\tint errors_motor;\n\t\tint errortime_motor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic ring;\n\tlogic vibrate_mode;\n\tlogic ringer_ref;\n\tlogic ringer_dut;\n\tlogic motor_ref;\n\tlogic motor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.ring,\n\t\t.vibrate_mode );\n\treference_module good1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_ref),\n\t\t.motor(motor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_dut),\n\t\t.motor(motor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ringer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ringer\", stats1.errors_ringer, stats1.errortime_ringer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ringer\");\n\t\tif (stats1.errors_motor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"motor\", stats1.errors_motor, stats1.errortime_motor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"motor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))\n\t\tbegin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;\n\t\t\tstats1.errors_ringer = stats1.errors_ringer+1'b1; end\n\t\tif (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))\n\t\tbegin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;\n\t\t\tstats1.errors_motor = stats1.errors_motor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "ringer", "prompt": "module top_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n", "canonical_solution": "\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput ring, \n\tinput vibrate_mode,\n\toutput ringer,\n\toutput motor\n);\n\t\n\tassign ringer = ring & ~vibrate_mode;\n\tassign motor = ring & vibrate_mode;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg ring, vibrate_mode,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\t{vibrate_mode,ring} <= 1'b0;\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\t{vibrate_mode,ring} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_ringer;\n\t\tint errortime_ringer;\n\t\tint errors_motor;\n\t\tint errortime_motor;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic ring;\n\tlogic vibrate_mode;\n\tlogic ringer_ref;\n\tlogic ringer_dut;\n\tlogic motor_ref;\n\tlogic motor_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.ring,\n\t\t.vibrate_mode );\n\treference_module good1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_ref),\n\t\t.motor(motor_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.ring,\n\t\t.vibrate_mode,\n\t\t.ringer(ringer_dut),\n\t\t.motor(motor_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_ringer) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"ringer\", stats1.errors_ringer, stats1.errortime_ringer);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"ringer\");\n\t\tif (stats1.errors_motor) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"motor\", stats1.errors_motor, stats1.errortime_motor);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"motor\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))\n\t\tbegin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;\n\t\t\tstats1.errors_ringer = stats1.errors_ringer+1'b1; end\n\t\tif (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))\n\t\tbegin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;\n\t\t\tstats1.errors_motor = stats1.errors_motor+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rotate100", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n", "canonical_solution": "\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[1:0] ena,\n\toutput reg[99:0] data\n);\n\n\talways @(posedge clk)\n\t\tdata <= {$random,$random,$random,$random};\n\t\n\tinitial begin\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\trepeat(4000) @(posedge clk, negedge clk) begin\n\t\t\tload <= !($random & 31);\n\t\t\tena <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [1:0] ena;\n\tlogic [99:0] data;\n\tlogic [99:0] q_ref;\n\tlogic [99:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.ena,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rotate100", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n", "canonical_solution": "\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [1:0] ena,\n\tinput [99:0] data,\n\toutput reg [99:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena == 2'h1)\n\t\t\tq <= {q[0], q[99:1]};\n\t\telse if (ena == 2'h2)\n\t\t\tq <= {q[98:0], q[99]};\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[1:0] ena,\n\toutput reg[99:0] data\n);\n\n\talways @(posedge clk)\n\t\tdata <= {$random,$random,$random,$random};\n\t\n\tinitial begin\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\trepeat(4000) @(posedge clk, negedge clk) begin\n\t\t\tload <= !($random & 31);\n\t\t\tena <= $random;\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [1:0] ena;\n\tlogic [99:0] data;\n\tlogic [99:0] q_ref;\n\tlogic [99:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.ena,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule110", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Load q[511:0] = 1: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\t\t\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h4df;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat (20) @(posedge clk);\n\t\t@(posedge clk) data <= 2;\n\t\t@(posedge clk) data <= 4;\n\t\t@(posedge clk) begin\n\t\t\tdata <= 9;\n\t\t\tload <= 0;\n\t\tend\n\t\t@(posedge clk) data <= 12;\n\t\trepeat(100) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule110", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= \n\t\t\t~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |\n\t\t\t(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |  \n\t\t\t(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )\n\t\t\t;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Load q[511:0] = 1: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\t\t\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h4df;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat (20) @(posedge clk);\n\t\t@(posedge clk) data <= 2;\n\t\t@(posedge clk) data <= 4;\n\t\t@(posedge clk) begin\n\t\t\tdata <= 9;\n\t\t\tload <= 0;\n\t\tend\n\t\t@(posedge clk) data <= 12;\n\t\trepeat(100) @(posedge clk);\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule90", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Sierpi&#324;ski triangle: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\n\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h1000000000000001;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat(20) @(posedge clk);\n\t\trepeat(2) @(posedge clk) data <= data + 2;\n\t\t@(posedge clk) begin \n\t\t\tload <= 0;\n\t\t\tdata <= data + 1;\n\t\tend\n\t\trepeat(20) @(posedge clk) data <= data + 1;\n\t\trepeat(500) @(posedge clk) begin\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "rule90", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n", "canonical_solution": "\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput [511:0] data,\n\toutput reg [511:0] q);\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse begin\n\t\t\tq <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;\n\t\tend\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg[511:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tdata <= 0;\n\t\tdata[0] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk); wavedrom_start(\"Sierpi&#324;ski triangle: See Hint.\");\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(10) @(posedge clk);\t\t\n\t\twavedrom_stop();\n\n\n\t\tdata <= 0;\n\t\tdata[256] <= 1'b1;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\t\tdata <= 512'h1000000000000001;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= $random;\n\t\tload <= 1;\n\t\t@(posedge clk);\n\t\tload <= 0;\n\t\trepeat(1000) @(posedge clk) begin\n\t\tend\n\n\t\tdata <= 0;\n\t\tload <= 1;\n\t\trepeat(20) @(posedge clk);\n\t\trepeat(2) @(posedge clk) data <= data + 2;\n\t\t@(posedge clk) begin \n\t\t\tload <= 0;\n\t\t\tdata <= data + 1;\n\t\tend\n\t\trepeat(20) @(posedge clk) data <= data + 1;\n\t\trepeat(500) @(posedge clk) begin\n\t\tend\n\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [511:0] data;\n\tlogic [511:0] q_ref;\n\tlogic [511:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "shift18", "prompt": "module top_module(\n\tinput clk,\n\tinput load,\n\tinput ena,\n\tinput [1:0] amount,\n\tinput [63:0] data,\n\toutput reg [63:0] q);\n", "canonical_solution": "\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena) case (amount)\n\t\t\t2'b00: q <= {q[62:0], 1'b0};\n\t\t\t2'b01: q <= {q[55:0], 8'b0};\n\t\t\t2'b10: q <= {q[63], q[63:1]};\n\t\t\t2'b11: q <= {{8{q[63]}}, q[63:8]};\n\t\t\tdefault: q <= 64'hx;\n\t\tendcase\n\tend\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk,\n\tinput load,\n\tinput ena,\n\tinput [1:0] amount,\n\tinput [63:0] data,\n\toutput reg [63:0] q);\n\t\n\t\n\talways @(posedge clk) begin\n\t\tif (load)\n\t\t\tq <= data;\n\t\telse if (ena) case (amount)\n\t\t\t2'b00: q <= {q[62:0], 1'b0};\n\t\t\t2'b01: q <= {q[55:0], 8'b0};\n\t\t\t2'b10: q <= {q[63], q[63:1]};\n\t\t\t2'b11: q <= {{8{q[63]}}, q[63:8]};\n\t\t\tdefault: q <= 64'hx;\n\t\tendcase\n\tend\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg load,\n\toutput reg ena,\n\toutput reg[1:0] amount,\n\toutput reg[63:0] data,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tload <= 1;\n\t\tena <= 0;\n\t\tdata <= 'x;\n\t\tamount <= 0;\n\t\t@(posedge clk) data <= 64'h000100;\n\t\twavedrom_start(\"Shifting\");\n\t\t\t@(posedge clk) load <= 0; ena <= 1;\n\t\t\t\t\t\t\tamount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 1;\n\t\t\t@(posedge clk) amount <= 1;\n\t\t\t@(posedge clk) amount <= 0;\n\t\t\t@(posedge clk) amount <= 0;\n\t\t\t@(posedge clk) amount <= 3;\n\t\t\t@(posedge clk) amount <= 3;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t@(posedge clk); load <= 1; data <= 64'hx;\n\t\t@(posedge clk); load <= 1; data <= 64'h80000000_00000000;\n\t\twavedrom_start(\"Arithmetic right shift\");\n\t\t\t@(posedge clk) load <= 0; ena <= 1;\n\t\t\t\t\t\t\tamount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(posedge clk) amount <= 2;\n\t\t\t@(negedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk);\n\t\t@(posedge clk);\n\t\t\n\t\t\n\t\t\n\t\trepeat(4000) @(posedge clk, negedge clk) begin\n\t\t\tload <= !($random & 31);\n\t\t\tena <= |($random & 15);\n\t\t\tamount <= $random;\n\t\t\tdata <= {$random,$random};\n\t\tend\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_q;\n\t\tint errortime_q;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic ena;\n\tlogic [1:0] amount;\n\tlogic [63:0] data;\n\tlogic [63:0] q_ref;\n\tlogic [63:0] q_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,amount,data,q_ref,q_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data,\n\t\t.q(q_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.ena,\n\t\t.amount,\n\t\t.data,\n\t\t.q(q_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_q) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"q\", stats1.errors_q, stats1.errortime_q);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"q\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (q_ref !== ( q_ref ^ q_dut ^ q_ref ))\n\t\tbegin if (stats1.errors_q == 0) stats1.errortime_q = $time;\n\t\t\tstats1.errors_q = stats1.errors_q+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "step_one", "prompt": "module top_module(\n\toutput one);\n", "canonical_solution": "\t\n\tassign one = 1'b1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput one);\n\t\n\tassign one = 1'b1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should be 1\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_one;\n\t\tint errortime_one;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic one_ref;\n\tlogic one_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,one_ref,one_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.one(one_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.one(one_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_one) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"one\", stats1.errors_one, stats1.errortime_one);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"one\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { one_ref } === ( { one_ref } ^ { one_dut } ^ { one_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (one_ref !== ( one_ref ^ one_dut ^ one_ref ))\n\t\tbegin if (stats1.errors_one == 0) stats1.errortime_one = $time;\n\t\t\tstats1.errors_one = stats1.errors_one+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "step_one", "prompt": "module top_module(\n\toutput one);\n", "canonical_solution": "\t\n\tassign one = 1'b1;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput one);\n\t\n\tassign one = 1'b1;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should be 1\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_one;\n\t\tint errortime_one;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic one_ref;\n\tlogic one_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,one_ref,one_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.one(one_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.one(one_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_one) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"one\", stats1.errors_one, stats1.errortime_one);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"one\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { one_ref } === ( { one_ref } ^ { one_dut } ^ { one_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (one_ref !== ( one_ref ^ one_dut ^ one_ref ))\n\t\tbegin if (stats1.errors_one == 0) stats1.errortime_one = $time;\n\t\t\tstats1.errors_one = stats1.errors_one+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "thermostat", "prompt": "module top_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n", "canonical_solution": "\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg too_cold, too_hot, mode, fan_on,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Winter\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0111;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1111;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Summer\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0101;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1101;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) {too_cold, too_hot, mode, fan_on} <= $random;\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_heater;\n\t\tint errortime_heater;\n\t\tint errors_aircon;\n\t\tint errortime_aircon;\n\t\tint errors_fan;\n\t\tint errortime_fan;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic mode;\n\tlogic too_cold;\n\tlogic too_hot;\n\tlogic fan_on;\n\tlogic heater_ref;\n\tlogic heater_dut;\n\tlogic aircon_ref;\n\tlogic aircon_dut;\n\tlogic fan_ref;\n\tlogic fan_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,mode,too_cold,too_hot,fan_on,heater_ref,heater_dut,aircon_ref,aircon_dut,fan_ref,fan_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on );\n\treference_module good1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_ref),\n\t\t.aircon(aircon_ref),\n\t\t.fan(fan_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_dut),\n\t\t.aircon(aircon_dut),\n\t\t.fan(fan_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_heater) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"heater\", stats1.errors_heater, stats1.errortime_heater);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"heater\");\n\t\tif (stats1.errors_aircon) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aircon\", stats1.errors_aircon, stats1.errortime_aircon);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aircon\");\n\t\tif (stats1.errors_fan) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fan\", stats1.errors_fan, stats1.errortime_fan);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fan\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { heater_ref, aircon_ref, fan_ref } === ( { heater_ref, aircon_ref, fan_ref } ^ { heater_dut, aircon_dut, fan_dut } ^ { heater_ref, aircon_ref, fan_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (heater_ref !== ( heater_ref ^ heater_dut ^ heater_ref ))\n\t\tbegin if (stats1.errors_heater == 0) stats1.errortime_heater = $time;\n\t\t\tstats1.errors_heater = stats1.errors_heater+1'b1; end\n\t\tif (aircon_ref !== ( aircon_ref ^ aircon_dut ^ aircon_ref ))\n\t\tbegin if (stats1.errors_aircon == 0) stats1.errortime_aircon = $time;\n\t\t\tstats1.errors_aircon = stats1.errors_aircon+1'b1; end\n\t\tif (fan_ref !== ( fan_ref ^ fan_dut ^ fan_ref ))\n\t\tbegin if (stats1.errors_fan == 0) stats1.errortime_fan = $time;\n\t\t\tstats1.errors_fan = stats1.errors_fan+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "thermostat", "prompt": "module top_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n", "canonical_solution": "\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput mode,\n\tinput too_cold, \n\tinput too_hot,\n\tinput fan_on,\n\toutput heater,\n\toutput aircon,\n\toutput fan\n);\n\t\n\tassign fan = (mode ? too_cold : too_hot) | fan_on;\n\tassign heater = (mode & too_cold);\n\tassign aircon = (~mode & too_hot);\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg too_cold, too_hot, mode, fan_on,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Winter\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0011;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1110;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0111;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1111;\n\t\t@(negedge clk) wavedrom_stop();\n\n\t\t{too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Summer\");\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0101;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1000;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1100;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1001;\n\t\t\t@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1101;\n\t\t@(negedge clk) wavedrom_stop();\n\t\t\n\t\trepeat(200)\n\t\t\t@(posedge clk, negedge clk) {too_cold, too_hot, mode, fan_on} <= $random;\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_heater;\n\t\tint errortime_heater;\n\t\tint errors_aircon;\n\t\tint errortime_aircon;\n\t\tint errors_fan;\n\t\tint errortime_fan;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic mode;\n\tlogic too_cold;\n\tlogic too_hot;\n\tlogic fan_on;\n\tlogic heater_ref;\n\tlogic heater_dut;\n\tlogic aircon_ref;\n\tlogic aircon_dut;\n\tlogic fan_ref;\n\tlogic fan_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,mode,too_cold,too_hot,fan_on,heater_ref,heater_dut,aircon_ref,aircon_dut,fan_ref,fan_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on );\n\treference_module good1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_ref),\n\t\t.aircon(aircon_ref),\n\t\t.fan(fan_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.mode,\n\t\t.too_cold,\n\t\t.too_hot,\n\t\t.fan_on,\n\t\t.heater(heater_dut),\n\t\t.aircon(aircon_dut),\n\t\t.fan(fan_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_heater) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"heater\", stats1.errors_heater, stats1.errortime_heater);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"heater\");\n\t\tif (stats1.errors_aircon) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"aircon\", stats1.errors_aircon, stats1.errortime_aircon);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"aircon\");\n\t\tif (stats1.errors_fan) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"fan\", stats1.errors_fan, stats1.errortime_fan);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"fan\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { heater_ref, aircon_ref, fan_ref } === ( { heater_ref, aircon_ref, fan_ref } ^ { heater_dut, aircon_dut, fan_dut } ^ { heater_ref, aircon_ref, fan_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (heater_ref !== ( heater_ref ^ heater_dut ^ heater_ref ))\n\t\tbegin if (stats1.errors_heater == 0) stats1.errortime_heater = $time;\n\t\t\tstats1.errors_heater = stats1.errors_heater+1'b1; end\n\t\tif (aircon_ref !== ( aircon_ref ^ aircon_dut ^ aircon_ref ))\n\t\tbegin if (stats1.errors_aircon == 0) stats1.errortime_aircon = $time;\n\t\t\tstats1.errors_aircon = stats1.errors_aircon+1'b1; end\n\t\tif (fan_ref !== ( fan_ref ^ fan_dut ^ fan_ref ))\n\t\tbegin if (stats1.errors_fan == 0) stats1.errortime_fan = $time;\n\t\t\tstats1.errors_fan = stats1.errors_fan+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "timer", "prompt": "module top_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n", "canonical_solution": "\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n\nmodule stimulus_gen(\n\tinput clk, \n\toutput logic load, \n\toutput logic [9:0] data, \n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tload <= 1'b0;\n\t\twavedrom_start(\"Count 3, then 10 cycles\");\n\t\t\t@(posedge clk) {data, load} <= {10'd3, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) {data, load} <= {10'd10, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h0};   // Load 0\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h3ff}; // Load 1023\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h0};\n\t\trepeat(1040) @(posedge clk);\n\n\t\trepeat(2500) @(posedge clk) begin\n\t\t\tload <= !($urandom & 10'hf);\n\t\t\tdata <= $urandom_range(0,32);\n\t\tend\n\n\t\t\n\t\t#1 $finish;\n\tend\n\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_tc;\n\t\tint errortime_tc;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [9:0] data;\n\tlogic tc_ref;\n\tlogic tc_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,tc_ref,tc_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_tc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"tc\", stats1.errors_tc, stats1.errortime_tc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"tc\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { tc_ref } === ( { tc_ref } ^ { tc_dut } ^ { tc_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (tc_ref !== ( tc_ref ^ tc_dut ^ tc_ref ))\n\t\tbegin if (stats1.errors_tc == 0) stats1.errortime_tc = $time;\n\t\t\tstats1.errors_tc = stats1.errors_tc+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "timer", "prompt": "module top_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n", "canonical_solution": "\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput clk, \n\tinput load, \n\tinput [9:0] data, \n\toutput tc\n);\n\tlogic [9:0] count_value;\n\n\talways @(posedge clk)\n\t\tif(load) count_value <= data;\n\t\telse if(count_value != 0) count_value <= count_value - 1;\n\n\tassign tc = count_value == 0;\n\nendmodule\n\nmodule stimulus_gen(\n\tinput clk, \n\toutput logic load, \n\toutput logic [9:0] data, \n\tinput tb_match,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable,\n\toutput int wavedrom_hide_after_time\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\tload <= 1'b0;\n\t\twavedrom_start(\"Count 3, then 10 cycles\");\n\t\t\t@(posedge clk) {data, load} <= {10'd3, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) load <= 0;\n\t\t\t@(posedge clk) {data, load} <= {10'd10, 1'b1};\n\t\t\t@(posedge clk) {data, load} <= {10'hx, 1'b0};\n\t\t\trepeat(12) @(posedge clk);\n\t\twavedrom_stop();\n\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h10};\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h0};   // Load 0\n\t\t@(posedge clk) {load, data} <= {1'b1, 10'h3ff}; // Load 1023\n\t\t@(posedge clk) {load, data} <= {1'b0, 10'h0};\n\t\trepeat(1040) @(posedge clk);\n\n\t\trepeat(2500) @(posedge clk) begin\n\t\t\tload <= !($urandom & 10'hf);\n\t\t\tdata <= $urandom_range(0,32);\n\t\tend\n\n\t\t\n\t\t#1 $finish;\n\tend\n\nendmodule\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_tc;\n\t\tint errortime_tc;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic load;\n\tlogic [9:0] data;\n\tlogic tc_ref;\n\tlogic tc_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,tc_ref,tc_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.load,\n\t\t.data );\n\treference_module good1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.clk,\n\t\t.load,\n\t\t.data,\n\t\t.tc(tc_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_tc) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"tc\", stats1.errors_tc, stats1.errortime_tc);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"tc\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { tc_ref } === ( { tc_ref } ^ { tc_dut } ^ { tc_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (tc_ref !== ( tc_ref ^ tc_dut ^ tc_ref ))\n\t\tbegin if (stats1.errors_tc == 0) stats1.errortime_tc = $time;\n\t\t\tstats1.errors_tc = stats1.errors_tc+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "truthtable1", "prompt": "module top_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n", "canonical_solution": "\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg x3, x2, x1,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x3, x2, x1} <= 3'h7;\n\t\t@(negedge clk) wavedrom_start(\"All 8 input combinations\");\n\t\trepeat(8) @(posedge clk) {x3, x2, x1} <= {x3, x2, x1} + 1'b1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(40) @(posedge clk, negedge clk);\n\t\t{x3, x2, x1} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x3;\n\tlogic x2;\n\tlogic x1;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x3,x2,x1,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x3,\n\t\t.x2,\n\t\t.x1 );\n\treference_module good1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "truthtable1", "prompt": "module top_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n", "canonical_solution": "\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput x3,\n\tinput x2,\n\tinput x1,\n\toutput f\n);\n\t\n\tassign f = ( ~x3 & x2 & ~x1 ) | \n\t\t\t\t( ~x3 & x2 & x1 ) |\n\t\t\t\t( x3 & ~x2 & x1 ) |\n\t\t\t\t( x3 & x2 & x1 ) ;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg x3, x2, x1,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\t\n\tinitial begin\n\t\t{x3, x2, x1} <= 3'h7;\n\t\t@(negedge clk) wavedrom_start(\"All 8 input combinations\");\n\t\trepeat(8) @(posedge clk) {x3, x2, x1} <= {x3, x2, x1} + 1'b1;\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(40) @(posedge clk, negedge clk);\n\t\t{x3, x2, x1} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_f;\n\t\tint errortime_f;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic x3;\n\tlogic x2;\n\tlogic x1;\n\tlogic f_ref;\n\tlogic f_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,x3,x2,x1,f_ref,f_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.x3,\n\t\t.x2,\n\t\t.x1 );\n\treference_module good1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.x3,\n\t\t.x2,\n\t\t.x1,\n\t\t.f(f_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_f) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"f\", stats1.errors_f, stats1.errortime_f);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"f\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (f_ref !== ( f_ref ^ f_dut ^ f_ref ))\n\t\tbegin if (stats1.errors_f == 0) stats1.errortime_f = $time;\n\t\t\tstats1.errors_f = stats1.errors_f+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector0", "prompt": "module top_module(\n\tinput [2:0] vec, \n\toutput [2:0] outv,\n\toutput o2,\n\toutput o1,\n\toutput o0\n);\n", "canonical_solution": "\t\n\tassign outv = vec;\n\tassign {o2, o1, o0} = vec;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [2:0] vec, \n\toutput [2:0] outv,\n\toutput o2,\n\toutput o1,\n\toutput o0\n);\n\t\n\tassign outv = vec;\n\tassign {o2, o1, o0} = vec;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [2:0] vec,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 0;\n\t\tvec <= 3'b0;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\trepeat(10) @(posedge clk)\n\t\t\tvec <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_outv;\n\t\tint errortime_outv;\n\t\tint errors_o2;\n\t\tint errortime_o2;\n\t\tint errors_o1;\n\t\tint errortime_o1;\n\t\tint errors_o0;\n\t\tint errortime_o0;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] vec;\n\tlogic [2:0] outv_ref;\n\tlogic [2:0] outv_dut;\n\tlogic o2_ref;\n\tlogic o2_dut;\n\tlogic o1_ref;\n\tlogic o1_dut;\n\tlogic o0_ref;\n\tlogic o0_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,vec,outv_ref,outv_dut,o2_ref,o2_dut,o1_ref,o1_dut,o0_ref,o0_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.vec );\n\treference_module good1 (\n\t\t.vec,\n\t\t.outv(outv_ref),\n\t\t.o2(o2_ref),\n\t\t.o1(o1_ref),\n\t\t.o0(o0_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.vec,\n\t\t.outv(outv_dut),\n\t\t.o2(o2_dut),\n\t\t.o1(o1_dut),\n\t\t.o0(o0_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_outv) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"outv\", stats1.errors_outv, stats1.errortime_outv);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"outv\");\n\t\tif (stats1.errors_o2) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o2\", stats1.errors_o2, stats1.errortime_o2);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o2\");\n\t\tif (stats1.errors_o1) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o1\", stats1.errors_o1, stats1.errortime_o1);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o1\");\n\t\tif (stats1.errors_o0) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"o0\", stats1.errors_o0, stats1.errortime_o0);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"o0\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { outv_ref, o2_ref, o1_ref, o0_ref } === ( { outv_ref, o2_ref, o1_ref, o0_ref } ^ { outv_dut, o2_dut, o1_dut, o0_dut } ^ { outv_ref, o2_ref, o1_ref, o0_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (outv_ref !== ( outv_ref ^ outv_dut ^ outv_ref ))\n\t\tbegin if (stats1.errors_outv == 0) stats1.errortime_outv = $time;\n\t\t\tstats1.errors_outv = stats1.errors_outv+1'b1; end\n\t\tif (o2_ref !== ( o2_ref ^ o2_dut ^ o2_ref ))\n\t\tbegin if (stats1.errors_o2 == 0) stats1.errortime_o2 = $time;\n\t\t\tstats1.errors_o2 = stats1.errors_o2+1'b1; end\n\t\tif (o1_ref !== ( o1_ref ^ o1_dut ^ o1_ref ))\n\t\tbegin if (stats1.errors_o1 == 0) stats1.errortime_o1 = $time;\n\t\t\tstats1.errors_o1 = stats1.errors_o1+1'b1; end\n\t\tif (o0_ref !== ( o0_ref ^ o0_dut ^ o0_ref ))\n\t\tbegin if (stats1.errors_o0 == 0) stats1.errortime_o0 = $time;\n\t\t\tstats1.errors_o0 = stats1.errors_o0+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector100r", "prompt": "module top_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n", "canonical_solution": "\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [99:0] in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\tin <= {$random, $random, $random, $random};\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [99:0] out_ref;\n\tlogic [99:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector100r", "prompt": "module top_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n", "canonical_solution": "\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [99:0] in,\n\toutput reg [99:0] out\n);\n\t\n\talways_comb \n\t\tfor (int i=0;i<$bits(out);i++)\n\t\t\tout[i] = in[$bits(out)-i-1];\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [99:0] in\n);\n\n\talways @(posedge clk, negedge clk)\n\t\tin <= {$random, $random, $random, $random};\n\t\n\tinitial begin\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [99:0] in;\n\tlogic [99:0] out_ref;\n\tlogic [99:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector2", "prompt": "module top_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n", "canonical_solution": "\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [31:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Random inputs\");\n\t\trepeat(10) @(posedge clk, negedge clk) \n\t\t\tin <= $random;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector2", "prompt": "module top_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n", "canonical_solution": "\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [31:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = {in[7:0], in[15:8], in[23:16], in[31:24]};\t\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [31:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\t\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Random inputs\");\n\t\trepeat(10) @(posedge clk, negedge clk) \n\t\t\tin <= $random;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [31:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector3", "prompt": "module top_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n", "canonical_solution": "\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:0] a,b,c,d,e,f,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\tinitial begin\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) {a,b,c,d,e,f} <= '0;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 1;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 2;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 4;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 8;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h10;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h20;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h40;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h80;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h100;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h200;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h400;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= {5'h1f, 5'h0, 5'h1f, 5'h0, 5'h1f, 5'h0};\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e,f} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_w;\n\t\tint errortime_w;\n\t\tint errors_x;\n\t\tint errortime_x;\n\t\tint errors_y;\n\t\tint errortime_y;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:0] a;\n\tlogic [4:0] b;\n\tlogic [4:0] c;\n\tlogic [4:0] d;\n\tlogic [4:0] e;\n\tlogic [4:0] f;\n\tlogic [7:0] w_ref;\n\tlogic [7:0] w_dut;\n\tlogic [7:0] x_ref;\n\tlogic [7:0] x_dut;\n\tlogic [7:0] y_ref;\n\tlogic [7:0] y_dut;\n\tlogic [7:0] z_ref;\n\tlogic [7:0] z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_ref),\n\t\t.x(x_ref),\n\t\t.y(y_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_dut),\n\t\t.x(x_dut),\n\t\t.y(y_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_w) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"w\", stats1.errors_w, stats1.errortime_w);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"w\");\n\t\tif (stats1.errors_x) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"x\", stats1.errors_x, stats1.errortime_x);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"x\");\n\t\tif (stats1.errors_y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"y\", stats1.errors_y, stats1.errortime_y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"y\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (w_ref !== ( w_ref ^ w_dut ^ w_ref ))\n\t\tbegin if (stats1.errors_w == 0) stats1.errortime_w = $time;\n\t\t\tstats1.errors_w = stats1.errors_w+1'b1; end\n\t\tif (x_ref !== ( x_ref ^ x_dut ^ x_ref ))\n\t\tbegin if (stats1.errors_x == 0) stats1.errortime_x = $time;\n\t\t\tstats1.errors_x = stats1.errors_x+1'b1; end\n\t\tif (y_ref !== ( y_ref ^ y_dut ^ y_ref ))\n\t\tbegin if (stats1.errors_y == 0) stats1.errortime_y = $time;\n\t\t\tstats1.errors_y = stats1.errors_y+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector3", "prompt": "module top_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n", "canonical_solution": "\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [4:0] a,\n\tinput [4:0] b,\n\tinput [4:0] c,\n\tinput [4:0] d,\n\tinput [4:0] e,\n\tinput [4:0] f,\n\toutput [7:0] w,\n\toutput [7:0] x,\n\toutput [7:0] y,\n\toutput [7:0] z\n);\n\n\tassign { w,x,y,z} = {a,b,c,d,e,f,2'b11};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [4:0] a,b,c,d,e,f,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\t\n);\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\tinitial begin\n\t\twavedrom_start(\"\");\n\t\t@(posedge clk) {a,b,c,d,e,f} <= '0;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 1;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 2;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 4;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 8;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h10;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h20;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h40;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h80;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h100;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h200;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= 'h400;\n\t\t@(posedge clk) {a,b,c,d,e,f} <= {5'h1f, 5'h0, 5'h1f, 5'h0, 5'h1f, 5'h0};\n\t\t@(negedge clk);\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e,f} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_w;\n\t\tint errortime_w;\n\t\tint errors_x;\n\t\tint errortime_x;\n\t\tint errors_y;\n\t\tint errortime_y;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [4:0] a;\n\tlogic [4:0] b;\n\tlogic [4:0] c;\n\tlogic [4:0] d;\n\tlogic [4:0] e;\n\tlogic [4:0] f;\n\tlogic [7:0] w_ref;\n\tlogic [7:0] w_dut;\n\tlogic [7:0] x_ref;\n\tlogic [7:0] x_dut;\n\tlogic [7:0] y_ref;\n\tlogic [7:0] y_dut;\n\tlogic [7:0] z_ref;\n\tlogic [7:0] z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_ref),\n\t\t.x(x_ref),\n\t\t.y(y_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.f,\n\t\t.w(w_dut),\n\t\t.x(x_dut),\n\t\t.y(y_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_w) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"w\", stats1.errors_w, stats1.errortime_w);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"w\");\n\t\tif (stats1.errors_x) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"x\", stats1.errors_x, stats1.errortime_x);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"x\");\n\t\tif (stats1.errors_y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"y\", stats1.errors_y, stats1.errortime_y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"y\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (w_ref !== ( w_ref ^ w_dut ^ w_ref ))\n\t\tbegin if (stats1.errors_w == 0) stats1.errortime_w = $time;\n\t\t\tstats1.errors_w = stats1.errors_w+1'b1; end\n\t\tif (x_ref !== ( x_ref ^ x_dut ^ x_ref ))\n\t\tbegin if (stats1.errors_x == 0) stats1.errortime_x = $time;\n\t\t\tstats1.errors_x = stats1.errors_x+1'b1; end\n\t\tif (y_ref !== ( y_ref ^ y_dut ^ y_ref ))\n\t\tbegin if (stats1.errors_y == 0) stats1.errortime_y = $time;\n\t\t\tstats1.errors_y = stats1.errors_y+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector4", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput [31:0] out\n);\n", "canonical_solution": "\n\tassign out = { {24{in[7]}}, in };\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput [31:0] out\n);\n\n\tassign out = { {24{in[7]}}, in };\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [31:0] out_ref;\n\tlogic [31:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector5", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n", "canonical_solution": "\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d, e\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic e;\n\tlogic [24:0] out_ref;\n\tlogic [24:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vector5", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n", "canonical_solution": "\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\tinput e,\n\toutput [24:0] out\n);\n\n\tassign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c, d, e\n);\n\n\tinitial begin\n\t\trepeat(100) @(posedge clk, negedge clk)\n\t\t\t{a,b,c,d,e} <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic e;\n\tlogic [24:0] out_ref;\n\tlogic [24:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.e,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vectorgates", "prompt": "module top_module(\n\tinput [2:0] a, \n\tinput [2:0] b, \n\toutput [2:0] out_or_bitwise,\n\toutput out_or_logical,\n\toutput [5:0] out_not\n);\n", "canonical_solution": "\t\n\tassign out_or_bitwise = a | b;\n\tassign out_or_logical = a || b;\n\tassign out_not = {~b,~a};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\tinput [2:0] a, \n\tinput [2:0] b, \n\toutput [2:0] out_or_bitwise,\n\toutput out_or_logical,\n\toutput [5:0] out_not\n);\n\t\n\tassign out_or_bitwise = a | b;\n\tassign out_or_logical = a || b;\n\tassign out_not = {~b,~a};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg [2:0] a, b,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\tint count; count = 6'h38;\n\t\t{b, a} <= 6'b0;\n\t\t@(negedge clk);\n\t\twavedrom_start();\n\t\trepeat(30) @(posedge clk)\n\t\t\t{b, a} <= count++;\t\t\n\t\twavedrom_stop();\n\t\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\t{b,a} <= $random;\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out_or_bitwise;\n\t\tint errortime_out_or_bitwise;\n\t\tint errors_out_or_logical;\n\t\tint errortime_out_or_logical;\n\t\tint errors_out_not;\n\t\tint errortime_out_not;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [2:0] a;\n\tlogic [2:0] b;\n\tlogic [2:0] out_or_bitwise_ref;\n\tlogic [2:0] out_or_bitwise_dut;\n\tlogic out_or_logical_ref;\n\tlogic out_or_logical_dut;\n\tlogic [5:0] out_not_ref;\n\tlogic [5:0] out_not_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_or_bitwise_ref,out_or_bitwise_dut,out_or_logical_ref,out_or_logical_dut,out_not_ref,out_not_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_or_bitwise(out_or_bitwise_ref),\n\t\t.out_or_logical(out_or_logical_ref),\n\t\t.out_not(out_not_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.out_or_bitwise(out_or_bitwise_dut),\n\t\t.out_or_logical(out_or_logical_dut),\n\t\t.out_not(out_not_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out_or_bitwise) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or_bitwise\", stats1.errors_out_or_bitwise, stats1.errortime_out_or_bitwise);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or_bitwise\");\n\t\tif (stats1.errors_out_or_logical) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_or_logical\", stats1.errors_out_or_logical, stats1.errortime_out_or_logical);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_or_logical\");\n\t\tif (stats1.errors_out_not) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_not\", stats1.errors_out_not, stats1.errortime_out_not);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_not\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } === ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ^ { out_or_bitwise_dut, out_or_logical_dut, out_not_dut } ^ { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_or_bitwise_ref !== ( out_or_bitwise_ref ^ out_or_bitwise_dut ^ out_or_bitwise_ref ))\n\t\tbegin if (stats1.errors_out_or_bitwise == 0) stats1.errortime_out_or_bitwise = $time;\n\t\t\tstats1.errors_out_or_bitwise = stats1.errors_out_or_bitwise+1'b1; end\n\t\tif (out_or_logical_ref !== ( out_or_logical_ref ^ out_or_logical_dut ^ out_or_logical_ref ))\n\t\tbegin if (stats1.errors_out_or_logical == 0) stats1.errortime_out_or_logical = $time;\n\t\t\tstats1.errors_out_or_logical = stats1.errors_out_or_logical+1'b1; end\n\t\tif (out_not_ref !== ( out_not_ref ^ out_not_dut ^ out_not_ref ))\n\t\tbegin if (stats1.errors_out_not == 0) stats1.errortime_out_not = $time;\n\t\t\tstats1.errors_out_not = stats1.errors_out_not+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vectorr", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n", "canonical_solution": "\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\t\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\t@(posedge clk) in <= 8'h2;\n\t\t\t@(posedge clk) in <= 8'h4;\n\t\t\t@(posedge clk) in <= 8'h8;\n\t\t\t@(posedge clk) in <= 8'h80;\n\t\t\t@(posedge clk) in <= 8'hc0;\n\t\t\t@(posedge clk) in <= 8'he0;\n\t\t\t@(posedge clk) in <= 8'hf0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "vectorr", "prompt": "module top_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n", "canonical_solution": "\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput [7:0] in,\n\toutput [7:0] out\n);\n\t\n\tassign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic [7:0] in,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\t\n\n\t\n\tinitial begin\n\t\tin <= 0;\n\t\t@(negedge clk) wavedrom_start();\n\t\t\t@(posedge clk) in <= 8'h1;\n\t\t\t@(posedge clk) in <= 8'h2;\n\t\t\t@(posedge clk) in <= 8'h4;\n\t\t\t@(posedge clk) in <= 8'h8;\n\t\t\t@(posedge clk) in <= 8'h80;\n\t\t\t@(posedge clk) in <= 8'hc0;\n\t\t\t@(posedge clk) in <= 8'he0;\n\t\t\t@(posedge clk) in <= 8'hf0;\n\t\t@(negedge clk) wavedrom_stop();\n\t\n\t\trepeat(200) @(posedge clk, negedge clk)\n\t\t\tin <= $random;\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic [7:0] in;\n\tlogic [7:0] out_ref;\n\tlogic [7:0] out_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.in );\n\treference_module good1 (\n\t\t.in,\n\t\t.out(out_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.in,\n\t\t.out(out_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire4", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\toutput w,\n\toutput x,\n\toutput y,\n\toutput z  );\n", "canonical_solution": "\t\n\tassign {w,x,y,z} = {a,b,b,c};\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\toutput w,\n\toutput x,\n\toutput y,\n\toutput z  );\n\t\n\tassign {w,x,y,z} = {a,b,b,c};\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput logic a, b, c,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\talways @(posedge clk, negedge clk)\n\t\t{a,b,c} <= $random;\n\t\n\tinitial begin\n\t\t@(negedge clk) wavedrom_start();\n\t\t\trepeat(8) @(posedge clk);\n\t\t@(negedge clk) wavedrom_stop();\n\t\trepeat(100) @(negedge clk);\n\t\t$finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_w;\n\t\tint errortime_w;\n\t\tint errors_x;\n\t\tint errortime_x;\n\t\tint errors_y;\n\t\tint errortime_y;\n\t\tint errors_z;\n\t\tint errortime_z;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic w_ref;\n\tlogic w_dut;\n\tlogic x_ref;\n\tlogic x_dut;\n\tlogic y_ref;\n\tlogic y_dut;\n\tlogic z_ref;\n\tlogic z_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.w(w_ref),\n\t\t.x(x_ref),\n\t\t.y(y_ref),\n\t\t.z(z_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.w(w_dut),\n\t\t.x(x_dut),\n\t\t.y(y_dut),\n\t\t.z(z_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_w) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"w\", stats1.errors_w, stats1.errortime_w);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"w\");\n\t\tif (stats1.errors_x) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"x\", stats1.errors_x, stats1.errortime_x);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"x\");\n\t\tif (stats1.errors_y) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"y\", stats1.errors_y, stats1.errortime_y);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"y\");\n\t\tif (stats1.errors_z) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"z\", stats1.errors_z, stats1.errortime_z);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"z\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (w_ref !== ( w_ref ^ w_dut ^ w_ref ))\n\t\tbegin if (stats1.errors_w == 0) stats1.errortime_w = $time;\n\t\t\tstats1.errors_w = stats1.errors_w+1'b1; end\n\t\tif (x_ref !== ( x_ref ^ x_dut ^ x_ref ))\n\t\tbegin if (stats1.errors_x == 0) stats1.errortime_x = $time;\n\t\t\tstats1.errors_x = stats1.errors_x+1'b1; end\n\t\tif (y_ref !== ( y_ref ^ y_dut ^ y_ref ))\n\t\tbegin if (stats1.errors_y == 0) stats1.errortime_y = $time;\n\t\t\tstats1.errors_y = stats1.errors_y+1'b1; end\n\t\tif (z_ref !== ( z_ref ^ z_dut ^ z_ref ))\n\t\tbegin if (stats1.errors_z == 0) stats1.errortime_z = $time;\n\t\t\tstats1.errors_z = stats1.errors_z+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire_decl", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n", "canonical_solution": "\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n// hdlbits_prop {len: 5}\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} = 4'h0;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Exhaustive test\");\n\t\trepeat(20) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= {d,c,b,a} + 1'b1;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{a,b,c,d} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_out_n;\n\t\tint errortime_out_n;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\tlogic out_n_ref;\n\tlogic out_n_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut,out_n_ref,out_n_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref),\n\t\t.out_n(out_n_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut),\n\t\t.out_n(out_n_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_out_n) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_n\", stats1.errors_out_n, stats1.errortime_out_n);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_n\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, out_n_ref } === ( { out_ref, out_n_ref } ^ { out_dut, out_n_dut } ^ { out_ref, out_n_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (out_n_ref !== ( out_n_ref ^ out_n_dut ^ out_n_ref ))\n\t\tbegin if (stats1.errors_out_n == 0) stats1.errortime_out_n = $time;\n\t\t\tstats1.errors_out_n = stats1.errors_out_n+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "wire_decl", "prompt": "module top_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n", "canonical_solution": "\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\n// hdlbits_prop {len: 5}\nmodule reference_module (\n\tinput a,\n\tinput b,\n\tinput c,\n\tinput d,\n\toutput out,\n\toutput out_n );\n\t\n\twire w1, w2;\n\tassign w1 = a&b;\n\tassign w2 = c&d;\n\tassign out = w1|w2;\n\tassign out_n = ~out;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg a,b,c,d,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\t{a,b,c,d} = 4'h0;\n\t\t@(negedge clk);\n\t\twavedrom_start(\"Exhaustive test\");\n\t\trepeat(20) @(posedge clk, negedge clk)\n\t\t\t{d,c,b,a} <= {d,c,b,a} + 1'b1;\n\t\twavedrom_stop();\n\t\trepeat(100) @(posedge clk, negedge clk) begin\n\t\t\t{a,b,c,d} <= $random;\n\t\tend\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_out;\n\t\tint errortime_out;\n\t\tint errors_out_n;\n\t\tint errortime_out_n;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic a;\n\tlogic b;\n\tlogic c;\n\tlogic d;\n\tlogic out_ref;\n\tlogic out_dut;\n\tlogic out_n_ref;\n\tlogic out_n_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut,out_n_ref,out_n_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.* ,\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d );\n\treference_module good1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_ref),\n\t\t.out_n(out_n_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.a,\n\t\t.b,\n\t\t.c,\n\t\t.d,\n\t\t.out(out_dut),\n\t\t.out_n(out_n_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_out) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out\", stats1.errors_out, stats1.errortime_out);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out\");\n\t\tif (stats1.errors_out_n) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"out_n\", stats1.errors_out_n, stats1.errortime_out_n);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"out_n\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { out_ref, out_n_ref } === ( { out_ref, out_n_ref } ^ { out_dut, out_n_dut } ^ { out_ref, out_n_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (out_ref !== ( out_ref ^ out_dut ^ out_ref ))\n\t\tbegin if (stats1.errors_out == 0) stats1.errortime_out = $time;\n\t\t\tstats1.errors_out = stats1.errors_out+1'b1; end\n\t\tif (out_n_ref !== ( out_n_ref ^ out_n_dut ^ out_n_ref ))\n\t\tbegin if (stats1.errors_out_n == 0) stats1.errortime_out_n = $time;\n\t\t\tstats1.errors_out_n = stats1.errors_out_n+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "zero", "prompt": "module top_module(\n\toutput zero);\n", "canonical_solution": "\t\n\tassign zero = 1'b0;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput zero);\n\t\n\tassign zero = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should 0\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_zero;\n\t\tint errortime_zero;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic zero_ref;\n\tlogic zero_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.zero(zero_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.zero(zero_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_zero) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"zero\", stats1.errors_zero, stats1.errortime_zero);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"zero\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))\n\t\tbegin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;\n\t\t\tstats1.errors_zero = stats1.errors_zero+1'b1; end\n\n\tend\nendmodule\n"}
{"task_id": "zero", "prompt": "module top_module(\n\toutput zero);\n", "canonical_solution": "\t\n\tassign zero = 1'b0;\n\t\nendmodule\n", "test": "`timescale 1 ps/1 ps\n`define OK 12\n`define INCORRECT 13\nmodule reference_module(\n\toutput zero);\n\t\n\tassign zero = 1'b0;\n\t\nendmodule\n\n\nmodule stimulus_gen (\n\tinput clk,\n\toutput reg[511:0] wavedrom_title,\n\toutput reg wavedrom_enable\n);\n\n\n// Add two ports to module stimulus_gen:\n//    output [511:0] wavedrom_title\n//    output reg wavedrom_enable\n\n\ttask wavedrom_start(input[511:0] title = \"\");\n\tendtask\n\t\n\ttask wavedrom_stop;\n\t\t#1;\n\tendtask\t\n\n\n\n\tinitial begin\n\t\twavedrom_start(\"Output should 0\");\n\t\trepeat(20) @(posedge clk, negedge clk);\n\t\twavedrom_stop();\n\t\t\n\t\t#1 $finish;\n\tend\n\t\nendmodule\n\nmodule tb();\n\n\ttypedef struct packed {\n\t\tint errors;\n\t\tint errortime;\n\t\tint errors_zero;\n\t\tint errortime_zero;\n\n\t\tint clocks;\n\t} stats;\n\t\n\tstats stats1;\n\t\n\t\n\twire[511:0] wavedrom_title;\n\twire wavedrom_enable;\n\tint wavedrom_hide_after_time;\n\t\n\treg clk=0;\n\tinitial forever\n\t\t#5 clk = ~clk;\n\n\tlogic zero_ref;\n\tlogic zero_dut;\n\n\tinitial begin \n\t\t$dumpfile(\"wave.vcd\");\n\t\t$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );\n\tend\n\n\n\twire tb_match;\t\t// Verification\n\twire tb_mismatch = ~tb_match;\n\t\n\tstimulus_gen stim1 (\n\t\t.clk,\n\t\t.*  );\n\treference_module good1 (\n\t\t.zero(zero_ref) );\n\t\t\n\ttop_module top_module1 (\n\t\t.zero(zero_dut) );\n\n\t\n\tbit strobe = 0;\n\ttask wait_for_end_of_timestep;\n\t\trepeat(5) begin\n\t\t\tstrobe <= !strobe;  // Try to delay until the very end of the time step.\n\t\t\t@(strobe);\n\t\tend\n\tendtask\t\n\n\t\n\tfinal begin\n\t\tif (stats1.errors_zero) $display(\"Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.\", \"zero\", stats1.errors_zero, stats1.errortime_zero);\n\t\telse $display(\"Hint: Output '%s' has no mismatches.\", \"zero\");\n\n\t\t$display(\"Hint: Total mismatched samples is %1d out of %1d samples\\n\", stats1.errors, stats1.clocks);\n\t\t$display(\"Simulation finished at %0d ps\", $time);\n\t\t$display(\"Mismatches: %1d in %1d samples\", stats1.errors, stats1.clocks);\n\tend\n\t\n\t// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.\n\tassign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );\n\t// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute\n\t// the sensitivity list of the @(strobe) process, which isn't implemented.\n\talways @(posedge clk, negedge clk) begin\n\n\t\tstats1.clocks++;\n\t\tif (!tb_match) begin\n\t\t\tif (stats1.errors == 0) stats1.errortime = $time;\n\t\t\tstats1.errors++;\n\t\tend\n\t\tif (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))\n\t\tbegin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;\n\t\t\tstats1.errors_zero = stats1.errors_zero+1'b1; end\n\n\tend\nendmodule\n"}