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+{"text":"\\section{\n\\usepackage{amssymb}\n\\usepackage{graphicx}\n\\usepackage{wrapfig}\n\n\n\\usepackage{amssymb}\n\\usepackage{graphicx}\n\n\n\\author{G. Fejes T\\'oth}\n\\address{Alfr\\'ed R\\'enyi Institute of Mathematics,\nRe\\'altanoda u. 13-15., H-1053, Budapest, Hungary}\n\\email{gfejes@renyi.hu}\n\n\\title{Finite variations on the isoperimetric problem}\n\\thanks{The English translation of the book ``Lagerungen in der Ebene,\nauf der Kugel und im Raum\" by L\\'aszl\\'o Fejes T\\'oth will be\npublished by Springer in the book series Grundlehren der\nmathematischen Wissenschaften under the title\n``Lagerungen---Arrangements in the Plane, on the Sphere and\nin Space\". Besides detailed notes to the original text the\nEnglish edition contains eight self-contained new chapters\nsurveying topics related to the subject of the book but not\ncontained in it. This is a preprint of one of the new chapters.}\n\n\n\n\\begin{document}\n\n\n\n\n\\begin{abstract}\nThe isoperimetric problem asks for\nthe maximum area of a region of given perimeter. It is natural to consider\nother measurements of a region, such as the diameter and width,\nand ask for the extreme value of one when another\nis fixed. The solution of these problems is known if the competing regions\nare general convex disks, however several of these problems are still open\nif the competing regions are polygons with at most a given number of sides.\nThe present work surveys these problems.\n\n\n\\end{abstract}\n\n\\maketitle\n\n\n\nLet $a$, $p$, $w$, and $d$ denote the area, perimeter, width and diameter\nof a convex disk. Fixing one of these four quantities, what is the infimum\nand the supremum of another one of them? Of course, fixing one quantity and\nasking for the supremum of another one is equivalent to the problem of\nfixing the second quantity and asking for the infimum of the first one.\nThe solution of one half of the twelve problems arising this way is obvious:\nThe answer is either zero or infinity. In the case of the six meaningful\nproblems, we can ask for minima and maxima and for the convex disks\nattaining the optimum.\n\nThe isoperimetric problem asks for the convex disk of maximum area with\ngiven perimeter. Its solution is the circle, which was known already in\nAncient Greece, although a mathematically rigorous proof was obtained\nonly in the 19th century. The solution of the problem on the maximum\nwidth for a given diameter is obvious: The optimal sets are convex disks of\nconstant width. Convex disks of constant width were also characterized by\n{\\sc{Blaschke}} \\cite{Blaschke} as those among domains of a given width\nthat have minimum perimeter, and by {\\sc Rosenthal} and {\\sc Sz{\\'a}sz}\n\\cite{RosenthalSzasz} as those among  with a given diameter, that have\nmaximum perimeter. {\\sc{Bieberbach}} \\cite{Bieberbach} proved that among\nall domains of a fixed diameter the one of maximum area is the circular\ndisk, and {\\sc{P\\'al}} \\cite{Pal21} proved that the minimum area of a convex\ndisk with given width is attained by the regular triangle.\n\nAn interesting area of research is to consider these optimum problems\nrestricted to polygons with at most a given number of sides. The\nisoperimetric problem for $n$-gons was solved centuries ago by Zenodorus\n(see \\cite{Blasjo}): Implicitly assuming the existence of a solution, he\nproved that a regular $n$-gon has greater area than all other $n$-gons\nwith the same perimeter. This is expressed in the inequality\n$$p^2\\ge4na\\tan\\frac{\\pi}{n}.$$\nThe theorem of P\\'al solves the problem of minimum area for a given width.\nConcerning the remaining four problems only partial results are known.\n\n{\\sc Reinhardt} \\cite{Reinhardt} considered the problem of maximizing the perimeter\nof a convex $n$-gon with a given diameter and proved that the perimeter $p$ of an $n$-gon\nof diameter $d$ satisfies the inequality\n$$p\\le2n\\sin\\frac{\\pi}{2n}d.$$\nEquality is attained here if and only if $n$ is not a power of 2. This result, together\nwith the characterization of the case of equality, was rediscovered by {\\sc{Larman}} and\n{\\sc{Tamvakis}} \\cite{LarmanTamvakis}, {\\sc{Datta}} \\cite{Datta} and {\\sc{A.~Bezdek}}\nand {\\sc{Fodor}} \\cite{BezdekAFodor00}.\n\nTo describe the polygons for which equality is attained, we start with a convex polygon with an\nodd number of sides such that each vertex is at distance $d$ from the endpoints of the opposite\nside. Replacing each side by a circular arc of radius $d$ centered at the opposite vertex we\nobtain a Reuleaux polygon. If $n$ is not a power of 2, the $n$-gons of diameter $d$ with\nperimeter $2n\\sin(\\pi\/2n)$ are inscribed in a Reuleaux polygon in such a way that every vertex\nof the Reuleaux polygon is a vertex of the polygon, and all sides of the polygon are of equal\nlength. Such polygons are called by {\\sc{Audet}}, {\\sc{Hansen}} and {\\sc{Messine}}\n\\cite{AudetHansenMessine09a} {\\it clipped Reuleaux polygons}, while {\\sc{Mossinghoff}}\n\\cite{Mossinghoff11} uses the term {\\it{Reinhardt polygons}} for them.\n\n\\medskip\n\\centerline {\\immediate\\pdfximage width4cm\n{abb_144a.pdf}\\pdfrefximage \\pdflastximage\\hskip.5truecm\n\\immediate\\pdfximage width4cm\n{abb_144b.pdf}\\pdfrefximage \\pdflastximage}\n\\smallskip{\\centerline{Figure~1}\n\\medskip\n\nConsider a Reuleaux polygon with $m$ vertices. Its diagonals form an $m$-gon which for\n$m>3$ is a star polygon. The sum of the angles of this polygon is $\\pi$, so in order that\nit can accommodate a clipped Reuleaux polygon its angles must be integer multiples of $\\pi\/n$.\nThe clipped Reuleaux polygons were studied by {\\sc{Gashkov}} \\cite{Gashkov07,Gashkov13},\n{\\sc{Mossinghoff}} \\cite{Mossinghoff11} and {\\sc{Hare}} and  {\\sc{Mossinghoff}}\n\\cite{HareMossinghoff13,HareMossinghoff19}. For a given $n$, there are clipped Reuleaux\n$n$-gons with $k$-fold rotational symmetry for some divisor $k$ of $n$. Besides these,\ncalled {\\it{periodic}} by Mossinghoff, there may be some others, called {\\it{sporadic}}.\nThe latter name is misleading, since it turned out that the sporadic clipped Reuleaux\npolygons outnumber the periodic ones for almost all $n$. Figure~1 shows a regular and\na sporadic clipped Reuleaux polygon with 30 vertices.\n\nFinding the maximum perimeter of an $n$-gon of given diameter when $n$ is a power of 2\nis difficult. Only the cases of the quadrangle and octagon are solved. The best quadrangle was\ndetermined by {\\sc{Tamvakis}} \\cite{Tamvakis} and rediscovered by {\\sc{Datta}} \\cite{Datta}. The\noctagon's case was settled by {\\sc{Audet, Hansen}} and {\\sc{Messine}} \\cite{AudetHansenMessine07a}.\nTamvakis described a sequence of unit-diameter $n$-gons for $n=2^k$ whose perimeter exceeds that of\nthe regular $n$-gon, and differs from the upper bound $2n\\sin\\frac{\\pi}{2n}$ by $O(n^{-4})$.\nBy improved constructions the difference from the upper bound was reduced to $O(n^{-5})$ by\n{\\sc{Mossinghoff}} \\cite{Mossinghoff06a} and lately to $O(n^{-6})$ by {\\sc{Bingane}} \\cite{Bingane21a}.\n\nCombining the inequality $p\\le2n\\sin\\frac{\\pi}{2n}d$ with the isoperimertic inequality\n$p^2\\ge4n\\tan\\frac{\\pi}{n}a$, {\\sc Reinhardt} \\cite{Reinhardt} obtained the inequality\n$$a\\le\\frac{n}{2}\\cos\\frac{\\pi}{n}\\tan\\frac{\\pi}{2n}d^2$$\nwith equality only for odd $n$ and regular $n$-gons. Thus, for odd $n$, among all $n$-gons\nof a given diameter the regular one has maximum area. Alternative proofs were given by\n{\\sc{Lenz}} \\cite{Lenz56a}, {\\sc{Griffiths}} and {\\sc{Culpin}} \\cite{GriffithsCulpin}, and\n{\\sc{Gashkov}} \\cite{Gashkov85}.\n\nReinhardt proved that for even $n\\ge6$, the optimal $n$-gon is never regular. Alternative\nproofs were given by {\\sc{Sch\\\"affer}} \\cite{Schaffer}, {\\sc{Audet, Hansen}} and {\\sc{Messine}}\n\\cite{AudetHansenMessine08} and {\\sc{Mossinghoff}} \\cite{Mossinghoff06a}. The latter author\nconstructed a sequence of $n$-gons with unit diameter for even $n$ whose area exceeds the\narea of the unit-diameter regular $n$-gon by $O(n^{-2}$), and whose area differs from the\nmaximum area of such $n$-gons by a term of at most $O(n^{-3})$. {\\sc{Bingane}}\n\\cite{Bingane21b} improved {\\sc{Mossighoff}}'s construction without improving\non the order of difference from the maximum area.\n\nThe maximum area of a quadrangle of diameter $d$ is $d^2\/2$. The diagonals of the optimal\nquadrangles are perpendicular and have length $d$. The case\nof the hexagon was solved by {\\sc{Graham}} \\cite{Graham}. He confirmed the conjecture of\n{\\sc{Bieri}} \\cite{Bieri} that the non-regular hexagon shown in Figure 2 is the unique\noptimal solution. He also formulated a conjecture for all even $n\\ge6$, stating that for\nsuch $n$, every optimal $n$-gon's diameter graph consists of an ($n-1$)-cycle with one\nadditional edge emanating from one of the cycle's vertices. Note that the conjecture\nleaves the geometric realization of the best polygon undetermined, subject to an\noptimization problem. Graham's conjecture was confirmed for $n=8$ by {\\sc{Audet, Hansen,\nMessine}}, and {\\sc{Xiong}} \\cite{AudetHansenMessineXiong}, who also solved the\ncorresponding optimization problem, thus determining the best octagon. Subsequently,\nGraham's conjecture was confirmed in general by {\\sc Foster} and {\\sc{Szabo}}\n\\cite{FosterSzabo}. The corresponding optimal polygons for $n=10$ and $n=12$ were\ndetermined by {\\sc{Henrion}} and {\\sc{Messine}} \\cite{HenrionMessine}.\n\n\\medskip\n\\centerline {\\immediate\\pdfximage width4cm\n{abb_143.pdf}\\pdfrefximage \\pdflastximage}\n\\smallskip{\\centerline{Figure~2}}\n\\medskip\n\n{\\sc{Graham}} \\cite{Graham} also asked for the solution of the higher-dimensional analogue of\nthe problem: Which convex $d$-polytope with $n$ vertices and unit diameter has the largest volume?\nFor $n=d+1$ the solution is the regular simplex. {\\sc{Kind}} and {\\sc{Kleinschmidt}}\n\\cite{KindKleinschmidt76} solved the problem for $n=d+2$ and described all the extremal\npolytopes. The case $n=d+3$ was attacked by {\\sc{Klein}} and {\\sc{Wessler}} \\cite{KleinWessler03},\nhowever their proof turned out to be incomplete (cf. {\\sc{Klein}} and {\\sc{Wessler}}\n\\cite{KleinWessler05}), thus, this case is still open.\n\nIn the Russian journal for high school students Quant, {\\sc{Gashkov}} \\cite{Gashkov85} wrote\na small article about the isoperimetrtic problem and its relatives. There he gave a proof of\nReinhard's theorem based on central symmetrization. He used the following facts about\na convex $n$-gon $P$ and its central symmetric image $P^*=\\frac{1}{2}(P-P)$: $P^*$ is\na convex polygon with at most $m\\le2n$ sides and the same width $w$, diameter $d$ and\nperimeter $p$ as $P$. The inradius of $P^*$ is at least $w$ and the circumradius of\n$P^*$ is at least $d$. It follows that\n$$2m\\sin\\frac{\\pi}{2m}d\\ge{p}\\ge{m}\\tan\\frac{\\pi}{m}w.$$\nSince $m\\le2n$, using the monotonicity of the functions $x\\sin\\frac{1}{x}$ and\n$x\\tan\\frac{1}{x}$, we get, on one hand, Reinhardt's inequality for the maximum\nperimeter of an $n$-gon with given diameter, and on the other hand, the new inequality\n$$p\\ge{2n}\\tan\\frac{\\pi}{2n}w.$$\nThe combination of these inequalities yields the inequality\n$$w\\le\\cos\\frac{\\pi}{2n}d$$\nbetween the width and diameter of a convex $n$-gon. Equality is attained in these\ninequalities for every $n\\ge3$ that has an odd factor by a clipped Reuleaux polygon.\n\nGashkov's article remained unnoticed. The last inequality was rediscovered by\n{\\sc{A.~Bezdek}} and {\\sc{Fodor}} \\cite{BezdekAFodor00}, and the inequality between\nperimeter and width by {\\sc Audet}, {\\sc Hansen} and {\\sc Messine}\n\\cite{AudetHansenMessine09a}. These authors also solved the case of the quadrangle for\nboth problems. The octagon of a given diameter with maximum width was determined by\n{\\sc{Audet, Hansen, Messine}} and {\\sc{Ninin}} \\cite{AudetHansenMessineNinin}.\n\nMotivated by a question of Erd\\H{o}s, {\\sc{Vincze}} \\cite{Vincze} studied the problem of finding\nthe maximum perimeter of an equilateral $n$-gon with given diameter. He solved the problem if $n$ is\nnot a power of 2. Of course, this case is an immediate consequence of Reinhardt's theorem. However,\nVincze's argument works without the assumption that the sides have equal length, so it yields an\nalternative proof of Reinhardt's theorem. The case that $n$ is a power of $2>4$ is of similar difficulty\nas the problem for general $n$-gons. The only case solved is the one for the octagon settled by\n{\\sc{Audet, Hansen, Messine}} and {\\sc{Perron}} \\cite{AudetHansenMessinePerron}. {\\sc{Mossinghoff}}\n\\cite{Mossinghoff08} constructed a sequence of equilateral $n$-gons with unit diameter for $n=2^k$,\n$k\\ge4$, and proved that their perimeter differs from the maximum perimeter of such $n$-gons by\na term of at most $O(n^{-4})$. By constructing a differen sequence of polygons {\\sc{Bingane}} and\n{\\sc{Audet}} \\cite{BinganeAudet21a} further improved the lower bound for the optimum perimeter.\n\nThe question about the maximum area of an equilateral $n$-gon with given diameter $d$ is solved for\nall $n$: It is $\\frac{d^2n}{2}\\cos\\frac{\\pi}{n}\\tan\\frac{\\pi}{2n}$, attained only for a regular $n$-gon.\nThis follows from Reinhardt's theorem for odd $n$ and was proved by {\\sc{Audet}} \\cite{Audet17}\nfor even $n$. {\\sc{Bingane}} and {\\sc{Audet}} \\cite{BinganeAudet21b} determined the equilateral octagon of unit diameter\nwith maximum width. They also provided a family of equilateral $n$-gons of unit diameter, for $n=2^s$ with\n$s\\ge4$, whose widths are within $O(n^{-4})$ of the maximum width. It appears that the question about the\nmaximum width of an equilateral polygon with $n=2^k$ sides and a given perimeter has not been studied so far.\n\nBy restricting the class of competing polygons to equilateral polygons some problems with obvious\nsolutions become interesting. The area, perimeter, and diameter of a general unit-width convex $n$-gon\ncan be arbitrarily large. This is still the case for an equilateral polygon with an even number of sides.\nHowever, these quantities are bounded for equilateral convex $n$-gons when the number of sides is odd.\n{\\sc{Audet}} and {\\sc{Ninin}} \\cite{AudetNinin} determined the maximal perimeter, diameter and area\nof an equilateral unit-width convex $n$-gon for every odd $n\\ge3$. The optimal polygon is the same for\nall three problems: For $n=3$ it is an equilateral triangle of side length $\\frac{2}{\\sqrt3}$, and\nfor $n=2k+1\\ge5$ a trapezoid whose non-parallel sides have length equal to $\\frac{2}{\\sqrt3}$,\nand the parallel ones have length $m\\frac{2}{\\sqrt3}$ and $(m-1)\\frac{2}{\\sqrt3}$.\n\nThe papers by {\\sc{Mossinghoff}} \\cite{Mossinghoff06b} and {\\sc{Audet, Hansen}} and {\\sc{Messine}}\n\\cite{AudetHansenMessine07b,AudetHansenMessine09a} contain nice surveys about variations of the\nisoperimetric problem for polygons.\n\n\n\\small{\n","meta":{"redpajama_set_name":"RedPajamaArXiv"}}
+{"text":"\\section{\\label{sec:level1}Introduction}\n\nSpin Hall effect (SHE) can be used to produce a pure transverse spin current density ($J_{\\rm s}$) from a longitudinal electrical current density ($J_{\\rm e}$) in heavy metals.~\\cite{Dyakonov1971,Hirsch1999}  The pure spin current can be measured using the reciprocal effect, \\textit{i.e.}, the inverse spin Hall effect (ISHE) employing a transverse charge current created from the pure spin current. The spin current can generate a current-induced spin-orbit torque (SOT) in heavy metal\/ferromagnet (HM\/FM) heterostructure for potential application in the efficient manipulation of magnetization at the nanoscale.~\\cite{Liu2011,Liu2012}\nWith sufficiently strong SOT, it is possible to excite magnetization to auto-oscillation for radio frequency generation application~\\cite{Liu2012PRL,VEDemidov2012,Dhananjay2017} or switch the magnetization, move domain walls or skyrmions for efficient memory applications.~\\cite{Liu2012,Miron2014,Liu2012PRL,Debanjan2014} \n\nFor realizing these applications, a large spin Hall angle, $\\theta_{\\rm SH}$ defined as the ratio of the spin current density to the charge current density is desirable. While the value of $\\theta_{\\rm SH}$  in most commonly investigated metal Pt is $\\theta_{\\rm SH}\\leq~0.12$,~\\cite{Ando2008,Liu2011,Azevedo2011,sinova2015rmp}\nrecent results show relatively higher spin Hall angle of $|\\theta_{\\rm SH}| \\leq 0.25$ in Ta,\\cite{Morota2011, Liu2012,Hao2015,Allen2015,Kim2015,Nimi2015,Qiu2014,PDeorani2013,Hahn2013,Velez2016,Emori2013} and of the order of $|\\theta_{\\rm SH}|\\leq0.50$ for W.~\\cite{CFPai2012,Demasius2016Ncomm,Hao2015}\nHowever, these higher values of $\\theta_{\\rm SH}$ in Ta and W are so far reported in very high resistive phase of these materials, which limits several applications that require a charge current to flow in the HM. \n\n\nIn this work, we report a strong correlation of spin Hall angle with the crystalline phase of Ta thin films in Py\/Ta bilayers. The crystalline phase of Ta films is varied by controlling growth rate in sputtering. We develop and demonstrate a simple method for measurement of ISHE using a broadband ferromagnetic resonance (FMR) set-up without involving micro-fabrication. We show that the voltage measured in our optimized set-up primarily arises from ISHE by using out-of-plane angle dependence and radio frequency (RF) power dependence, which rules out voltage signal due to other galvanomagnetic effects such as anisotropic magneto-resistance (AMR) and anomalous Hall effect (AHE). We find a higher spin mixing conductance and spin Hall conductivity ($-2439~(\\hbar\/e)~\\Omega^{-1}$cm$^{-1}$) for \\textit{low resistivity} Ta having mixed crystalline phase, which is promising for applications. The large spin Hall conductivity for mixed crystalline phase Ta is consistent with the extrinsic mechanism of spin Hall effect.         \n\n\n\nThe Py($t_{\\rm Py}$ nm)\/Ta(20 nm) bilayer thin films are prepared on Si substrates using DC-magnetron sputtering at a working and base pressure of $2\\times10^{-3}$ and $3\\times10^{-6}$ Torr, respectively. We first studied single layer Ta thin films with different growth rates by varying the DC-sputtering power. Subsequently, Py($t_{\\rm Py}$ nm)\/Ta(20 nm) bilayer thin films were prepared with varying thickness of Py, $t_{\\rm Py}$ and growth rate of Ta. The Ta thickness was kept fixed at 20~nm. Before the deposition of the different layers, pre-sputtering of the targets was performed for 10 min with a shutter. Crystallographic properties of films were determined using X-ray diffraction (XRD) while the thicknesses and interface\/surface roughness were determined from X-ray reflectivity (XRR) technique using a PANalytical X'Pert diffractometer with Cu-K$_{\\alpha}$ radiation. \nThe  XRR data (not shown) was fitted using the recursive theory of Parratt.~\\cite{parratt1954}\nFrom XRR fitting the surface and interface roughness were found to be $<$0.5~nm.  \n\n\\begin{figure}[t]\n\\centering\n\\includegraphics[width=9cm]{1_v5.pdf}\\\\\n\\caption{(a) X-ray diffraction data for Ta thin films grown at different growth rates ($G_{R}$). The plots are shifted for clarity. The inset shows the resistivity versus $G_{R}$ for Ta thin films having thickness of 20~nm.}\\label{XRD_Ta}\n\\end{figure}\n\nFerromagnetic resonance (FMR) measurements are carried out for excitation frequencies of 4--12 GHz at room temperature. We use a co-planar waveguide (CPW) based broad-band FMR set-up.~\\cite{bansal2018apl}\nFor a fixed excitation frequency of microwave field, external magnetic field ($H$) is swept for the resonance condition. \nThe ISHE measurements are performed on $4\\times3~$mm$^{2}$ samples by measuring voltage signal at the edge of the samples by fabricating 100~$\\mu$m-thick Cu contact pads. This geometry allows us to measure ISHE signal in our samples when the film side is facing the CPW. \n\n\n\\begin{figure} [t!]\n\\centering\n  \\includegraphics[width=8.5cm]{2_FMR_v4.pdf}\\\\\n  \\caption{(a) Frequency ($f$) \\textit{vs.} resonance field ($H_{r}$) and (b) Linewidth ($\\Delta H$) vs. frequency, $f$ for Py (30 nm)\/Ta (20 nm) with varying phase of Ta obtained by varying the growth rates. The inset in (a) shows an example FMR spectra at 5 GHz for $G_{R}=0.62~\\rm \\AA$\/s. The symbols are measured data while solid lines are fits.}\\label{FMR}\n\\end{figure}\nFigure~\\ref{XRD_Ta} shows the XRD spectra for single layer 50~nm-thick Ta thin films prepared at different growth rates by varying sputtering power in DC magnetron sputtering. \nA broad diffusive peak of $\\alpha$-phase of Ta centered around 2$\\theta = 38.0^\\circ$ is observed for thin films grown at the lowest growth rate of 0.40~\\AA\/s. This peak corresponds to (110) reflection of $\\alpha-$Ta. Bragg peaks corresponding to (002) $\\beta$-Ta and (110) $\\alpha$-Ta are observed for growth rates between 0.62~\\AA\/s and 1.4~\\AA\/s, respectively, which suggest the growth of a mixed ($\\alpha$+$\\beta$) phase of Ta. However, an oriented $\\beta$-phase of Ta is observed for growth rate higher than 1.4 \\AA\/s with Bragg reflections at 2$\\theta$ = 33.6$^\\circ$ corresponding to $\\beta$-Ta (002) reflection. Inset of Fig.~\\ref{XRD_Ta} shows the resistivity measurements on 20 nm Ta thin films grown with varying growth rate, measured using Van der Pauw method. The samples with pure $\\beta$-phase of Ta shows a higher resistivity of about 180~$\\mu\\Omega$--cm which is in agreement with literature.~\\cite{Liu2012}\nFor the $\\alpha$-phase the resistivity is found to be around 60~$\\mu\\Omega$--cm. \n\n\nThe measured FMR data are shown in Fig.~\\ref{FMR} for Py(30~nm)\/Ta(20~nm) bilayer structure, where Ta is grown at a growth rate of 0.62 $\\rm \\AA$\/s at which a mixed ($\\alpha$+$\\beta$) phase of Ta is formed. The raw FMR spectra are fitted with the sum of derivative of symmetric and asymmetric Lorentzian functions:~\\cite{Woltersdorf2004}  \n\n\\begin{equation}\\label{Vdc}\n\\begin{split}\nV_{\\rm dc}= -2V_{\\rm sym} \\frac{\\Delta H^{2} \\small(H-H_{\\rm r})}{(\\Delta H^2+\\small(H-H_{\\rm r})^2)^2}\\\\+V_{\\rm asym} \\frac{ \\Delta H\\small(\\Delta H^2 -\\small(H-H_{\\rm r})^2)}{(\\Delta H^2+\\small(H-H_{\\rm r})^2)^2},\n\\end{split}\n\\end{equation}\n\nwhere $H$, $\\Delta H$, and $H_{\\rm r}$ are the measured field, FMR linewidth (half width at half maximum; HWHM) and resonance field, respectively.  $V_{\\rm sym}$ and $V_{\\rm asym}$ are the symmetric and asymmetric amplitudes of the voltage signal, respectively.  An example of FMR spectra with the fitting is shown in the inset of Fig.~\\ref{FMR}(a).\n\nFrom the fittings of FMR spectra, the linewidth $(\\Delta H)$ and the resonance field ($H_{\\rm r}$) are determined. The $H_{\\rm r}$ as a function of frequency ($\\it f$) is shown in Fig.~\\ref{FMR}(a), which was fitted with Kittel equation:~\\cite{Kittle1948}\n\\begin{equation}\\label{Kittel}\nf=\\frac{\\gamma}{2\\pi}[(H_{\\rm r}+H_{\\rm k})(H_{\\rm r}+H_{\\rm k}+4\\pi M_{\\rm eff})]^{1\/2},\n\\end{equation}\n \nwhere, $M_{\\rm eff}$ is the effective saturation magnetization and $H_{\\rm k}$ is the anisotropy field. Here, $\\gamma$=1.85$\\times10^{2}$~GHz\/T is the gyromagnetic ratio. \n\nThe Gilbert damping parameter, $\\alpha $ was calculated from the slope of the $\\Delta H$ vs. $f$ [Fig.~\\ref{FMR}(b)] by fitting with following equation:\n\\begin{equation}\\label{eq;deltah}\n\\Delta H=\\frac{2\\pi\\alpha_{\\rm eff} f}{\\gamma}+\\Delta H_{\\rm 0},\n\\end{equation}\n where $\\Delta H_{\\rm 0}$ is inhomogeneous line broadening, which is related with the film quality. In our experimental results [Fig.~\\ref{FMR}(b)], the $\\Delta H$ vs. $f$ shows a linear behavior indicating the intrinsic origin of damping parameter observed in our Py\/Ta bilayers thin films. We have also observed very small value of $\\Delta H_{\\rm 0}$ ($< 1$~mT), which further confirms the high-quality of these thin films. For quantifying spin pumping for different Ta crystalline phase, we have performed Py thickness dependence of $\\alpha_{\\rm eff}$ and $M_{\\rm eff}$ for varying crystalline phase of Ta. Figure~\\ref{SMC}(a) shows damping parameter vs. inverse of Py thickness for the different crystalline phase of Ta thin films.  We then calculate the spin mixing conductance, $\\mathrm{g}_{\\uparrow \\downarrow}$ which is an important parameter that determines the spin pumping efficiency. According to the theory of spin pumping,~\\cite{Tserkvovyak2002}  \n\\begin{equation}\\label{eq:spump}\n\\alpha_{\\rm eff} = \\alpha_{0}+g\\mu_{0}\\mu_{B}\\frac{\\textsl{g}_{\\uparrow\\downarrow}}{4\\pi M_{\\rm s}}\\frac{1}{t_{\\rm FM}},\n\\end{equation}\n\nwhere, $g$ and $\\mu_{B}$ are Land\\'e $g$-factor and Bohr magneton, respectively. We have calculated $\\mathrm{g}_{\\uparrow \\downarrow}$ by fitting Gilbert damping parameter $(\\alpha_{\\rm eff})$ versus inverse of Py thickness with above equation as shown in Fig.~\\ref{SMC}(a). We used $g=2.1$ for Ni$_{80}$Fe$_{20}$ for calculating $\\textsl{g}_{\\uparrow\\downarrow}.$~\\cite{Shaw2013} In Eq~(\\ref{eq:spump}), we neglected the spin back flow, since the Ta thickness we used is quite large compared to reported spin diffusion length of Ta.~\\cite{Liu2012,Emori2013,Wang2014,Kim2015,Allen2015,Nilamani2016} \n\n\\begin{figure}[t]\n\\centering\n  \\includegraphics[width=8.5cm]{3_SHC.pdf}\\\\\n  \\caption{(a) Effective damping constant ($\\alpha_{\\rm eff}$) vs. inverse of Py thickness, for different crystalline phases of Ta. (b) Variation of $\\mathrm{g}_{\\uparrow \\downarrow}$ with growth rate $G_{\\rm R}$ of Ta.}\\label{SMC}\n\\end{figure}\n\n\nFigure~\\ref{SMC}(b) shows the value of $\\textsl{g} _{\\uparrow\\downarrow}$ with varying growth rate of Ta thin films. Interestingly, the highest value of $\\textsl{g} _{\\uparrow\\downarrow}$ is observed for the mixed phase of Ta. In a recent study, we showed that the spin current efficiency is maximum for the mixed phase Ta using an optical technique.~\\cite{Rajni2017} Thus, the higher value of $\\textsl{g} _{\\uparrow\\downarrow}$ for mixed phase Ta is consistent with this earlier study. The spin mixing conductance,  $\\textsl{g} _{\\uparrow\\downarrow}$ determines the amount of spin current injected to the non-magnetic Ta layer. A variation of $\\textsl{g} _{\\uparrow\\downarrow}$ with crystalline phase, imply a change of effective spin current injected to the Ta layer. Hence, a correlation between $\\textsl{g} _{\\uparrow\\downarrow}$ and the inverse spin Hall voltage is expected.\nFor this, we measured ISHE in these bilayers as a function of the crystalline phase of Ta thin films. The upper panel in Fig.~\\ref{ISHE}(a) shows an example of ISHE voltage signal observed for the Py\/Ta thin film for the growth rate of 0.62 $\\rm \\AA$\/s. \n\nIn our measurement, we have used a field-modulation method to enhance the sensitivity.~\\cite{tiwari2016apl} In this method, the static field is modulated with a small ac field (98~Hz) of magnitude 0.5~mT, produced by a pair of Helmholtz coils. These coils are powered by the lock-in amplifier, which also measures the voltage across the sample.\nThus, the field modulation method measures essentially the derivative signal. However, the most reported literature on ISHE uses amplitude modulation of RF signal.~\\cite{Mosendz2010,Mosendz2010PRL,Ando2011,PDeorani2013,Surbhi2017}\nHence, in the lower panel of Fig.~\\ref{ISHE}(a), we show the integrated ISHE signal for better comparison with the literature. The measured signal in our system may consist of ISHE in the Ta layer, and the AMR or AHE of the Py layer. The AMR or AHE is often assumed to produce an asymmetric Lorentzian shape  while the ISHE is assumed to produce a symmetric Lorentzian shape~\\cite{Mosendz2010PRL,Ando2011,Ando2012NC,Bai2013PRL,Iguchi2017} \nso that the measured data is a sum of symmetric and asymmetric Lorentzian functions. Our measured ISHE spectra are symmetric in shape and changes sign with inversion of magnetic field direction which indicates that the voltage signal we measure may be primarily due to ISHE.~\\cite{Mosendz2010,Mosendz2010PRL,Ando2011,PDeorani2013}\n\n\\begin{figure}[t]\n  \\includegraphics[width=9cm]{4_ISHE_v1.pdf}\\\\\n  \\caption{(a) Measured and integrated ISHE signal at 3 GHz, for Py(30 nm)\/Ta(20 nm) with $G_{\\rm R}=0.62~\\AA$\/s. The inset shows the schematic of the ISHE voltage measurement geometry. (b) Out-of plane ($\\theta_{H}$) ISHE measurements with magnetic field applied out-of the film plane for 2~GHz of excitation frequency at  RF power of 15.85~mW. Inset shows $V_{\\rm sym}$ versus $P_{\\rm RF}$ for 3~GHz. The solid line is a linear fit.}\\label{ISHE}\n\\end{figure}\n\n\nTo further verify that the measured signal is indeed from the ISHE, we measured the voltage in our samples by changing the direction of magnetic field out-of-the film plane. The measurement geometry is shown in the inset of Fig.~\\ref{ISHE}(a). Here, the out-of-plane angle ($\\theta_{\\rm H}$) is measured from the \\textit{z}-axis, so that $\\theta_{H}=0^\\circ$ corresponds to the out-of-plane direction. Figure~\\ref{ISHE}(b) shows the variation of symmetric and asymmetric voltage components with varying $\\theta_{\\rm H}$. According to Lustikova \\textit{et. al.}, the asymmetric component ($V_{\\rm asym}$) can arise due to the AMR and AHE while the symmetric component ($V_{\\rm sym}$) arises due to ISHE, as well as AMR and AHE.~\\cite{Lustikova2015} \nIn our measurements, we found $V_{\\rm asym}<<V_{\\rm sym}$ for the entire range of $\\theta_{H}$. Also, the observed angular dependence of $V_{\\rm asym}$ is not analogous to the analysis presented by Lustikova \\textit{et al.}.~\\cite{Lustikova2015}\nThis indicates that the voltage signal measured in our set-up is primarily due to the ISHE. Furthermore, the $V_{\\rm sym}$ increases linearly with radio frequency(RF) power as shown in the inset of Fig.~\\ref{ISHE}(b), which is also consistent with ISHE.~\\cite{Ando2011}\n\n\n\nBased on the above observations, we took the symmetric signal as ISHE ($V_{\\rm sym} = V_{\\rm ISHE}$) for calculating the spin Hall angle ($\\theta_{\\rm SH}$) of Ta. The spin Hall angle relates to the ISHE voltage in the following manner:~\\cite{Ando2010,Mosendz2010,PDeorani2013,Wang2014,Surbhi2017}\n\\begin{equation}\\label{VISHE}\nV_{\\rm ISHE}=\\zeta \\theta_{\\rm SH}LR\\lambda_{\\rm Ta}\\tanh\\left( \\frac{d_{\\rm Ta}}{2\\lambda_{\\rm Ta}}\\right)\\times J^0_{\\rm s}\n\\end{equation}\n \nwhere, $V_{\\rm ISHE}$ is the ISHE signal induced by spin pumping, $R$ is the sample resistance measured from Py\/Ta samples, $L$ is the length of the sample, $d_{\\rm Ta}$ and $\\lambda_{\\rm Ta}$ are thickness and spin diffusion length of Ta thin film, respectively. The spin diffusion length of Ta thin films is taken to be 2.47~nm measured in similar bilayer structures.~\\cite{Nilamani2016} As a first approximation, we neglect the possible variation of $\\lambda_{\\rm Ta}$  with the crystalline phase of Ta. This assumption is very much valid in our case as the thickness of Ta is very large compared to the reported values of the spin diffusion length of Ta, which is of the order of 0.4--3~nm~\\cite{Liu2012,Emori2013,Wang2014,Kim2015,liu2015apl, Allen2015,Nilamani2016,beherarsca2017} so that $\\tanh\\left( \\frac{d_{\\rm Ta}}{2\\lambda_{\\rm Ta}}\\right)\\approx 1$ in the above equation.\nThe spin back flow is also negligible for the same reason \\textit{i.e.,}  $d_{\\rm Ta} \\gg \\lambda_{\\rm Ta}$. \n$\\zeta$ is the correction factor and comes from the fact that only a part of the sample contributes to the spin pumping and it depends upon the area of the sample above the signal line of CPW. The value of $\\zeta$ can be calculated using the method discussed by P. Deorani \\textit{et al.}~\\cite{PDeorani2013} by noting that the width ($w$) of signal line is 185~$\\mu m$ wide and distance between contact pads is 2~mm and spin wave propagation length of Ta is about 25 $\\mu m$.~\\cite{Kwon2013}\n\n$J^0_{\\rm S}$ is spin current density and can be defined as,\n\\begin{equation}\\label{Js}\nJ^0_{\\rm s}=\\frac{2e}{\\hbar}\\times\\frac{\\hbar\\omega}{4\\pi} Re(\\mathsf{g_{\\uparrow\\downarrow}}) \\sin^2\\theta_{\\rm C}\\times P, \n\\end{equation}\n\nwhere, $\\omega=2\\pi f$ is the angular frequency of microwave excitation, $Re(\\mathsf{g_{\\uparrow\\downarrow}})$ is real part spin mixing conductance. $\\theta_{\\rm C}$ is the magnetization precession cone angle given by $\\theta_{\\rm C}=\\frac{h_{\\rm rf}}{2\\Delta H}$, where $h_{\\rm rf}$ is the strength of RF field experienced by the sample. This field is generated around the signal line as a result of RF current flow. The value of $h_{\\rm rf}$ is obtained from Ampere's law, $h_{\\rm rf} = \\frac{\\mu_{\\rm 0}}{2\\pi w} \\sqrt[]{\\frac{P_{\\rm RF}}{Z}}\\log(1+\\frac{w}{D})$, where $w$ and $D$ is the width of signal line and separation between signal line to sample (0.5 mm), $P_{\\rm RF}$ is the applied RF power and $Z$ is the impedance of CPW \\textit{i.e.,} 50~$\\Omega$. $P$ is the ellipticity correction factor and arises from the ellipticity of the magnetization precession. As the magnetization precession in a magnetic thin film is not exactly circular, but follows an elliptical path due to strong demagnetizing fields. According to Ando \\textit{et al.}\\cite{Ando2009}, $P$  is given by,\n\n\\begin{equation}\\label{P}\nP= \\frac{2\\omega[M\\gamma+\\sqrt(M\\gamma)^2+(2\\omega)^2]}{(M\\gamma)^2+(2\\omega)^2}\n\\end{equation}\n\nwhere, $M=4\\pi M_{\\rm s}$. As explained by Mosendz \\textit{et al.}\\cite{Mosendz2010}, the value of ellipticity correction factor $P$ changes by a multiple of more than 3 for frequency range 2 to 8 GHz and becomes larger than 1 for frequencies higher than 10 GHz. This shows that magnetization precession trajectory is very elliptical for lower frequencies and DC voltage due to ISHE requires this correction factor. \n\\begin{figure}[t]\n\\centering  \\includegraphics[width=8.5cm]{5_SHA.pdf}\\\\\n\\caption{(a) Measured Spin Hall angle ($\\theta_{\\rm SH}$) versus growth rate, $G_{R}$ of Ta for the Py (30 nm)\/Ta (20 nm) bilayer thin films at 3 GHz FMR frequency. (b) Spin Hall conductivity ($\\sigma_{\\rm SH}$) as a function of resistivity ($\\rho$) of Ta thin films.}\\label{SHA}\n\\end{figure}\nAfter considering all the required terms, the value of the spin Hall angle of the Ta thin films can be calculated using Eq.~(\\ref{VISHE}).\n\nWe found the sign of spin Hall angle to be negative, which was confirmed by measuring a Py\/Pt sample (not shown) for which the sign was found positive which is consistent with the literature. \nFigure~\\ref{SHA} shows the variation of spin Hall angle with varying growth rate of Ta, measured at 3 GHz.  The results show a strong correlation between the spin Hall angle and crystalline phase of Ta. Furthermore, the behavior of spin Hall angle is similar to the variation of spin mixing conductance shown in Fig.~\\ref{SMC}(b) indicating a strong correlation between the spin-mixing conductance and the inverse spin Hall effect. This correlation further confirms that spin rectification effects are negligible in our measurement, unlike a recent study where spin-mixing conductance and the inverse spin Hall effect were found to be uncorrelated due to the presence of spin rectification effects.~\\cite{conca2017prb} \n\nSurprisingly,  it is observed that the low-resistivity Ta thin films with mixed phase show the highest value of spin Hall angle, $-0.16\\pm 0.01$. The highest value of spin Hall angle reported in the literature for Ta is $-0.25$, which was for the high resistive $\\beta$-phase of Ta.~\\cite{Emori2013} In our case, we observed a lower spin Hall angle of $\\theta_{\\rm SH}\\approx-0.02$ for the high resistive $\\beta$-phase of Ta. We calculate the spin Hall conductivity, $\\sigma_{\\rm SH}$ using the following formula: \n\\begin{equation}\\label{Js}\n\\sigma_{\\rm SH}=\\theta_{\\rm SH}\\times \\sigma \\frac{\\hbar}{e}, \n\\end{equation}\n\nwhere, $\\sigma$ is the charge conductivity of the Ta thin films. We found the spin Hall conductivity, $\\sigma_{\\rm SH}$ to be around -2439~$(\\hbar\/e)~\\Omega^{-1}$cm$^{-1}$ for low-resistivity Ta having mixed crystalline phase for the sample grown at a growth rate of 0.62 $\\rm \\AA$\/s.\nTo our knowledge, no theoretical calculation exists for the polycrystalline mixed phase Ta films. \nHowever, first principle calculation show that the \\textit{intrinsic} spin Hall conductivity of $\\beta-$Ta is $-378~(\\hbar\/e)~\\Omega^{-1}$cm$^{-1}$, while that of  $\\alpha-$Ta is $-103~(\\hbar\/e)~\\Omega^{-1}$cm$^{-1}$.~\\cite{qu2018prb} Hence, the significantly higher value of $\\sigma_{\\rm SH}$ , that we obtain for the mixed phase Ta is likely caused by extrinsic mechanism.  The intrinsic and extrinsic contributions to the spin Hall\nconductivity can be written in the following manner:\\cite{tian2009prl,isasa2015prb,ramaswamypra2017,sagasta2018arXiv}\n\n\\begin{equation}\\label{eq:scale}\n\\sigma_{\\rm SH}=\\sigma_{\\rm SH}^{\\rm int}+ \\frac{\\sigma_{\\rm SH}^{\\rm sj}\\rho_{\\rm Ta, 0}^{2}+\\alpha_{ss}\\rho_{\\rm Ta, 0}}{\\rho_{\\rm Ta}^{2}},\n\\end{equation}\nwhere, $\\sigma_{\\rm SH}^{\\rm int}$ is intrinsic spin Hall conductivity, $\\sigma_{\\rm SH}^{\\rm sj}$ is the spin Hall conductivity due to side jump mechanism, $\\alpha_{ss}$ is the skew scattering angle and $\\rho_{\\rm Ta}$ is the longitudinal resistivity of Ta at room temperature, and $\\rho_{\\rm Ta, 0}$ is the residual resistivity of Ta. In Fig.~\\ref{SHA}(b), we plot the measured $|\\sigma_{\\rm SH}|$ versus $\\rho_{\\rm Ta}$. The figure shows a strong dependence of $\\sigma_{\\rm SH}$  with $\\rho_{\\rm Ta}$ indicating that the $\\sigma_{\\rm SH}$ in these films is influenced by both the intrinsic and extrinsic contributions. In particular, for the mixed phase Ta films, $\\sigma_{\\rm SH}$ increases when $\\rho_{\\rm Ta}$ decreases as predicted by Eq.~(\\ref{eq:scale}).  Assuming that $\\rho_{\\rm Ta, 0}$ is independent of crystalline phase, we expect $\\sigma_{\\rm SH} \\propto 1\/\\rho_{\\rm Ta}^{2}$, which is shown by the dashed line. The experimental behavior nearly follows this dependence except for the  $\\alpha-$phase Ta. Thus, from Fig.~\\ref{SHA} (b) one can conclude that the large spin Hall conductivity in the mixed phase Ta films is due to the extrinsic mechanism of spin Hall effect. Though a more detailed microscopic examination of samples is needed to find the exact origin of defects in the mixed phase Ta, the results do support the extrinsic mechanism of spin Hall effect in the Ta thin films. \n\n\n\nIn summary, we have measured inverse spin Hall voltage (ISHE) in Py\/Ta system by varying the crystalline phase of Ta using a co-planar wave-guide based broadband ferromagnetic resonance set-up. We demonstrate a strong correlation of measured spin mixing conductance and spin Hall conductivity with the crystalline phase of Ta thin films. We found a large spin Hall conductivity of $-2439~(\\hbar\/e)~\\Omega^{-1}$cm$^{-1}$ for low-resistivity (68~$\\mu\\Omega$--cm) Ta having mixed crystalline phase, due to the extrinsic mechanism of spin Hall effect. The study is useful for the efficient manipulation of magnetization at the nanoscale as well as for explaining the spread in the values of spin Hall angle of Ta in literature.\n\nThe partial support from the Ministry of Human Resource Development under the IMPRINT program, the Department of Electronics and Information Technology (DeitY), and Department of Science and Technology under the Nanomission program are gratefully acknowledged. \nA.~K. acknowledges support from Council of Scientific and Industrial Research (CSIR), India.\n\n\n\n","meta":{"redpajama_set_name":"RedPajamaArXiv"}}
+{"text":"\n\n\\section{Summary and Outlook}\n\\label{sec:conclusions}\nIn this paper, we have presented an open source math library featuring a DPC++ backend to execute on Intel GPUs. We elaborated on the porting effort and the workarounds we implemented to enable DPC++ support. We also evaluated the raw performance of different Intel GPU generations and investigated how this raw performance translates into the developed basic sparse linear algebra operations and sparse iterative solvers. The performance analysis revealed that DPC++ allows to achieve high efficiency in terms of translating raw performance into mathematical algorithms. The portability analysis shows \\textsc{Ginkgo's}\\xspace performance portability on modern HPC platforms. Future work will focus on running the platform-portable DPC++ kernels on AMD GPUs and NVIDIA GPUs and compare the kernel performance with the performance of kernels written in the vendor-specific programming languages HIP and CUDA, respectively. We failed to include the work in this paper as at the time of writing, platform portability of DPC++ is not yet enabled.\n\\section{The oneAPI Programming Ecosystem}\n\\label{sec:dpcpp}\n\noneAPI\\footnote{\\url{https:\/\/spec.oneApi.com\/versions\/latest\/index.html}} is an open and free programming ecosystem which aims at providing portability across a wide range of hardware platforms from different architecture generations and vendors. The oneAPI software stack is structured with the new DPC++ programming language at its core, accompanied by several libraries to ease parallel application programming.\n\nDPC++ is a community-driven (open-source) language based on on the ISO C++ and Khronos' SYCL standards. The concept of DPC++ is to enhance the SYCL~\\cite{sycl} ecosystem with several additions that aim at improving the performance on modern hardware, improving usability, and simplifying the porting of classical CUDA code to the DPC++ language. Compared to SYCL, two relevant features of the DPC++ ecosystem are\\footnote{Both extensions are now also part of the SYCL 2020 Provisional Specification: \\url{https:\/\/www.khronos.org\/news\/press\/khronos-releases-sycl-2020-provisional-specification}}: 1) DPC++ introduces a new subgroup concept which can be used inside kernels. This concept is equivalent to CUDA subwarps (or SIMD on CPUs) and allows optimized routines such as subgroup based shuffles. In the \\textsc{Ginkgo}\\xspace library, we make extensive use of this capability to boost the performance. 2) DPC++ adds a new Unified Shared Memory (USM) model which provides new \\texttt{malloc\\_host} and \\texttt{malloc\\_device} operations to allocate memory which can either be accessed both by host or device, or respectively accessed by a device only. Additionally, the new SYCL \\texttt{queue} extensions\nfacilitate the porting of CUDA code as well as memory control. Indeed, in pure SYCL, memory copies are entirely asynchronous and hidden from the user, since the SYCL programming model is based on tasking with automatic discovery of task dependencies.\n\nAnother important aspect of oneAPI and DPC++ is that they adopt platform portability as the central design concept. Already the fact that DPC++ is based on SYCL (which leverages the OpenCL's runtime and SPIRV's intermediate kernel representation) provides portability to a variety of hardware. On top of this, DPC++ develops a plugin API which allows to develop new backends and switch dynamically between them\\footnote{\\url{https:\/\/intel.github.io\/llvm-docs\/PluginInterface.html}}.\nCurrently, DPC++ supports the standard OpenCL backend, a new Level Zero backend which is the backend of choice for Intel hardware\\footnote{\\url{https:\/\/spec.oneApi.com\/level-zero\/latest\/core\/INTRO.html}}, and an experimental CUDA backend for targeting CUDA-enabled GPUs. As our goal is to provide high performance sparse linear algebra functionality on Intel GPUs, we focus on the Intel Level Zero backend of DPC++.\n\n\n\\begin{figure}[!t]\n\\begin{center}\n\\lstinputlisting[language=C,caption={Small example of a SYCL\/DPC++ code with a dummy kernel.},label={code:dpcppsample},morekeywords={submit, memcpy, malloc_device}]{code\/sample_sycl.cpp}\n\\end{center}\n\\label{fig:dpcppsample}\n\\end{figure}\n\n\nIn Listing~\\ref{code:dpcppsample}, we show a minimal example of a SYCL\/DPC++ code in a classical use case. In line 10-11, previously declared data is wrapped into a \\texttt{sycl::buffer} to enable automatic memory management. In this example, the \\texttt{sycl::queue} declared in line 14 automatically selects the execution hardware. In general, the hardware selection can also be controlled explicitly. In line 17-28, the submission of a kernel is controlled through a command group handler. This allows to define accessors for the data in lines 19 and 20. These accessors declare the data access policy of the previous buffers and allow the runtime to automatically infer which data transfers (host\/device) are required. Lines 22-27 contain the actual kernel declaration. The accessors are used to write to the previous buffers. \nTaking the C++ principles, at the end of the kernel, DPC++ automatically transfers the buffers back to the vectors A, B, destroys the buffers and synchronizes the queue. As a result, after kernel completion, the (modified) vectors A and B can again be accessed transparently, see lines 31-34.\n\\section{Experimental Performance Assessment}\n\\label{sec:experiments}\n\n\\subsection{Experiment Setup}\nIn this paper, we consider two Intel GPUs: the generation 9 (\\textsc{Gen9}\\xspace{}) integrated GPU UHD Graphics P630 with a theoretical bandwidth of 41.6~GB\/s\nand the generation 12 Intel\\textsuperscript{\\tiny\\textregistered} Iris\\textsuperscript{\\tiny\\textregistered} Xe Max discrete GPU (\\textsc{Gen12}\\xspace{})\\footnote{\\url{https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/211013\/intel-iris-xe-max-graphics-96-eu.html}} which features 96 execution units and a theoretical bandwidth of 68~GB\/s.\nTo better assess the performance of either GPUs, we include in our analysis the performance we can achieve in bandwidth tests, performance tests, and sparse linear algebra kernels. We note that the \\textsc{Gen12}\\xspace architecture lacks native support for IEEE 754 double precision arithmetic, and can only emulate double precision arithmetic. Obviously, emulating double precision arithmetic provides significantly lower performance. Given that native support for double precision arithmetic is expected for future Intel GPUs and using the double precision emulation would artificially degrade the performance results while not providing insight whether \\textsc{Ginkgo's}\\xspace algorithms are suitable for Intel GPUs, we use single precision arithmetic in the performance evaluation on the \\textsc{Gen12}\\xspace architecture\\footnote{\\textsc{Ginkgo}\\xspace is designed to compile for IEEE 754 double precision arithmetic, single precision arithmetic, double precision complex arithmetic, and single precision complex arithmetic.}.\nThe DPC++ version we use in all experiments is Intel oneAPI DPC++ Compiler 2021.1 (2020.10.0.1113).  All experiments were conducted on hardware that is part of the Intel DevCloud.\n\n\\begin{figure}[!h\n    \\centering\n \\begin{tabular}{lr}\n  \\includegraphics[width=.45\\columnwidth]{plots\/intel_gen9_neo_bandwidth.pdf}\n  &\n  \\includegraphics[width=.45\\columnwidth]{plots\/gen12lp_halfsize_bandwidth.pdf}\n  \\end{tabular}\n    \\caption{Performance evaluation of the Intel GPUs using the BabelStream benchmark. The bandwidth analysis on the \\textsc{Gen9}\\xspace architecture (left) uses IEEE 754 double precision values, the bandwidth analysis on the \\textsc{Gen12}\\xspace architecture (right) uses IEEE 754 single precision values.}\n    \\label{fig:babelstream}\n\\end{figure}\n\n\n\\begin{figure}[!h\n    \\centering\n     \\begin{tabular}{lr}\n  \\includegraphics[width=.45\\columnwidth]{plots\/gen9_flops.pdf}\n  &\n  \\includegraphics[width=.45\\columnwidth]{plots\/gen12lp_gflops_ro.pdf}\n  \\end{tabular}\n    \\caption{Experimental performance roofline of the Intel GPUs using the mixbench benchmark for the \\textsc{Gen9}\\xspace (left) and \\textsc{Gen12}\\xspace (right) GPUs.}\n    \\label{fig:roofline}\n\\end{figure}\n\n\n\\subsection{Bandwidth Tests and Roofline Performance Model}\nInitially, we evaluate the two GPUs in terms of architecture-specific performance bounds. For that purpose, we use the BabelStream~\\cite{babelstream} benchmark to evaluate the peak bandwidth, and the mixbench~\\cite{mixbench} benchmark to evaluate the arithmetic performance in different precision formats and derive a roofline model~\\cite{roofline}.\nIn \\Cref{fig:babelstream} we visualize the bandwidth we achieve for different memory-intense operations. On both architectures, the {\\sc Dot} kernel requiring a global synchronization achieves lower bandwidth than the other kernels. We furthermore note that the \\textsc{Gen12}\\xspace architecture achieves for large array sizes about 58 GB\/s, which is about 1.6$\\times$ the \\textsc{Gen9}\\xspace bandwidth (37 GB\/s).\n\nIn \\Cref{fig:roofline} we visualize the experimental performance roofline for the two GPU architectures. The \\textsc{Gen9}\\xspace architecture achieves about 105 GFLOP\/s, 430 GFLOP\/s, and 810 GFLOP\/s for IEEE double precision, single precision, and half precision arithmetic, respectively. The \\textsc{Gen12}\\xspace architecture does not provide native support for IEEE double precision and the double precision emulation achieves only 8 GFLOP\/s, which is significantly below the \\textsc{Gen9}\\xspace performance. On the other hand, the \\textsc{Gen12}\\xspace architecture achieves 2.2 TFLOP\/s and 4.0 TFLOP\/s for single precision and half precision floating point operations.\n\n\n\n\\subsection{\\textsc{SpMV}\\xspace Performance Analysis}\n\n\n\\begin{figure}[!h\n    \\centering\n    \\subfloat[\\textsc{Gen9}\\xspace\\label{fig:spmvnine}\n    ]{\\includegraphics[width=.6\\columnwidth]{plots\/gen9_spmv.png}\n    }\\\\\n    \\subfloat[\\textsc{Gen12}\\xspace\\label{fig:spmvtwelve}\n    ]{\\includegraphics[width=.6\\columnwidth]{plots\/gen12lp_float_almost_spmv.png}\n    }\n    \\caption{Performance evaluation of two \\textsc{SpMV}\\xspace kernels available in the \\textsc{Ginkgo}\\xspace open source library and Intel's oneMKL vendor library on the Intel GPUs. The experiments on the \\textsc{Gen9}\\xspace architecture (left) use IEEE 754 double precision arithmetic, the experiments on the \\textsc{Gen12}\\xspace (right) use IEEE 754 single precision arithmetic.}\n    \\label{fig:spmvperf}\n\\end{figure}\n\n\n\nNext, we turn to evaluating the performance of numerical functionality on the Intel GPUs. All \\textsc{SpMV}\\xspace experimental performance data we report reflects the average of 10 kernel repetitions after 2 warmup kernel launches. In \\Cref{fig:spmvperf}, we visualize the performance of the \\textsc{CSR}\\xspace and \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace kernels of the \\textsc{Ginkgo}\\xspace library along with the performance of the \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace kernel from the oneAPI library. Each dot represents the performance for one of the test matrices of the Suite Sparse Matrix Collection~\\cite{suitesparse}. On the \\textsc{Gen9}\\xspace GPU, we run these benchmarks using IEEE 754 double precision arithmetic. \\textsc{Ginkgo's}\\xspace \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace kernel and the \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace kernel of Intel's oneMKL library achieve similar performance, while \\textsc{Ginkgo's}\\xspace \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace generally achieves lower performance. Assuming an arithmetic intensity of 1\/6 (2 FLOP \/ 12 Byte) for the double precision \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace and 1\/8 (2 FLOP \/ 16 Byte) for the double precision \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace, we can derive for the \\textsc{Gen9}\\xspace architecture (experimental peak bandwidth 37 GB\/s) an upper bound for \\textsc{SpMV}\\xspace performance of 6 and 4.6 GFLOP\/s respectively. This theoretical upper bound does neither account for the row-pointer overhead in the \\textsc{CSR}\\xspace format nor for the read and write access to the vector. Hence, the experimental performance achieving 5.1 GFLOP\/s (\\textsc{CSR}\\xspace) and 3.8 GFLOP\/s (\\textsc{COO}\\xspace) indicate the high efficiency of the \\textsc{SpMV}\\xspace kernel implementations.\n\nGiven the lack of native IEEE 754 double precision support, we use IEEE 754 single precision in the performance evaluation on the \\textsc{Gen12}\\xspace architecture. Ignoring the access to the vectors and the CSR row-pointer, the arithmetic intensity of the \\textsc{SpMV}\\xspace routines becomes 1\/4 (2 FLOP \/ 8 Byte) for the single precision \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace and 1\/6 (2 FLOP \/ 12 Byte) for the single precision \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace. With the experimental bandwidth peak of 58 GB\/s, we derive the theoretical performance limits of 14.5 GFLOP\/s and 9.7 GFLOP\/s for the single precision \\textsc{CSR}\\xspace and \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace kernels, respectively. The experimental data presented in \\Cref{fig:spmvtwelve} reveals that both the \\textsc{CSR}\\xspace and \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace routines from \\textsc{Ginkgo}\\xspace and the \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace kernel shipping with Intel's oneAPI library achieve performance close to this theoretical performance limit\\footnote{At the point of writing, oneMKL \\textsc{CSR}\\xspace can only operate on shared memory on the \\textsc{Gen12}\\xspace architecture and oneMKL does not support the \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace operation yet.}.\n\n\n\\begin{table}[]\n    \\centering\n    \\begin{tabular}{|l|l|r|r|}\n    \\hline\n    \\hline\n    Matrix & Origin & Size (n) & Nonzeros (nz)\\\\\n    \\hline\n     rajat31    &  Circuit Simulation Problem & 4,690,002 & 20,316,253\\\\\n     atmosmodj    &  \tCFD Problem & 1,270,432 & 8,814,880\\\\\n     nlpkkt160 & Nonlinear Programming Problem & 8,345,600 & 225,422,112\\\\\n     thermal2 & Unstructured FEM & 1,228,045 & 8,580,313\\\\\n     CurlCurl\\_4 & 2nd order Maxwell & 2,380,515 & 26,515,867\\\\\n     Bump\\_2911 & 3D Geomechanical Simulation & 2,911,419 & 127,729,899\\\\\n     Cube\\_Coup\\_dt0 & 3D Consolidation Problem & 2,164,760 & 124,406,070\\\\\n     StocF-1456 & Flow in Porous Medium & 1,465,137 &  \t21,005,389 \\\\\n     circuit5M &   \tCircuit Simulation Problem & \t5,558,326 &  \t59,524,291 \\\\\n     FullChip &  Circuit Simulation Problem & \t2,987,012 &  \t26,621,990\\\\\n     \\hline\n     \\hline\n    \\end{tabular}\n    \\caption{Test matrix along with key characteristics.}\n    \\label{tab:matrices}\n\\end{table}\n\n\\begin{figure}[!h\n    \\centering\n    \\subfloat[\\textsc{Gen9}\\xspace\\label{fig:solvernine}\n    ]{\\includegraphics[width=.6\\columnwidth]{plots\/gen9_solver.png}\n    }\\\\\n    \\subfloat[\\textsc{Gen12}\\xspace\\label{fig:solvertwelve}\n    ]{\\includegraphics[width=.6\\columnwidth]{plots\/gen12lp_float_solver.png}\n    }\n    \\caption{Performance evaluation of \\textsc{Ginkgo's}\\xspace Krylov solvers on the Intel GPUs.}\n    \\label{fig:solverperf}\n\\end{figure}\n\\subsection{Krylov Solver Performance Analysis}\nWe now turn to complete linear solver applications as they are typical for scientific simulation codes. We run the solver experiment for 1,000 solver iterations after a warm-up phase. The iterative Krylov solvers we consider all have the \\textsc{SpMV}\\xspace kernel as central building block, and we use \\textsc{Ginkgo's}\\xspace \\textsc{COO}\\xspace \\textsc{SpMV}\\xspace kernel in the solver performance assessment. For this experiment, we select a set of test matrices from the Suite Sparse Matrix Collection that are orthogonal in their characteristics and origin, see \\Cref{tab:matrices}. The upper graph in \\Cref{fig:solverperf} visualizes the performance for the Krylov solvers on the \\textsc{Gen9}\\xspace architecture. All solvers achieve between 1.5 GFLOP\/s and 2.5 GFLOP\/s depending on the test matrix. We notice that the performance differences in-between the solvers are quite small compared the performance differences for the distinct problems. The lower graph in \\Cref{fig:solverperf} visualizes the performance for the Krylov solvers on the \\textsc{Gen12}\\xspace architecture. We recall that \\textsc{Gen12}\\xspace does not provide native support for IEEE double precision computations, and we therefore run the solver benchmarks in IEEE single precision.\nOverall, in this experiment, the \\textsc{Ginkgo}\\xspace solvers achieve between 5 GFLOP\/s and 9 GFLOP\/s for the distinct systems. We note that all Krylov solvers based on short recurrences are very similar in terms of performance, while the performance of the GMRES solver is usually significantly lower. This may be due to the fact that the GMRES algorithm requires solving the Hessenberg system, and some needed functionality not yet being supported on the \\textsc{Gen12}\\xspace architecture by oneAPI. The developed workaround occurs to achieve lower performance.\n\n\\subsection{Platform Portability}\nFinally, we want to take a look at the platform portability of \\textsc{Ginkgo}\\xspace{}'s functionality, and see whether the ``dpcpp'' backend can provide the same efficiency like the ``cuda'' and ``hip'' backends. For that, we do not focus on the absolute performance the functionality achieves on GPUs from AMD, NVIDIA, and Intel, but the relative performance taking the theoretical performance limits reported in the GPU specifications as baseline. This approach reflects the aspect that the GPUs differ significantly in their performance characteristics, and that Intel's OneAPI ecosystem and Intel's high performance GPU architectures still being under active development and not yet having reached the maturity level of other GPU computing ecosystems. At the same time, reporting the performance relative to the theoretical limits allows to quantify the suitability of \\textsc{Ginkgo}\\xspace{}'s algorithms and efficiency of \\textsc{Ginkgo}\\xspace{}'s kernel implementations for the distinct GPU architectures. It may also indicate the performance we can expect for \\textsc{Ginkgo}\\xspace{}'s functionality when scaling up the GPU performance.\nIn \\Cref{fig:spmvpercent} we report the relative performance of different \\textsc{SpMV}\\xspace kernels on the AMD Radeon VII (``hip'' backend), the NVIDIA V100 (``cuda'' backend), and the Intel \\textsc{Gen9}\\xspace and Intel \\textsc{Gen12}\\xspace GPUs (both ``dpcpp'' backend).\n\n\n\\begin{figure}[!h\n    \\centering\n    \\subfloat[RadeonVII\n    ]{\\includegraphics[width=.48\\columnwidth]{plots\/RadeonVII_spmv_percent_theoretical.png}\n    }\n    \\subfloat[V100\n    ]{\\includegraphics[width=.48\\columnwidth]{plots\/V100_spmv_percent_theoretical.png}\n    }\\\\\n    \\subfloat[\\textsc{Gen9}\\xspace\\label{fig:spmvnine_percent}\n    ]{\\includegraphics[width=.48\\columnwidth]{plots\/gen9_spmv_percent_theoretical.png}\n    }\n    \\subfloat[\\textsc{Gen12}\\xspace\\label{fig:spmvtwelve_percent}\n    ]{\\includegraphics[width=.48\\columnwidth]{plots\/dg1_float_spmv_percent_theoretical.png}\n    }\n\n    \\caption{\\textsc{SpMV}\\xspace kernel bandwidth relative to the peak bandwidth for \\textsc{SpMV}\\xspace kernels available in the \\textsc{Ginkgo}\\xspace open source library and vendor libraries on the AMD, NVIDIA, and Intel GPUs.}\n    \\label{fig:spmvpercent}\n\\end{figure}\n\nAs expected, the achieved bandwidth heavily depends on the \\textsc{SpMV}\\xspace kernel and the characteristics of the test matrix. Overall, the performance figures indicate that the \\textsc{SpMV}\\xspace kernels achieve about 90\\% of peak bandwidth on A100 and \\textsc{Gen12}\\xspace, but about 60-70\\% of peak bandwidth on RadeonVII and \\textsc{Gen9}\\xspace. At the same time, we notice that on the \\textsc{Gen12}\\xspace, the performance of the oneMKL \\textsc{CSR}\\xspace \\textsc{SpMV}\\xspace to be inconsistent, largely outperforming \\textsc{Ginkgo}\\xspace{}'s \\textsc{SpMV}\\xspace kernels for some cases, but underperforming for others. Overall, \\textsc{Ginkgo}\\xspace{}'s \\textsc{SpMV}\\xspace kernels are on all platforms competitive to the vendor libraries, indicating the validity of the library design and demonstrating good performance portability.\n\n\\section{\\textsc{Ginkgo}\\xspace design}\n\\label{sec:gko}\n\\textsc{Ginkgo}\\xspace is a GPU-focused cross-platform linear operator library focusing on sparse linear algebra~\\citep{ginkgoarxiv,ginkgojoss}. The library design is\nguided by combining ecosystem extensibility with heavy,\narchitecture-specific kernel optimization using the platform-native\nlanguages CUDA (NVIDIA GPUs), HIP (AMD GPUs), or OpenMP (Intel\/AMD\/ARM\nmulticore)~\\cite{cojean2020ginkgo}. The software development cycle ensures production-quality code by featuring unit testing, automated configuration and installation,\nDoxygen code documentation, as well as a continuous integration and\ncontinuous benchmarking framework~\\cite{gpe}.\n\\textsc{Ginkgo}\\xspace provides a comprehensive set of sparse BLAS operations, iterative solvers including many Krylov methods, standard and advanced preconditioning techniques, and cutting-edge mixed precision methods~\\cite{toms-adaptiveblockjacobi}.\n\nA high-level overview of \\textsc{Ginkgo}\\xspace{}'s software architecture is visualized in \n\\Cref{fig:gko_desgin}. The library design collects all classes and generic \nalgorithm skeletons in the ``core'' library which, however, is useless without \nthe driver kernels available in the ``omp'', ``cuda'', ``hip'', and ``reference'' \nbackends. We note that ``reference'' contains sequential CPU kernels used to \nvalidate the correctness of the algorithms and as reference implementation for \nthe unit tests realized using the googletest \\cite{googletest} framework.\nWe note that the ``cuda'' and ``hip'' backends are very similar in kernel design, and we therefore have ``shared'' kernels that are identical for the NVIDIA and AMD GPUs up to kernel configuration parameters~\\cite{Tsai2020PreparingGF}.\nExtending \n\\textsc{Ginkgo}\\xspace{}'s scope to support Intel GPUs via the DPC++ language, we add the ``dpcpp'' backend containing the kernels in the DPC++ language.\n\n\n\\begin{figure}[!b]\n  \\centering\n  \\includegraphics[width=0.9\\linewidth]{plots\/CUDA_HIP_DPCPP}\n  \\caption{The \\textsc{Ginkgo}\\xspace library design overview.}\n  \\label{fig:gko_desgin}\n\\end{figure}\n\nTo reduce the effort of adding a DPC++ backend, we use the same \nbase components of \\textsc{Ginkgo}\\xspace{} like \\texttt{config}, \\texttt{binding},  \n\\texttt{executor}, \\texttt{types} and \\texttt{operations},\nwhich we only extend and adapt to support DPC++.\n\\begin{itemize}\n\\item \\texttt{config}: hardware-specific information like warp size, \nlane\\_mask\\_type, etc.;\n\\item \\texttt{binding}: the C++ style overloaded interface to vendors' BLAS and sparse BLAS\nlibrary and the exception calls of the kernels not implemented;\n\\item \\texttt{executor}: the ``handle'' controlling the kernel execution, all form of\ninteractions with the hardware such as memory allocations and the ability to switch\nthe execution space (hardware backend);\n\\item \\texttt{types}: the type of kernel variables and the conversion between library \nvariables and kernel variables;\n\\item \\texttt{operations}: a class aggregating all the possible kernel implementations\n  such as reference, omp, cuda, hip, and dpc++, which allows to switch between\n  implementations at runtime when changing the executor type used.\n\\end{itemize}\n\n\n\\section{Introduction}\n\\label{s1-intro}\nFor a long time, Intel GPUs were almost exclusively available as integrated component of Intel CPU architectures. However, at latest with the announcement that the Aurora Supercomputer will be composed of general purpose Intel CPUs complemented by discrete Intel GPUs and the deployment of the oneAPI ecosystem in cooperation with CodePlay, Intel has committed to enter the arena of discrete high performance GPUs. Other than integrated GPUs, discrete GPUs are usually not exclusively intended to accelerate graphics, but they are designed to also deliver computational power that can be used, e.g., for scientific computations. On the software side, the oneAPI ecosystem promoted by Intel intends to provide a platform for C++ developers to develop code in the DPC++ language that can be executed on any Intel device, including CPUs, GPUs, and FPGAs.\n\nIn 2020, Intel released the Intel generation 12 Intel\\textsuperscript{\\tiny\\textregistered} Iris\\textsuperscript{\\tiny\\textregistered} Xe Graphics GPU codename {\\emph{DG1}}, an architecture more powerful than the Intel generation 9 integrated GPU deployed in many systems, and with full support of the oneAPI ecosystem. As this GPU may be spearheading the development of Intel's discrete GPU line, we assess the performance this GPU can achieve in numerical calculations. Specifically, we develop a DPC++ backend for the \\textsc{Ginkgo}\\xspace open source math library, and benchmark the developed functionality on different Intel GPU architectures. As \\textsc{Ginkgo's}\\xspace main focus is on sparse linear algebra, we assess the performance of the sparse matrix vector product (\\textsc{SpMV}\\xspace) and iterative Krylov solvers within the hardware-specific performance limits imposed by arithmetic peak performance and memory bandwidth. We consider both double precision and single precision computations and compare against Intel's vendor library oneMKL designed for the oneAPI ecosystem.\n\nUp to our knowledge, we are the first to present the functionality and performance of an open source math library on Intel discrete GPUs. We structure the paper into the following sections:\nIn \\Cref{sec:gko}, we introduce the \\textsc{Ginkgo}\\xspace open source library and its design for platform portability. In \\Cref{sec:dpcpp}, we introduce the oneAPI ecosystem and the DPC++ programming environment. In \\Cref{sec:porting}, we discuss some aspects of adding a DPC++ backend to \\textsc{Ginkgo}\\xspace for portability to Intel GPUs. For convenience, we briefly recall in \\Cref{sec:numerics} the functionality and some key aspects of the algorithms we utilize in our experimental evaluation. This performance evaluation is presented in \\Cref{sec:experiments}: we initially benchmark the both the Intel generation 9 and 12 GPUs in terms of feasible bandwidth and peak performance to derive a roofline model, then evaluate the performance of \\textsc{Ginkgo's}\\xspace \\textsc{SpMV}\\xspace kernels (also in comparison to the \\textsc{SpMV}\\xspace routine available in the oneMKL vendor library), and finally assess the performance of \\textsc{Ginkgo's}\\xspace Krylov solvers. For completeness, we include performance results using \\textsc{Ginkgo's}\\xspace other backends on high-end AMD and NVIDIA hardware to demonstrate the (performance) portability of the \\textsc{Ginkgo}\\xspace library. We conclude with a summary of the porting and performance experiences on the first discrete Intel GPU in \\Cref{sec:conclusions}.\n\n\\section*{Acknowledgment}\n\n\\FloatBarrier\n\\bibliographystyle{plain}\n\n\\section{Central Sparse Linear Algebra Functionality}\n\\label{sec:numerics}\n\nAn important routine in sparse linear algebra is the \\textbf{sparse matrix product} (\\textsc{SpMV}\\xspace). This kernel reflects how a discretized linear operator acts on a vector, and therewith plays the central role in the iterative solution of linear problems and eigenvalue problems. Popular methods based on the repetitive application of the \\textsc{SpMV}\\xspace kernel are Krylov subspace solver such as Conjugate Gradient (CG), GMRES, or BiCGSTAB~\\cite{Saad:1986:GGM:14063.14074}, and the PageRank algorithm based on the Power Iteration~\\cite{pagerank}. The \\textsc{SpMV}\\xspace kernel is also a key routine in graph analytics as it can be used to identify all immediate neighbors of a node or a set of nodes. \n\nThe sparse data format used to store the discretized matrix and the kernel processing scheme of an \\textsc{SpMV}\\xspace kernel are usually optimized to the hardware characteristics and the matrix properties. In particular on SIMD-parallel architectures like GPUs, the optimization balances between minimization of the matrix memory footprint and efficient parallel processing~\\cite{spmv}. \nIn the performance evaluation in this paper, we consider two sparse matrix formats: 1) the ``coordinate format'' (\\textsc{COO}\\xspace) that stores all nonzero entries (and only those) of the matrix along with their column-indices and row-indices, and the ``compressed sparse row'' (\\textsc{CSR}\\xspace) format that reduces the memory footprint of the \\textsc{COO}\\xspace format further by replacing the explicit row-indices with pointers to the first element in each row of a row-sorted \\textsc{COO}\\xspace matrix. We focus on these popular matrix formats not only because of their widespread use, but also because Intel's oneMKL library provides a heavily-optimized \\textsc{CSR}\\xspace-\\textsc{SpMV}\\xspace routine for Intel GPUs. For a theoretical analysis of the arithmetic intensity of the sparse data formats, one usually simplifies the \\textsc{CSR}\\xspace memory footprint as 1 floating point value + 1 index value per nonzero entry (8 Byte for single precision \\textsc{CSR}\\xspace, 12 Byte for double precision \\textsc{CSR}\\xspace) and the \\textsc{COO}\\xspace memory footprint as 1 floating point value + 2 index values per nonzero entry (12 Byte for single precision \\textsc{CSR}\\xspace, 16 Byte for double precision \\textsc{CSR}\\xspace).\n\nAside from the \\textsc{SpMV}\\xspace kernel which forms the backbone of many algorithms, in the present performance evaluation we also consider \\textbf{iterative sparse linear system solvers} that are popular in scientific computing. Specifically, we consider the Krylov solvers CG, BiCGSTAB, CGS, an GMRES. All these solvers are based on the principle of successively building up a Krylov search space and approximating the solution in the Krylov subspace. While the generation of the Krylov search directions is specific to the distinct solvers and realized via a combination of orthogonalizations and vector updates, all solvers heavily rely on the \\textsc{SpMV}\\xspace kernel. All solvers except the GMRES solver are based on short recurrences, that is, the new Krylov search direction is only orthogonalized against the previous search direction~\\cite{saad}. Conversely, GMRES stores all search directions, and each new search direction is orthogonalized against all previous search direction~\\cite{Saad:1986:GGM:14063.14074}. Therefore, the orthogonalization plays a more important role in the GMRES algorithm. Another difference is that all algorithms except the CG algorithm are designed to solve general linear problems, while the CG algorithm is designed to solve symmetric positive definite problems. \nFor a more comprehensive background on the Krylov solvers we consider, we refer the reader to~\\cite{saad}.\n\n\n\\section{Porting to the DPC++ ecosystem}\n\\label{sec:porting}\nPorting CUDA code to the DPC++ ecosystem requires to acknowledge that the SYCL-based DPC++ ecosystem is expressing algorithms in terms of tasks and their dependencies, which requires a fundamentally-different code structure. For the porting process, Intel provides the ``DPC++ Compatibility Tool'' (DPCT) that is designed to migrate CUDA code into compilable DPC++ code. DPCT is not expected to automatically generate a DPC++ ``production-ready'' executable code, but ``ready-to-compilation'' and it requires the developer's attention and effort in fixing converting issues and tuning it to reach performance goals. However, with oneAPI still being in its early stages, DPCT still has some flaws and failures, and we develop a customized porting workflow using the DPC++ Compatibility Tool at its core, but embedding it into a framework that weakens some DPCT prerequisites and prevents incorrect code conversion. In general, DPCT requires not only knowledge of the functionality of a to-be-converted kernel, but also knowledge of the complete library and its design. This requirement is hard to fulfill in practice, as for complex libraries, the dependency analysis may exceed the DPCT capabilities. Additionally, many libraries do not aim at converting all code to DPC++, but only a subset to enable the dedicated execution of specific kernels on DPC++-enabled accelerators. In \\Cref{sec:isolated_modification}, we demonstrate how we isolate kernels to be converted by DPCT from the rest of the library. Another flaw of the early version of the DPCT is that it typically fails to convert CUDA code making use of atomic operations or the cooperative group functionality. As \\textsc{Ginkgo}\\xspace implementations aim at executing close to the hardware-induced limits, we make heavy use of atomic- and cooperative group operations. In \\Cref{sec:dpct_workaround} we demonstrate how we prevent DPCT from executing an incorrect conversion of these operations such that we can convert them using a customized script. To simplify the maintenance of the platform-portable \\textsc{Ginkgo}\\xspace library, our customized porting workflow also uses some abstraction to make the DPC++ code in this first version look more similar to CUDA\/ HIP code. We note that this design choice is reflecting that the developers of \\textsc{Ginkgo}\\xspace are currently used to designing GPU kernels in CUDA, but it may not be preferred by developers used to programming in task-based languages. We elaborate on how we preserve much of the CUDA\/ HIP code style in \\Cref{sec:cuda_familiar}.\n\n\n\\subsection{Isolated Modification}\n\\label{sec:isolated_modification}\nUnfortunately, DPCT needs to know the definition of all functions related to the target file. Otherwise, when running into a function without definition in the target file, DPCT returns an error message. Furthermore, DPCT by default converts all files related to the target file containing any CUDA code that are located in the same folder like the target file\\footnote{Also files in subfolders are automatically converted by DPCT if they contain CUDA code.}.\nTo prevent DPCT from converting files that we do not want to be converted, we have to artificially restrict the conversion to the target files. We achieve this by copying the target files into a temporary folder and considering the rest of the \\textsc{Ginkgo}\\xspace software as a system library. After the successful conversion of the target file, we copy the file back to the correct destination in the new DPC++ submodule.\n\nBy isolating the target files, we indeed avoid additional changes and unexpected errors, but we also lose the DPCT ability to transform CUDA kernel indexing into the DPC++ \\texttt{nd\\_item\\textless3\\textgreater} equivalent. As a workaround, we copy simple headers to the working directory containing the thread\\_id computation helper functions of the CUDA code such that DPCT can recognize them and transform them into the DPC++ equivalent. \nUnfortunately, this workaround works well only if DPCT converts all code correctly. If DPCT fails to convert some files or function definitions live outside the target files, we need to add a fake interface. Examples where the DPCT conversion does not meet our requirements are our custom DPC++ cooperative group interface and the DPC++ CUDA-like dim3 interface which allows to use CUDA-like block and grid kernel instantiation instead of the DPC++ \\texttt{nd\\_range}. For those, we prevent DPCT from applying any conversion steps but keep DPCT's functionality to add the \\texttt{nd\\_item\\textless3\\textgreater} launch parameters.\n\n\n\\subsection{Workaround for Atomic Operations and Cooperative Groups}\n\\label{sec:dpct_workaround}\nDPC++ provides a subgroup interface featuring shuffle operations. However, this interface is different from CUDA's cooperative group design as it requires the subgroup size as a function attribute and does not allow for different subgroup sizes in the same global group.\nBased on the DPC++ subgroup interface, we implement our own DPC++ cooperative group interface. \nSpecifically, to remove the need for an additional function attribute, we add the \\texttt{item\\_ct1} function argument into the group constructor. As the remaining function arguments are identical to the CUDA cooperative group function arguments, we therewith achieve a high level of interface similarity. \n\nA notable difference to CUDA is that DPC++ does not support subgroup vote functions like ``ballot'', ``any'', or other group operations yet. To emulate this functionality, we need to use a subgroup reduction or some algorithms provided by the oneAPI groups to emulate these vote functions in a subgroup setting. This lack of native support may affect the performance of kernels relying on these subgroup operations.\nWe visualize the workflow we use to port code making use of the cooperative group functionality in \\Cref{fig:dpct_workaround_with_coop}. This workflow composes four steps:\n\\begin{enumerate}\n    \\item Origin: We need to prepare an alias to the cooperative group function such that DPCT does not catch the keyword. We create this alias in a fake cooperative group header we only use during the porting process.\n    \\item Adding Interface: As explained in \\Cref{sec:isolated_modification}, we need to isolate the files to prevent DPCT from changing other files. During this process we add the simple interface including \\texttt{threadIdx.x} and make use of the alias function. Note that for the conversion to succeed, it is required to return the same type as the original CUDA type, which we need to extract from the CUDA cooperative group function \\texttt{this\\_thread\\_block}.\n    \\item DPCT: Apply DPCT on the previously prepared files. As we add the \\texttt{threadIdx.x} indexing to the function, DPCT will automatically generate the \\texttt{nd\\_item\\textless3\\textgreater} indexing for us.\n    \\item Recovering: During this step, we change the related cooperative group functions and headers to the actual DPC++ equivalent. We implement a complete header file which ports all the cooperative group functionality to DPC++.\n\\end{enumerate}\n\n\\begin{figure}\n    \\centering\n    \\includegraphics[width=\\textwidth]{plots\/dpct_workaround.png}\n    \\caption{Summary of the workflow used to port the cooperative groups functionality and isolating effort such that we get the correct converted DPC++ codes.}\n    \\label{fig:dpct_workaround_with_coop}\n\\end{figure}\n\nWe show in \\Cref{fig:cooperative_group} the final result of the porting workflow on a toy example featuring the use of cooperative groups. For the small example code in \\Cref{fig:cuda_coop}, if we do not isolate the code, DPCT will throw an error like \\Cref{fig:dpct_fail_coop} once encountering the cooperative group keyword. A manual implementation of the cooperative group equivalent kernel is shown in \\Cref{fig:dpcpp_coop}. Our porting workflow generates the code shown in \\Cref{fig:gko_ported_coop}, which is almost identical to the original CUDA code \\Cref{fig:cuda_coop}.\n\n\\begin{figure}\n    \\centering\n    \\subfloat[CUDA small cooperative group example\\label{fig:cuda_coop}\n    ]{\\includegraphics[width=.45\\columnwidth]{plots\/cuda_cg_sample.pdf}\n    }\n    \\subfloat[DPCT conversion fails and reports error\\label{fig:dpct_fail_coop}\n    ]{\\includegraphics[width=.45\\columnwidth]{plots\/dpct_fail_cg.pdf}\n    }\\\\\n    \\subfloat[Manual DPC++ subgroup implementation. The orange boxes are the main difference from CUDA\\label{fig:dpcpp_coop}\n    ]{\\includegraphics[width=.45\\columnwidth]{plots\/dpcpp_manual_cg.pdf}\n    }\n    \\subfloat[The result converted by our porting script\\label{fig:gko_ported_coop}\n    ]{\\includegraphics[width=.45\\columnwidth]{plots\/gko_ported_cg.pdf}\n    }\n    \\caption{The cooperative group example}\n    \\label{fig:cooperative_group}\n\\end{figure}\n\nThe conversion of CUDA atomics to DPC++ atomics is challenging as the conversion needs to recognize the data location and decide whether the DPC++ atomics operate on local or global memory. DPCT generally succeeds in this automated memory detection, however, there are two aspects that require us to create a workaround: 1) at the time of writing, DPCT fails to correctly convert atomic operations on local memory\\footnote{We reported this issue to the Intel Development Team and they are working on a bugfix.}; and 2) DPC++ does not provide atomics for complex floating point numbers\\footnote{Atomic operations on complex numbers is correct only if a single modification is applied at a time.}. We prevent DPCT from applying any conversion of atomic operations and add a customized conversion to our preprocessing script. For this to work, we manually ported the atomic functions from CUDA to DPC++ in a specific header file which is properly added during the postprocessing step.\n\n\\subsection{Workaround for Code Similarity}\n\\label{sec:cuda_familiar}\n\\textsc{Ginkgo}\\xspace was originally designed as a GPU-centric sparse linear algebra library using the CUDA programming language and CUDA design patterns for implementing GPU kernels. The \\textsc{Ginkgo}\\xspace HIP backend for targeting AMD GPUs was deployed for production in early 2020. The next step is to support Intel GPUs via a DPC++ backend. Thus, for historic reasons and simplified maintenance, we prefer to keep the coding style of the initial version of the DPC++ backend of \\textsc{Ginkgo}\\xspace similar to the CUDA coding style. We acknowledge that this design choice may narrow down the tasking power of the SYCL language, but consider this design choice as acceptable since task-based algorithms are currently outside the focus of the \\textsc{Ginkgo}\\xspace library at the backend level. However, the \\textsc{Ginkgo}\\xspace library design allows to move closer to the SYCL programming style at a later point if the algorithm properties favor this.\nFor now, we aim for a high level of code similarity by not only adding the customized cooperative group interface as discussed in \\Cref{sec:dpct_workaround}, but also adding a dim3 implementation layer for DPC++ kernel launches that uses the same parameters and parameter order like CUDA and HIP. The interface layer simply reverses the launch parameter order in a library-private member function.\n\nDespite adding a dim3 helper to use the grid and block notation from CUDA, several differences are left when calling CUDA and DPC++ kernels as in \\Cref{fig:dpct_conversion}. One fundamental difference between the CUDA\/ HIP ecosystem and DPC++ is that the latter handle the static\/dynamic memory allocation in the main component. CUDA and HIP handle the allocation of static shared memory inside the kernel and the allocation of dynamic shared memory in the kernel launch parameters. Another issue is that widely different syntax are used to call CUDA and DPC++ kernels, since DPC++ relies on a hierarchy of calls first to a queue, then a parallel instantiation. For consistency, we add another layer that abstracts the combination of DPC++ memory allocation and DPC++ kernel invocation away from the user. This enables a similar interface for CUDA, HIP, and DPC++ kernels for the main component, and shared memory allocations can be perceived as a kernel feature, see \\Cref{fig:dpct_conversion_second}. The purple block (additional\\_layer\\_call) in \\Cref{fig:dpct_conversion_second} has the same structure as the gray block (cuda\\_kernel\\_call) in the left side of \\Cref{fig:dpct_conversion}. Our script will convert the code from the left side of \\Cref{fig:dpct_conversion} to the right side of \\Cref{fig:dpct_conversion_second} by adding the corresponding additional layer automatically.\n\n\\begin{figure}[!h]\n    \\centering\n    \\includegraphics[width=0.7\\textwidth]{plots\/original_dpct_overview.png}\n    \\caption{Hierarchical view of usual CUDA (left) and DPC++ (right) kernel call and parameters.}\n    \\label{fig:dpct_conversion}\n\\end{figure}\n\n\\begin{figure}[!h]\n    \\centering\n    \\includegraphics[width=0.7\\textwidth]{plots\/dpct_additional_layer_effect.png}\n    \\caption{Wrapping the hardware-specific kernels written in HIP, CUDA, and DPC++ into an intermediate layer enables consistency in the kernel invocation across all backends.}\n    \\label{fig:dpct_conversion_second}\n\\end{figure}\n\\section*{Acknowledgments}\n\nThis work was supported by the ``Impuls und Vernetzungsfond'' of the Helmholtz \nAssociation under grant VH-NG-1241, and the US Exascale Computing Project \n(17-SC-20-SC), a collaborative effort of the U.S. Department of Energy Office \nof Science and the National Nuclear Security Administration.\n\nThe authors want to acknowledge the access to the Intel\\textsuperscript{\\tiny\\textregistered} Devcloud early access development platform.\n\n\n","meta":{"redpajama_set_name":"RedPajamaArXiv"}}
+{"text":"\n\\section{Introduction}\n\\label{sec:intro}\n \nFederated learning (FL) enables distributed clients to collaboratively train an ML model without moving their local data to the cloud.\nIt circumvents the systematic privacy risk and cost of data transfers in centrally collecting user data. FL is increasingly being adopted by many popular applications, such as Google's Gboard~\\cite{gboard}, Apple's Siri~\\cite{siri}, NVIDIA's medical platform~\\cite{nvidia}, Meta's Ads recommendation~\\cite{meta}, and WeBank risk prediction~\\cite{webank}, across up to millions of end-user devices.\n \n \nDespite its privacy advantage over traditional ML, FL faces unique challenges due to statistical heterogeneity among user data and systems-level heterogeneity among user device capabilities. \nOn the one hand, statistical heterogeneity makes one single global model insufficient for satisfying every client's data distributions~\\cite{convergence1,convergence2}.\nEven if a personalization algorithm is used to generate individual models for each client, they may suffer from heterogeneity-borne challenges~\\cite{personalization-cluster, multi-personal}.\nSeveral studies that try to mitigate the effect of statistical heterogeneity, such as FedYoGi~\\cite{yogi}, q-FedAvg~\\cite{qfedavg}, FTFA~\\cite{fine-tune}, have shown that their convergence depends on the degree of heterogeneity, both theoretically and empirically.\nOn the other hand, system heterogeneity raises challenges for straggler mitigation and fault tolerance, and degrades overall system efficiency \\cite{character-impact,tff-paper,lin}.\nFor example, recent studies that consider system heterogeneity, such as Oort~\\cite{oort}, PyramidFL~\\cite{pyramid}, and FedProx~\\cite{prox}, have shown that their performance also worsen with increasing heterogeneity (\\S\\ref{sec:flchallenge}).\n\n\nTo tackle the root cause of the problems caused by heterogeneity instead of only the symptoms arising from heterogeneity, we consider \\emph{whether we can reduce heterogeneity itself during FL training instead of simply trying to address its ill effects?} \nIntuitively and analytically, we observe that real-world FL populations often include groups of clients with statistically similar data distributions or \\emph{cohorts}~\\cite{generalization} (\\S\\ref{sec:room-improv}). \nIf a population has $K$ cohorts, training $K$ separate models -- one for each cohort with lower statistical heterogeneity -- can boost the performance of many existing FL algorithms that are orthogonal to ours and target on convergence~\\cite{yogi, prox, oort}, fairness optimization~\\cite{qfedavg}, communication efficiency~\\cite{marco, fetchsgd} and so on. \n\n\n\nAlthough some recent works that have attempted to train separate models for different client groups~\\cite{hc+fl,ifca,multi-personal}, how to cluster clients at scale and in the wild while respecting client privacy has received little systematic attention (\\S\\ref{sec:challenge}). \nTo this end, we propose \\textbf{\\name}, a cohort manager for efficient FL, to enable \n1) scalable cohort identification to reduce intra-cohort heterogeneity under large-scale and low-participation FL scenarios; and \n2) efficient cohort-based training to guarantee model convergence and facilitate most FL optimizations ({e.g.\\xspace}, fairness optimization) without extra resource cost.  \n\n\nIn addition to the challenges faced by state-of-the-art clustering mechanisms~\\cite{cfl, flexcfl}, \n\\name addresses the following practical challenges toward real FL deployment (\\S\\ref{sec:algo}). \nFirst, most existing clustering strategies require a complete pass of all clients, visibility to client data, or additional on-device training for every participant and over time, which is not only expensive and risky to privacy, but also can be impractical as clients can be unavailable over time. Instead, \\name allows sporadic client availability, and respects client resource constraints and privacy. It automatically spawns new cohorts and selects the right cohort even for unseen clients while exploring a large population. \nSecond, unlike expensive and ad-hoc hyper-parameter tuning stages used in existing solutions, \\name finds a sweet spot between creating too many or too few cohorts. \nIt also determines when to derive new cohorts to jointly optimize the model performance and the overall training resources.\\footnote{We refer to the number of participants that contribute to a round of FL training as training resource throughout this paper.}\nMoreover, \\name delivers such efficient cohort clustering and training while being robust to uncertainties ({e.g.\\xspace}, failure tolerance and unfavorable settings) at scale (\\S\\ref{sec:overview}). \n\n\nWe have implemented (\\S\\ref{sec:impl}) and evaluated (\\S\\ref{sec:eval}) \\name on a wide variety of real-world FL datasets, tasks, and algorithms at scale. \nCompared to existing solutions, \\name improves the performance for various FL algorithms, such as better test accuracy (2.1\\%--8.2\\%) and convergence speed (up to 2.2$\\times$) and smaller bias of model accuracy (5\\%--116\\%). \n \n \nOverall, we make the following contributions in this paper:\n\\begin{denseitemize}\n    \\item We propose a systematic clustering mechanism to identify cohorts for the practical large-scale, low-participation and resource-constrained FL setting.\n    \n    \\item We identify a sweet spot for jointly optimizing model convergence and training cost, and provide analytical insights to ensure good model performance.\n     \n    \\item We implement and evaluate \\name at scale, showing the improvement of final accuracy, convergence time, and model fairness over the state-of-the-art.  \n    \n\\end{denseitemize}\n \n \n \n \n \n \n \n \n\n\n\n\n\n\n\\section{BACKGROUND AND MOTIVATION}%\n\\label{sec:motivation}\n \nWe start with a brief introduction of federated learning (\\S\\ref{sec:back}),\nfollowed by the challenges it faces due to heterogeneity in real-world settings (\\S\\ref{sec:flchallenge} ) .\nNext, we describe some opportunities to improve FL that motivates our work (\\S\\ref{sec:room-improv}).\nFinally, we explain the limitations in related works that motivate our algorithm and system design  (\\S\\ref{sec:challenge}).\nMore discussion about related works can be found in  Appendix~\\ref{sec:related}.\n \n \n\\subsection{Federated Learning}\n\\label{sec:back}\n\\begin{figure}[t!]\n   \\centering\n   \\includegraphics[trim=0 130 0 0,clip,scale=0.88]{original.pdf} \n     \\caption{Traditional FL overview. The server first selects from available clients and sends out model weights. Clients train the updated model on their local dataset. After training is finished, clients report their model gradient to the server.}\n   \\label{fig:orig}\n   \\vspace{-0.4cm}\n   \\end{figure}\n \nA typical cross-device FL system consists of two primary components (Figure~\\ref{fig:orig}):\nA logically centralized cloud \\emph{server} that maintains a single global model and many distributed \\emph{clients} with private local data. \nThe overall lifecycle of an FL training round can be divided into three broad stages.\n\\begin{denseitemize}\n  \\item[\\circled{1}] \\textbf{Selection stage:} Clients check in with the server continuously to announce their availability for FL computation.\n    The server selects a number of \\emph{participants} for that round based on its client selection strategy.\n \n  \\item[\\circled{2}] \\textbf{Execution stage:} The selected participants download the current model from the server and perform server-specified computation on their local data. \n  \n  \\item[\\circled{3}] \\textbf{Aggregation stage:} Participants that successfully complete the execution stage send model updates back to the server.\n    The server aggregates the updates to finalize an updated model for the next round.\n\\end{denseitemize}\n \n \n \n\\subsection{Heterogeneity Challenges in FL} \n\\label{sec:flchallenge}\n \nUnlike centralized ML, FL faces unique challenges in terms of statistical and system heterogeneity.\nThe former refers to the diversity of data distribution across clients, which hinders model convergence; the latter refers to variations in system characteristics among participants' devices, which results in large differences in training performance.\nIncreasing heterogeneity in either dimension leads to poor performance.\n \n \n  \n \n \n\\begin{figure}[t!]\n  \\centering\n     \\begin{subfigure}{1.6in}\n  \\centering\n   \\includegraphics[scale=0.3]{heter_fair_acc_base.pdf} \n     \\caption{Statistical heterogeneity. }\n   \\label{fig:heter}\n  \\end{subfigure}\n     \\begin{subfigure}{1.6in}  \n   \\centering \n   \\includegraphics[scale=0.3]{sys-heter.pdf} \n     \\caption{System heterogeneity.  }\n   \\label{fig:sysheter}\n     \\end{subfigure}\n    \\caption{The impact of heterogeneity on final accuracy. }\n\\end{figure}\n \n\\paragraph{Impact of statistical heterogeneity.}\n Under large statistical heterogeneity,  poor model accuracy, convergence and fairness can be observed by individual clients as the model is validated on their local data but is trained over all the clients.  \nExisting works that address statistical heterogeneity in FL assume bounded heterogeneity~\\cite{convergence1, convergence2, yogi, prox}. \nThus, they are fragile to larger statistical heterogeneity.\\footnote{In this experiment, we measure the statistical heterogeneity among a set of clients using the popular L2 distance on their data distributions~\\cite{oort}.}\nFor example, our analysis of FedYoGi~\\cite{yogi} (a  state-of-the-art FL algorithm) on OpenImage~\\cite{openimg} (an FL image dataset),\nin Figure~\\ref{fig:heter} shows that the model accuracy and its fairness across clients worsens with increasing statistical heterogeneity.\nTo reach the same model performance with larger heterogeneity, more communication and\/or computation costs are needed. \nThis is true for personalization algorithms as well~\\cite{personalization-cluster}. \n \n\\paragraph{Impact of system heterogeneity.}\nHeterogeneity of system-level characteristics raise challenges such as fault tolerance and straggler mitigation~\\cite{prox,papaya}. \nOver-commitment~\\cite{tff-paper}, which discards updates from slowest-responding participants, is commonly used to reduce the impact of stragglers, but it may lead to participation bias against slow devices.\nFigure~\\ref{fig:sysheter} shows the final accuracy of the OpenImage task under different degrees of system heterogeneity (variance of system speed).\nFor each experiment, we control the round duration and the number of successful participants to be the same; as a result, participation bias exacerbates with increasing system heterogeneity.\nSince participation bias may enhance statistical heterogeneity in another form,\nthe final accuracy decreases with increasing system heterogeneity (albeit at a slower rate than statistical heterogeneity).\n \n \n\\begin{figure}[!t]\n\\centering\n\\begin{minipage}[t]{0.22\\textwidth}\n\\centering\n  \\includegraphics[scale=0.3]{heter_by_cluster.pdf} \n    \\caption{Intra-cluster heterogeneity in real datasets.}\n  \\label{fig:kmeans}\n   \\end{minipage}\n      \\hspace{2mm}\n\\begin{minipage}[t]{0.22\\textwidth}\n\\centering\n  \\includegraphics[scale=0.3]{num_clt.pdf} \n    \\caption{Diminishing return by adding more participants.}\n  \\label{fig:num_clt}\n\\end{minipage} \n\\end{figure}\n \n \n \n \n\\subsection{Opportunities }\n\\label{sec:room-improv}\nThe opportunity for improving FL training performance, therefore, lies in decreasing heterogeneity especially the statistical heterogeneity.\nBy identifying statistically homogeneous groups and performing FL within each group, we may be able to boost model performance of most FL algorithms that are suffered by the heterogeneity.\n \n \nDespite large statistical heterogeneity across the entire FL client population, there exist groups of statistically similar clients in most large populations.\nFigure~\\ref{fig:kmeans} shows that for four representative FL workloads~\\cite{fedscale} in the real world.\nWe use K-means clustering (with increasing values of K) on clients' data distribution by their L2-distance metric. \nAs the number of clusters increases from one ({i.e.\\xspace}, traditional FL with one global model) to larger values, we observe a small number of statistically similar groups emerge for most datasets.\n \n However, training K models to converge may need more training resources compared to training one model. \n As shown in Figure~\\ref{fig:num_clt}, increasing training resources has diminishing returns on the model convergence, which  presents the primary opportunity leveraged in this work: \\emph{instead of letting all available clients contribute to a single global model, it may be more beneficial to partition them into several cohorts, each with smaller heterogeneity.}\n  \n \n \n\n\\begin{table}[]\n  \\resizebox{\\columnwidth}{!}{\n  \\begin{tabular}{c|ccccc}\n  \\hline\n                                      & CFL      & FL+HC        & FlexCFL   & IFCA   & \\name         \\\\ \\hline\n  Partial part.             & $\\times$ & $\\checkmark$ & $\\checkmark$ & $\\checkmark$ & $\\checkmark$ \\\\\n  Low avail.              & $\\times$ & $\\times$     & $\\checkmark$ & $\\checkmark$ & $\\checkmark$ \\\\\n  Res. constraint                 & $\\times$ & $\\times$     & $\\times$     &  $\\times$     & $\\checkmark$ \\\\\n  Training perf.    & $\\times$ & $\\times$     & $\\times$     &$\\times$     & $\\checkmark$ \\\\\n  \\hline\n  \\end{tabular}}\n   \\caption{Comparing \\name with existing Clustered FL.}\n    \\label{table:comparison}\n\\end{table}\n  \n\\begin{figure*}[t]\n  \\vspace{-1cm}\n  \\begin{minipage}[t]{0.3\\textwidth}\n \n    \\includegraphics[trim=0 70 0 100,  scale=1]{coco.pdf} \n       \\caption{\\name architecture. \\name server guides \\name clients to train on their best-fit cohorts.}\n     \\label{fig:coco}\n     \\end{minipage}\n        \\hspace{1mm}\n  \\begin{minipage}[t]{0.66\\textwidth}\n  \\centering\n     \\includegraphics[trim=0 70 0 0,clip, scale=1.25]{workflow.pdf}     \n     \\caption{\n       {\\name} lifecycle. \n       Clients first submit their affinity requests, which are then forwarded to the matched cohorts. \n       Then each cohort conducts traditional FL training independently. \n       Finally, each cohort reports back the results to guide clients' cohort selection. }\n     \\label{fig:workflow}\n  \\end{minipage}\n\\end{figure*}\n\n\\subsection{Limitations of Existing Clustered FL Solutions}\n\\label{sec:challenge}\n \nRecent efforts in the ML community have (theoretically) explored to create smaller groups of statistically similar clients. Yet, existing clustered FL algorithms often fall short across multiple dimensions in practical deployments (Table~\\ref{table:comparison}), which motivates us to design systems support for efficient cohort identification and training. We empirically show the superior performance of \\name over them too (\\S\\ref{sec:e2e}). \n\n \n\\paragraph{Scalability.}\nFL in practice often involves millions of clients, and only a small fraction, $\\sim$5\\%~\\cite{tff-paper, fedscale}, are available to participate in during a time window.\nSuch low availability and partial participation limit the available information for the clustering algorithms. \nThis, however, is ignored by CFL~\\cite{cfl}, multi-center~\\cite{multi-personal} and FL+HC~\\cite{hc+fl}, \nand makes the deployment impractical as they requires a complete pass over the entire population to identify clusters. \nFurthermore, clients usually have limited on-board resources, but IFCA~\\cite{ifca}, FlexCFL~\\cite{flexcfl}, and FL+HC require extra computation to for \\emph{every} client  and\/or over time to assign them to a cluster, which incurs large computation and communication overhead. \nFor example, IFCA initiates multiple global models and broadcasts all models for each participant to choose from in each round; and FlexCFL and FL+HC require pre-training for every client to identify their clusters.\n \n \n \n\\paragraph{Efficiency.}\nIn addition to the challenge of identifying statistically similar groups at scale, how to leverage those similar groups to improve model performance introduces new trade-offs in deciding the right number of cohorts and time to partition.\nGiven a fixed amount of resources, generating more cohorts results in smaller heterogeneity; but it divides up the fixed training resource and unique training data per cohort, which hurts model convergence and generalizability. \nMoreover, partitioning clients too early can lead to model bias as the model is not generalized well by training on various clients, while partitioning too late can result in model variance over high heterogeneity. \nUnfortunately, most existing clustered FL algorithms are unaware of these tradeoffs, and rely on ad-hoc hyper-parameter tuning, which is prohibitively expensive as FL training can take many days and consume large amount of resources. \n\n\n\n\n\n\n\\section{\\name Clustering}%\n\\label{sec:algo}\n \nIn this section, we present the core clustering algorithm used in \\name to identify cohorts (\\S\\ref{sec:prob}- \\S\\ref{sec:cold-start}). \nThen, we discuss the techniques of cohort-based training to boost model performance under realistic constraints (\\S\\ref{sec:system-tradeoff}).\n \n\\subsection{Problem Formulation and Overview}\n\\label{sec:prob} \n\n\\name's primary objective is to accurately cluster clients by their statistical heterogeneity into appropriate cohorts under the following real-world FL constraints: \n\\begin{inlineenum}\n    \\item The participants $\\mathcal{P}^r$ in each round are only a small fraction of all clients ($N$), {i.e.\\xspace}, $|\\mathcal{P}^r| \\ll N $, and  \n    \\item The information available to today's FL central server is limited to gradients transferred by the existing FL algorithms. \n     \\end{inlineenum}\n \nThe \\textit{input} to the server is a list of participants along with their gradients collected over training rounds based on these two constraints. \nSince the gradient of client $i$ relies on its local dataset $x_i$ and the received model weights (unique for the round $r$ and cohort $m$), we formulate the \\textit{input} of the clustering algorithm in each round $r$ as $\\{\\{g_m^r(x_i) \\}_{ i \\in \\mathcal{P}_m^r} \\}_{m\\in [1, M_r]}$, where $g_m^r(x_i)$ is the gradient of participant $i$ , $\\mathcal{P}_m^r$ is the participants list, and $M_r$ is the number of cohorts.\n \n\nThe \\textit{output} is the cohort membership $\\{S_i \\in [1, M]\\}$ for each client $i\\in[1,N]$ with the \\textit{objective} to minimize the average intra-cohort heterogeneity:\n\n   \\vspace{-0.4cm}\n   \\begin{equation}\n  J = \\sum_{m=1}^M \\frac{1}{2|\\{x | S_x=m\\}|} \\sum_{S_i,S_j = m} || {x_i} - {x_j} ||^2.\n   \\label{eq:obj}\n\\end{equation}\n   \\vspace{-0.4cm}\n\n\n\n\nIntuitively, we can model it as a clustering problem $\\{ x_1, ... , x_N \\} \\rightarrow \\{ S_1,...,S_N  \\}$, whereas doing so encounters new challenges.\n\\begin{inlineenum}\n\\item  How to derive client data similarity without direct access to data and without iterating all but part of the clustering objects every round.\n\n\\item How to assign new incoming clients to the best-fit cohort without prior information.\n\n\n\\end{inlineenum}\n\n \n \nFollowing this problem definition and challenge, Algorithm~\\ref{algo:all} illustrates the overview of \\name clustering mechanism, \nwhich consists of an online cluster algorithm to cluster clients at scale (\\S\\ref{sec:clustering}) and the cohort selection for individual FL clients (\\S\\ref{sec:cold-start}).\n \n  \\renewcommand\\algorithmiccomment[1]{%\n  \\hspace{2em} \\eqparbox{COMMENT}{$\\triangleright$ #1}%\n}\n  \n\\begin{algorithm}[t!]\n    \\caption{\\name Clustering Algorithm \n  \n    }\n    \\label{algo:all}\n        \\begin{algorithmic}[1]\n \n   \\STATE {\\bfseries Input: }{Participants list $\\mathcal{P}$, Exploration factor $\\epsilon$} \n    \\STATE {\\bfseries Output: }{Client-cohort membership list $S_{\\mathcal{D}}$}\n \\STATE $M \\leftarrow 1$;  \n \\COMMENT{Initialize the number of cohorts.}\n\\vspace{-0.4cm}\n \\STATE $S_{\\mathcal{D}} \\leftarrow 0 $;  \n \\COMMENT{Initialize client-cohort membership.}\n\\vspace{-0.4cm}\n\\STATE $R_{\\mathcal{D}, M } \\leftarrow 0 $;   \n\\COMMENT{Initialize client-cohort reward.} \n\\vspace{-0.4cm}\n         \\STATE $L_{\\mathcal{D}, M } \\leftarrow   N\/A. $  \n\\COMMENT{Initialize client-cohort cluster id.}\n                \n         \\FOR{each round $ r = 1, 2, . . .  $}         \n\n           \\STATE  $\\mathcal{P}_{m}^r = \t\\{ i | S_i = m, i \\in \\mathcal{P}^r$\\} \\label{code:reward}      \n         \\FOR{each cohort $ m = 1, . . . , M $  in  parallel } \n       \t\t\\STATE \\texttt{\\name-Clustering} ($\\mathcal{P}^r_m  $  )\n\t \\ENDFOR   \n             \\STATE  $S_{\\mathcal{D}} = \\texttt{CohortSelection}  (R_{\\mathcal{D}}, \\epsilon, r )$                   \\label{code:select}           \n     \\ENDFOR\n     \\RETURN $S_{\\mathcal{D}}$\n      \n  \\vspace{.5cm}\n  \\textbf{Function}  \\texttt{\\name-Clustering}(Participants list$\\mathcal{P}^r_m $)  \\label{code:func}\n  \n            \n                \\hspace{-1cm}      \\COMMENT{\\com{ Identify clusters on the fly.}}\n \t\\IF{$r==1$} \\label{code:kmeans}\n        \\STATE    $L_{ \\mathcal{P}_{m}^r, m } = \\texttt{Kmeans}( g_{m}^r(x_{\\mathcal{P}_{m}^r}), K).  $ \\label{code:kmeans-label}\n   \t\\ELSE \\label{code:assign}\n\t\\STATE  $\\mathcal{P}_0 = \\{i | L_{i,m} = 0, i\\in \\mathcal{P}_{m}^r\\}$ \\label{code:cluster-cen1}\n\t\\STATE  $\\mathcal{P}_1 = \\{i | L_{i,m}  = 1, i\\in \\mathcal{P}_{m}^r\\}$\n        \\STATE $ C_0 = avg( g_m^r(x_{\\mathcal{P}_0}) )$, $ C_1 = avg( g_m^r(x_{\\mathcal{P}_1}) )\t$    \\label{code:cluster-cen2}\n   \t\\STATE $ L_{\\mathcal{P}_{m}^r,m}  = arg\\min_k ||  g_m^r(x_{\\mathcal{P}_m^r}) - C_k ||_2\t$  \\label{code:label}\n        \\ENDIF \n        \n      \n           \\hspace{-1cm}   \\COMMENT{\\com{Decide partitioning to start separate training. }}\n  \t\\IF{ \\texttt{PartitionCriteria}(m) } \\label{code:decision}\n\t\\STATE $ M=M+1$\n\t\\STATE $R_{\\mathcal{D}, m} = R_{\\mathcal{D}, m} + 0.1 * \\mathds{1}(L_{\\mathcal{D}, m} == 0)$\n\t\\STATE $R_{\\mathcal{D}, M} = R_{\\mathcal{D}, m} + 0.1 * \\mathds{1}(L_{\\mathcal{D}, m} == 1)$\n  \t\\ENDIF\n\t\n   \n           \\hspace{-1cm}  \\COMMENT{\\com{Update rewards for cohort selection.}}\n  \\IF{$M > 1$} \n       \\STATE   $  R_{ \\mathcal{P}_{m}^r ,m } =\\texttt{ExploitReward}(  R_{ \\mathcal{P}_{m}^r ,m }, x_{\\mathcal{P}^r_m} ) $ \\label{code:exploit}\n\n       \\STATE $ R_{ \\mathcal{P}_{m}^r ,m' } $=\\texttt{ExploreReward}($ R_{ \\mathcal{P}_{m}^r } ,m'$),  $\\forall m \\neq m'$  \\label{code:explore}\n\n       \n       \\label{code:efficient}\n  \\ENDIF\n           \n        \\end{algorithmic}\n\\end{algorithm}\n \n \n\\subsection{Online Clustering}  \n\\label{sec:clustering} \n\nTo derive client data similarity without direct access, \\name leverages client gradient similarity to derive the client data similarity based on the theoretical insights from related works~\\cite{cfl,proof} under certain assumptions.\nIntuitively, gradient divergence can be attributed to data heterogeneity~\\cite{prox} and similar clients would have smaller gradient divergence, based on the \\emph{same} initial model weight. \nWe leverage this observation and measure the gradient divergence by the widely-used cosine similarity~\\cite{cosine} among the input batch of gradients $g_m^r(x_i), i \\in \\mathcal{P}_m^r$ to investigate client similarity.\\footnote{Cosine similarity measures the similarity between two vectors of an inner product space~\\cite{cosine}.}  \nWe denote $g(\\cdot)$ as the normalized gradient for simplicity of exposition.\n\n\n\nTo accommodate partial input to the clustering algorithm, \\name represents the problem as a mini-batch clustering problem and clusters clients adaptively.\nHowever, traditional mini-batch clustering algorithms~\\cite{mini-batch} usually maintain a running center for each cluster, which is used to assign the incoming batch of points. \nHowever, this strategy cannot directly be applied to our problem because we only know the gradients $\\{g_m^r(x_{\\mathcal{P}_m^r}) \\}$ instead of the raw data $x_{\\mathcal{P}}$. \nMoreover, since the gradient $g_m^r(\\cdot)$ depends on the initial model of round $r$ and client data, which is unknown and different across rounds and cohorts, it is hard to maintain absolute running centers over rounds. \nHence, \\name approximates the cluster centers based on the gradients from the current round -- that is, it averages the gradients with known cluster membership from the cluster (Algorithm~\\ref{algo:all} Lines~\\ref{code:cluster-cen1}--\\ref{code:cluster-cen2}).\nThen, \\name uses the approximated cluster centers to update the cluster membership for new clients.\n \n \n \n \nHence, \\name starts with one cohort with the entire FL population and adaptively identify cohorts.\nAfter using K-means to initialize the cluster prototype (Line~\\ref{code:kmeans-label}), during every round, \n \\name first estimates cluster centers by averaging corresponding cluster members' gradient from the current round (Lines~\\ref{code:cluster-cen1}--\\ref{code:cluster-cen2}), and then\n assigns new clients to their closest cluster (Line~\\ref{code:label}).\nWith repeated cluster updating and clients assignment, \\name can identify the cohorts at scale.\n\n \n\\paragraph{Hierarchical Partitioning}  \n \n  \nWhile online clustering enables us to identify the clusters, we need to partition the cohort sometime accordingly in order to start training specialized models separately.  \nPartitioning in \\name specifically means splitting a cohort into K cohorts to start training over their own members with smaller statistical heterogeneity.\nAfter partitioning, each new cohort starts with the parent cohort model weights with the same architecture, performs conventional FL steps separately, and converges to different model weights. \nThe function \\texttt{PartitionCriteria()} (Line~\\ref{code:decision})  provides the decision to partition the cohort, which is determined by two trade-offs related to model performance in Section~\\ref{sec:system-tradeoff}.\n \n \nSince new clusters may be found after exploring more clients from the large-scale population, \\name will keep identifying and partitioning newly-discovered cohorts through conducting the same algorithm as in function \\texttt{\\name-Clustering} (Line~\\ref{code:func}) independently.\n\n \n  \n \n\\subsection{Cohort Selection}  \n\\label{sec:cold-start}\n\nBecause FL often involves a large training population, more clients participate in model training for the first time than not. \nThe cohort membership of a new client is unknown a priori.\nThis is because \\name neither has access to client data nor has absolute cohort centers that can inform a new client to choose the closest cohort. \nTo address this, \\name adopts an \\emph{exploration-exploitation} strategy to efficiently identify the cohort membership for new participants (Line~\\ref{code:select}).\nGiven a new client, \\name first randomly assigns it to a cohort. \nAfter getting the feedback on how well the client fits in that cohort, \\name attempts to identify a more suitable cohort for it the next time it participates again.\n \n \n\\name uses reward-based decaying $\\epsilon$-greedy selection~\\cite{mab} to help the client find the best-fit cohort (Line~\\ref{code:select}). \nWith an aim to maximize the expected reward for each client, there is a $1- \\epsilon$ probability of selecting a cohort with a maximum reward and a $\\epsilon$ probability of selecting cohorts randomly, where $ \\epsilon \\in[0,1] $ is the exploration factor that decays over time. \nIntuitively, smaller gradient divergence compared to the members within the explored cohort means a better fit and gives a higher reward. Hence, \\name calculates the relative divergence between the clients and the explored cohort center,\nwhich is estimated by averaging the client gradients belonging to the cohort $\\mathcal{P}_{m,Known}^r$, to be \n$ D = || g_m^r(x_{\\mathcal{P}^r_m})  - avg(  g_m^r(x_{\\mathcal{P}^r_{m,  Known}})) ||_2$.\nWe then compare each client's relative gradient divergence with $avg(D)+b \\cdot std(D)$ to show its relationship to the chosen cohort.\nSpecifically, we quantify the instant reward to be $ \\Delta R  =  1 - \\frac{1}{avg(D) + b\\cdot std(D)} D$, where the client with a negative  $\\Delta R$ would be considered as an outlier of the cohort.\nThe choice of $b$ depends on input gradient distribution and expected ratio of outliers, where \\name empirically set $b=1$. \nThen, \\name updates the reward between each client and its explored cohort with a discounting factor $\\gamma$ as  $  R_{ \\mathcal{P}_{m}^r ,m } =  \\gamma *\\Delta R + (1-\\gamma)*  R_{\\mathcal{P}_{m}^r, m}  $.\n \n \n\\paragraph{Efficient cohort exploration.}\nDuring exploration, there may exist multiple cohorts for a client to try out with. \nTo improve the searching efficiency and save device training resources, during both training and deployment, \n\\name enables a new client to perform a binary search to find the most appropriate cohort by predicting the rewards for other unexplored cohorts $m'$ through function \\texttt{ExploreReward()} (Line~\\ref{code:explore}):\n$\n  R_{ \\mathcal{P}_{m}^r ,m' } \\mathrel{{+}{=}} \\frac{  R_{ \\mathcal{P}_{m}^r } }{d(m,m')+1} , \\forall m \\neq m'.\n $\n \nThe intuition behind \\texttt{RewardUpdate()} is that the client may perform similar to or receive similar rewards from the cohorts that are closer\/similar to the previously explored ones, and vice versa.\nThus, we first define the distance ($d$) between two cohorts to be the distance \nto their lowest common ancestral cohorts based on the hierarchical cluster relationship among cohorts.\nGiven an explored cohort $m$ and the reward $\\Delta R_m$ for a participant, \\name calculates the distance $d$ and updates the rewards for unexplored cohorts to be inversely proportional to their distance.\n For example, if a client receives a negative reward for the chosen cohort, then he is more likely to explore another furthest cohort with higher reward given by \\texttt{ExploreReward()} next time. \n  \n \n \n   \n  \n \n \n \n \n \n\\subsection{Cohort-Based Training}\n\\label{sec:system-tradeoff}\n \nTraining separate models for each cohort leads to a new trade-off between resource efficiency and model convergence. \nTo understand the effect of client-level heterogeneity and training resources on model convergence, we analyze the rate of convergence for FedAvg~\\cite{fedavg}, which is the most widely used aggregation algorithm. \nAs prior works have shown ({e.g.\\xspace}, Theorem 1 in SCAFFOLD~\\cite{scaffold}), \nthis convergence rate is largely dominated by heterogeneity, which suggests the promise of cohort-based training.\nHowever, as shown in Figure~\\ref{fig:kmeans}, generating more cohorts has diminishing returns: when the total training resource is constant, creating more cohorts leads to fewer resources for each individual cohort. \nIn contrast, spawning too few can not reduce the intra-cohort client heterogeneity well. \nTherefore, \\name must decide the right number of cohorts to find the sweet spot of better resource efficiency and model convergence.\n\nWe start by analyzing the relationship between heterogeneity and training resources in theory. Inspired by the convergence analysis of FedAvg in SCAFFOLD, we establish the following Lemma:\n\\newtheorem{lemma}{Lemma}\n \n\\begin{lemma}\n\n If the population and training resources are partitioned into up to $K$ cohorts, to theoretically achieve better model convergence, intra-cohort heterogeneity should  be reduced by $\\sqrt{K}$ times \nwhen the training resource $|\\mathcal{P}|$ is larger than $\\alpha \\sqrt{ \\frac{  |\\mathcal{P}_0| }{J_0^2}}$.\n  $\\alpha$ is a constant setting specified in SCAFFOLD that elaborates the relationship between model convergence and training resources.\n\n\\label{lm:res}\n\\end{lemma}\n \nWe elaborate more on the assumptions and proof of Lemma~\\ref{lm:res} in Appendix~\\ref{sec:proof}.\nTo this end, \\name actively monitors the gradient divergence within each potential cohort to decide \\emph{the time of partitioning} and \\emph{the total number of cohorts to generate}.\nBased on Lemma~\\ref{lm:res}, \n\\name automatically decides to partition the population into up to $K$ cohorts and equally allocates training resources to each cohort\nwhen it detects that the intra-cohort heterogeneity would reduce by $\\sqrt{K}$ times.\nAs a result, theoretically, model convergence can be benefited from cohort-based training in \\name.  \nAs for some FL datasets with larger heterogeneity, FL developers can further improve model convergence by dynamically raising the resource budget to allow generating more cohorts.  \n\n \n \n \n  \nFinally, as cohort partitioning may reduce the unique training data for each cohort model, \nthe trade-off between model bias and variance can be affected by the time of partition.\nOn the one hand, hard partitioning of the entire population at the beginning could reduce heterogeneity, but it could also reduce the amount of unique training data for each cohort model, leading to poor model generalizability.\nOn the other hand, late partitioning exposes the model to diverse training data but leads to worse model variance due to high heterogeneity.\nThese also guide the \\emph{reuse} of identified cohorts to facilitate other FL tasks.\n\\name can naturally partition in appropriate times during training following the aforementioned technique to balance this trade-off. \nWe report more results about the effect of partition time on model convergence in Section~\\ref{sec:partition-time}.\n\n\\section{\\name OVERVIEW}%\n\\label{sec:overview}\n \n\\name progressively reduces the intra-group heterogeneity and improves the model performance through cohort identification and cohort-based training toward practical FL.\nIn this section, we introduce the cohort abstraction, provide an overview of how \\name manages cohorts in a distributed fashion and fits into the FL life cycle.\n \n\\subsection{Cohort Abstraction}\n\\label{sec:cohort}\n \nInstead of training only one global model, \\name trains a model separately for each group of FL clients that shares  similar statistical data and model characteristics.\nWe refer to each of these groups, which can perform independent FL training over more homogeneous clients than the overall population, as a \\emph{cohort} $C_m ( m\\in [1,M])$ with two associated properties:\n \n\\begin{denseitemize}\n    \\item A cohort should hold a specialized model that targets data distribution with smaller intra-cohort heterogeneity.    \n    \\item A cohort should have enough members $|C_m|$ to form a meaningful group and deliver the benefit of partition. \n\\end{denseitemize}\nTraditional ({i.e.\\xspace}, cohort-agnostic) FL training has a single cohort with unbounded heterogeneity among the members.\n \n\\subsection{\\name Architecture}\n\\label{sec:arch}\n  \n\n\\name server consists of two primary components (Figure~\\ref{fig:coco}):\n \n\\begin{denseitemize}\n  \\item A logically centralized \\textbf{cohort coordinator} performs three main functions. \n    First, it manages existing cohorts for fault tolerance.\n    Second, it matches clients to their best-fit cohorts.\n    Finally, it monitors the progress of cohort training and identification in order to decide cohort partition when it observes an opportunity for better model convergence .\n\n    \n     \n  \\item A set of \\textbf{cohorts} each performs independent FL training.\n    Each cohort contains traditional FL components such as aggregator and client selector.\n    On top of traditional FL training activities, each cohort continuously identifies its internal composition,  reports its progress to the coordinator and waits for the partition instruction from the coordinator. \n\\end{denseitemize} \n \n \n \n \n \n\\paragraph{FL Lifecycle in \\name}\n As shown in Figure~\\ref{fig:workflow}, following the traditional FL stages in Section~\\ref{sec:back}, \\name adds a matching stage \\circled{0} and a feedback stage \\circled{4} before and after the traditional round. \n \n \n\\begin{denseitemize}\n  \\item[\\circled{0}] \\textbf{Matching stage:} When checking in, clients using \\name optionally include an affinity request (a hint about their cohort preference) to the cohort coordinator.\n   \n    If it took part in the training of one or more cohorts in the past, its preference is dependent on previous feedback. Otherwise, it has no preference.\n    The cohort coordinator forwards the affinity request to the corresponding cohort based on its search algorithm and client's request.\n   \n \n  \\item[\\circled{1}]-\\circled{3} \\textbf{Traditional FL stages:} Each cohort starts a traditional FL training round independently after continuously receiving its client requests from the cohort coordinator. \n    These traditional stages include client selection, training execution, server aggregation, and so on.\n    \n  \\item[\\circled{4}] \\textbf{Feedback stage:}\n  After the traditional FL round finishes, each cohort updates the affinity feedback for its current participants based on the \\name clustering algorithm (\\S\\ref{sec:algo}).\n    Then, each participant receives an affinity feedback -- w.r.t. the cohort it trained with \u2013- and updates the corresponding affinity record for submitting requests in a future round of FL training.\n    During this stage, each cohort also reports its training and identification progress to the cohort coordinator.\n \n\\end{denseitemize}\n \nMore details of systems implementation and distributed protocols are in Appendix~\\ref{sec:system}.\n\n \n \n\\paragraph{Resource management.}\n\n\n\\name jointly maximizes model convergence and resource efficiency in two ways.\nFirst, its scalable cohort identification algorithm does not require extra on-device computation and uses the same amount of resources as traditional FL algorithms(\\S\\ref{sec:prob}- \\S\\ref{sec:cold-start}). \nSecond, it carefully chooses the number of cohorts and time to partition to theoretically guarantee better model convergence and generalizability despite each cohort having less training resources than the previous global model (\\S\\ref{sec:system-tradeoff}).\n  \n\n\n \n\\paragraph{Scalability and fault tolerance.}\n\nCohort management over a large scale population would incur tremendous storage, fault tolerance, and response time overhead.\nThus, \\name designs a soft-state server that offloads cohort-related information to individual clients in order to enable fate sharing -- a failed client will only lose its own information.  \nIf the soft-state server fails, a restarted server only needs to load meta data from disk and receive all necessary information from the clients.\nWe elaborate the design in Appendix~\\ref{sec:dist}-\\ref{sec:robustness}\n  \n\\paragraph{Threat model and robustness.}\nSimilar to the state-of-the-art production FL systems~\\cite{tff-paper,papaya}, \\name considers an \\emph{honest-but-curious} centralized server for aggregation, which can infer any information without interfering with the FL training.\n\\name also assumes that most clients are honest, and only a small fraction can act maliciously under the control of a bad actor~\\cite{FL-poisoning-attacks-response}. \nWe elaborate on how \\name can provide robustness under this threat model along with some experiment results in Appendix~\\ref{sec:robustness}-\\ref{sec:dp}.\n \n \n \n \n \n \n \n\n\n\n\n\\section{CONCLUSION}\n\\label{sec:con}\n\n\nIn this paper, with the observation of the natural groups among real-world FL clients, \\name identifies cohorts with reduced intra-cohort heterogeneity at scale, which addresses the root cause of FL challenges.\n\\name proposes an efficient algorithm and practical system that can be applied under real-world FL constraints to maximally benefit the FL training in terms of model convergence, final accuracy, and model bias.\n\n\n\n\n\n\n\n\\section{EVALUATION}%\n\\label{sec:eval}\n\n\\begin{table}[t!]\n  \\small\n  \\begin{center}\n  \\begin{tabular}{crr}\n  \\toprule \n  Dataset\t& \\#Clients\t& \\#Samples \\\\\n  \\midrule \n      Google Speech~\\cite{google-speech}\t& 2,618\t&\t105K\t\\\\\n      FEMNIST~\\cite{FEMNIST}\t&\t3,400\t&\t640K\t\t\t\\\\\n      OpenImage-Easy \t\t&\t10,133\t&\t1M\t\t\\\\\t\n      OpenImage~\\cite{openimg}\t\t&\t13,771\t&\t1.3M\t\t\\\\\n      Amazon Review~\\cite{amazon}\t&  42,031\t&\t2M\t\t\\\\\n      Reddit~\\cite{reddit}\t&  63,058\t&\t5M\t\t\t\\\\\n  \\bottomrule \n  \\end{tabular}\n  \\end{center}\n \\caption{Statistics of the six datasets in evaluation.}\n  \\label{table:data-stats}\n  \\vspace{-0.8cm}\n\\end{table}\n\n\n\\definecolor{Gray}{gray}{0.9}\n\\newcolumntype{g}{>{\\columncolor{Gray}}c}\n\n\\begin{table*}[ht]\n\\centering\n\\begin{tabular}{ccccgg}\n\\hline\nTask                                   & Dataset                        & Model                                                                                            & Target Acc. & \\name Speedup    & \\name Acc. Impr.   \\\\ \\hline\n                                       & FEMNIST                        & ResNet-18                                                   & 82.2\\%            & $1.2\\times  $                     & 7.3\\%                                   \\\\ \\cline{2-6} \n                                       &                                & MobileNet     & 56.5\\%            & $   1.3\\times  $                     & 4.8\\%                                   \\\\ \\cline{3-6} \n                                       & \\multirow{-2}{*}{OpenImg}      & ShuffleNet      & 58.2\\%            & $   2.2\\times  $                     & 5.0\\%                                   \\\\ \\cline{2-6} \n                                       &                                & MobileNet                                        & 65.4\\%               & $ 1.4 \\times  $                       & 3.4\\%                                      \\\\ \\cline{3-6} \n\\multirow{-5}{*}{Image Ccalassification} & \\multirow{-2}{*}{OpenImg-Easy} & ShuffleNet                                       & 64.8\\%               & $1.2\\times  $                       & 4.4\\%                                      \\\\ \\hline\n                                       & Amazon Review                  & Logistic Regression                                                                              & 65.3\\%               & $ 1.2 \\times   $                      & 8.2\\%                                      \\\\ \\cline{2-6} \n\\multirow{-2}{*}{Language Modeling}    & Reddit                         & Albert                                             & 7 perplexity      & $   1\\times  $                     & 0 perplexity                                    \\\\ \\hline\nSpeech Recognition                     & Google Speech                  & ResNet-34                                                                                        & 78.5\\%            & $   1.5\\times  $                     & 5.7\\%                  \\\\ \\hline\n                     \n\\end{tabular}\n  \\caption{Summary of improvements on time to accuracy. \n    We tease apart the overall improvement with statistical and system ones, and take the highest accuracy that YoGi can achieve as the target, which is moderate due to the high task complexity and lightweight models. } \n  \\label{table:e2e-perf}\n\\end{table*}\n\n\n\n\\begin{figure*}[t!]\n  \\centering\n \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{openimg.pdf}\n    \\caption{Yogi}%\n    \\label{fig:yogi}\n  \\end{subfigure}\n      \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{qfedavg.pdf}\n    \\caption{q-Fedavg}%\n    \\label{fig:qfedavg}\n  \\end{subfigure}\n    \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{prox.pdf}\n    \\caption{FedProx}%\n    \\label{fig:prox}\n  \\end{subfigure}\n     \n \n \n \n \n \n \n    \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{pyramid.pdf} \n    \\caption{PyramidFL + YoGi }\n  \\label{fig:pyramid}\n  \\end{subfigure}\n   \\vspace{-0.2cm}\n  \\caption{\\name with different  FL algorithms. }\n  \\label{fig:diff-algo}\n  \\vspace{-0.4cm}\n   \\end{figure*}\n\n\n \n\nWe evaluate \\name's effectiveness for six different ML tasks as well as different choices of FL  algorithms.\nOur evaluation shows the following key highlights:\n\n\\begin{denseitemize}\n\\item \\name  speeds up model convergence on different FL datasets up to 2.2$\\times$, while improving final test accuracy by 3.4\\%-8.2\\%\n\n\\item \\name  cooperates with existing FL efforts ({e.g.\\xspace}, personalization) and boosts final test accuracy by 2.1\\%--6.7\\%\n\n\\item \\name can mitigate model bias \nacross devices by 19\\% on average and improve resource efficiency. \n\n\\item \\name outperforms existing clustered FL algorithms up to 4.8$\\times$ in terms of time and 5.2$\\times$ in terms of resources.\n\n\n\\item \\name performs well across a broad range of its parameter settings.\n\n\\end{denseitemize}\n\n\n\n\\subsection{Experiment Setup}\n\\paragraph{Evaluation environment}\nWe use 24 NVIDIA Tesla P100 GPUs on CloudLab~\\cite{cloudlab} to emulate the large-scale client training in our evaluations. \nThe client data distribution follows the real-world partition, where client data can vary in quantities, data, and label distribution.\nWe use an open-source benchmark~\\cite{oort,fedscale} with standardized setup and report the simulated wall clock time by relying on realistic FL system and data traces, including the FedScale  device availability and device speed trace in simulating FL client behaviors.\n\n\n\n\\paragraph{Datasets and models}\nWe run three categories of applications with six FL datasets~\\cite{fedscale} of different scales using real-world partitions, whose statistics are reported in Table~\\ref{table:data-stats}.\nEach of the dataset has realistic data partition among clients.\n\\begin{inlineenum}\n\\item \\emph{Speech Recognition}: \nWe train Resnet-34~\\cite{resnet}        on a small-scale Google Speech dataset with 35 types of commands.  \n\n\\item \\emph{Image Classification}: \nWe train Resnet-18 on small-scale FEMNIST with 62 handwritten digits to classify.\nAlso, we train ShuffleNet~\\cite{shufflenet} and MobileNet~\\cite{mobilenet} on middle-scale OpenImage with 596 classes to classify, whereas OpenImage-Easy only has 60 classes.\n\n\\item \\emph{Language Modeling}: \nWe train logistic regression on middle-scale Amazon Review to predict review ratings, and Albert model~\\cite{albert} on large Reddit for word prediction.\n\\end{inlineenum}\n\nThese applications are widely used in real end-device applications~\\cite{mobile-app}, and these models are lightweight.\n\n\n\\paragraph{Parameters}\nWe follow the standardized experiment and parameter settings in FedScale. \nWe adopt an over-commitment strategy to mitigate stragglers which allow 25\\% failures or stragglers every round as in real FL deployments~\\cite{tff-paper}.\nWe set the number of participants per round to be 200, the local minibatch size to be 6, and\nthe initial learning rate  to be 4e-5 for the Albert model, and 0.05 for other models. \nAnd we use the linear scaling rule~\\cite{lr} to scale the learning rate after partition.\n\n\n\\paragraph{Metrics}\nThe \\emph{time-to-accuracy} performance, \\emph{final test accuracy}, and \\emph{model bias} are our key metrics. \nWe use the cohort member's test data, which follows the realistic data partition, to evaluate each cohort model.\nThe test data would be the global test data if we end up with one global model.\nFor each experiment, we report the average  top-1 accuracy based on the results over 3 runs.\n\n\\subsection{End-to-End Performance}\n\\label{sec:e2e}\n\n\\paragraph{\\name's performance on different datasets.}\n\nWe first evaluate \\name's performance on different real-world FL datasets.   \nIn the following experiments, we adopt YoGi as the FL algorithm because it outperforms other FL algorithms most of the time.\nTable~\\ref{table:e2e-perf} summarizes the key time-to-accuracy performance of all datasets. \nWe quantify the time-to-accuracy as speedup by \\name, which measures how many times \\name can speed up to achieve the target accuracy compared to the baseline time cost. \nIn Appendix~\\ref{sec:adde2e}, Figure~\\ref{fig:end-to-end} reports the timeline of training to achieve different accuracy, as different cohorts perform FL asynchronously. \n\nWe notice that \\name speeds up the wall-clock time to reach target accuracy up to $2.2 \\times $ faster.\nMoreover, the final accuracy for different datasets is improved by 3.4\\%--8.2\\%.\nThe benefit of \\name varies over datasets.\nFor most of the datasets, \\name can achieve significant final accuracy improvement.\nNevertheless, \\name does not improve Reddit task because the clients' texting behavior is similar to each other that makes it hard to identify significant groups as shown in Figure~\\ref{fig:kmeans}.\nIn order to maximize the benefit of clustering in FL training, \\name decides not to partition into multiple cohorts as a result.\n   \n   \n   \n   \n \\paragraph{\\name's performance on different FL algorithms.}\n\nWe then evaluate \\name's performance on ShuffleNet-OpenImage with different FL Algorithms, which are complementary to \\name. \nWe refer to YoGi running atop \\name as YoGi+\\name, and similarly for FedProx, q-FedAvg and PyramidFL+YoGi.\n\n\nAs shown in Figure~\\ref{fig:diff-algo},\n \\name speeds up the time to reach the target accuracy of baseline algorithms, from $1.2\\times$ to $2.2 \\times$ faster and improve the final test accuracy by 3\\%--6.8\\%.\n\n\nAs for the personalization algorithm FTFA, we adopt the cohort models generated by \\name to conduct local training using FTFA on corresponding cohort members. \nIn addition to faster convergence of the initial model, \\name also improves the average test accuracy of FTFA from 63.18\\% to 67.40\\% with local fine-tuning.\n\n\n   \n   \n \n  \n   \\vspace{-0.4cm}\n\n \\paragraph{\\name's benefit on model bias.}\n\n\n \nWe show that \\name can also mitigate the model bias due to smaller intra-cohort statistical heterogeneity.\nWe report the variance of the final accuracy distributions, the worst and best 10\\% test accuracy in Appendix~\\ref{sec:addbias} Table~\\ref{table:bias}.\nOur experiment show that the variance of test accuracy is decreased across all devices for all the datasets by 19\\% on average.\n\n\n\n\n\n   \\vspace{-0.4cm}\n\n \n \n\\paragraph{\\name's benefit on resource efficiency.}\n\nWe finally show that \\name can optimize resource efficiency on OpenImg dataset by saving 55\\% training resources.\nWe also account for the affinity maintaining overhead into the client resource usage, which is around 0.02\\% of the total resource consumption.\nAs shown in Figure~\\ref{fig:resource}, \\name achieves higher resource efficiency about 2.2$\\times$ over baseline. \n \n\n\\begin{figure*}[t]\n\n\n\\begin{minipage}[t]{0.24\\textwidth}\n\\centering\n  \\includegraphics[scale=0.3]{resource.pdf} \n    \\caption{Resource Efficiency. }\n  \\label{fig:resource}\n   \\end{minipage}\n\\begin{minipage}[t]{0.77\\textwidth}\n  \\centering\n   \\begin{subfigure}[t]{0.3\\textwidth}\n   \\centering\n     \\includegraphics[trim=0 0 0 0,clip,scale=0.28]{heter_fair_acc_auxo.pdf}\n   \\caption{Different degrees of heterogeneity.}\n    \\label{fig:diff-heter}   \n  \\end{subfigure} \n  \\begin{subfigure}[t]{0.28\\textwidth}\n  \\centering\n      \\includegraphics[scale=0.28]{partition-time-1.pdf}\n     \\caption{Different partition time (FEMNIST).}\n     \\label{fig:conf} \n   \\end{subfigure}\n   \\begin{subfigure}[t]{0.3\\textwidth}\n \\centering\n    \\includegraphics[scale=0.28]{num_cohorts.pdf}\n    \\caption{Different number of cohorts (OpenImg). }\n    \\label{fig:impact-cohort} \n  \\end{subfigure}  \n      \\caption{Sensitivity analysis. }\n      \\end{minipage} \n   \\end{figure*}\n   \n\n\n\\subsection{Clustered FL Comparison}\n\nWe compare \\name with four existing clustered FL algorithms CFL, FL+HC, FlexCFL, and IFCA in terms of three metrics: time-to-accuracy, resource-to-accuracy, and final accuracy.\nSince these algorithms do not meet some real-world FL constraints (Table~\\ref{table:comparison}), we simplify the settings accordingly.\n\n\n\nWe compare with CFL  in small-scale settings ($\\sim 100$ clients) from the FEMNIST dataset to meet their full participation assumption. \nWe observe little difference between CFL, \\name, and baseline ({i.e.\\xspace}, no cohorts) in terms of time and resources used due to the absence of significant clusters within small populations.\nHowever, this highlights the need for large-scale FL settings, where CFL cannot even be applied as it does not support partial participation.\n \n\nTo compare with FL+HC, FlexCFL and IFCA, we conduct experiments with the full FEMNIST and Amazon Review datasets \\emph{without} the client availability traces to align with their constraints.\nAs shown in Table~\\ref{table:relatedexp} and Appendix~\\ref{sec:addcfl}, \n \\name achieve better time efficiency $1.4\\times-4.8\\times$ and better resource efficiency  $1.3\\times-4.8\\times$  compared to the related works especially for the large-scale Amazon dataset, due to our efficient and scalable algorithm design. \n\nAlso, our result for IFCA are consistent with  Motley~\\cite{motley}.\n \n\n  \n\n\n \n \\begin{table}[]\n  \\vspace{-0.5cm}\n\\centering\n\\resizebox{\\columnwidth}{!}{\n\\begin{tabular}{lc|\n>{\\columncolor[HTML]{FFFFFF}}c ccc}\n\\hline\n                                               & \\multicolumn{1}{l|}{}                  & {\\color[HTML]{000000} FL+HC}                               & FlexCFL                             & IFCA                                & \\name                \\\\ \\hline\n\\multicolumn{1}{l|}{}                          & \\cellcolor[HTML]{EFEFEF}Speedup      & \\cellcolor[HTML]{EFEFEF}{\\color[HTML]{000000} $1.7\\times$} & \\cellcolor[HTML]{EFEFEF}$1.3\\times$ & \\cellcolor[HTML]{EFEFEF}$0.5\\times$ & \\cellcolor[HTML]{EFEFEF}$2.4\\times$ \\\\\n\\multicolumn{1}{l|}{}                          & Efficiency                          & {\\color[HTML]{000000} $1.6\\times$}                         & \\cellcolor[HTML]{FFFFFF}$1.8\\times$ & $0.5\\times$                         & \\cellcolor[HTML]{FFFFFF}$2.4\\times$ \\\\\n\\multicolumn{1}{l|}{\\multirow{-3}{*}{FEMNIST}} & \\cellcolor[HTML]{EFEFEF}Final acc. & \\cellcolor[HTML]{EFEFEF}{\\color[HTML]{000000} 5.8\\%}      & \\cellcolor[HTML]{EFEFEF}7.1\\%       & \\cellcolor[HTML]{EFEFEF}1.3\\%       & \\cellcolor[HTML]{EFEFEF}9.1\\%       \\\\ \\hline\n\n\n\\multicolumn{1}{l|}{~Amazon}                    & Speedup                              & {\\color[HTML]{000000} $0.4\\times$}                         & $ 0.4\\times$                         & \\cellcolor[HTML]{FFFFFF}$0.5\\times$ & $2.3\\times$                         \\\\\n\\multicolumn{1}{l|}{~ Review}                    & \\cellcolor[HTML]{EFEFEF}Efficiency  & \\cellcolor[HTML]{EFEFEF}{\\color[HTML]{000000} $0.4\\times$} & \\cellcolor[HTML]{EFEFEF}$0.5\\times$ & \\cellcolor[HTML]{EFEFEF}$0.5\\times$ & \\cellcolor[HTML]{EFEFEF}$2.1\\times$ \\\\\n\\multicolumn{1}{l|}{}                          & Final acc.                          & {\\color[HTML]{000000} -2.9\\%}                              & -2.7\\%                               & 0.6\\%                               & 5.4\\%                               \\\\ \\hline\n\\end{tabular}\n}\n\\caption{Summary of improvements over baseline ({i.e.\\xspace}, no cohorts) in terms of time, resource and accuracy.  } \n\\label{table:relatedexp}\n   \\vspace{-0.4cm}\n\\end{table}\n\n\n\n\\subsection{Sensitivity Analysis }\n\\label{sec:partition-time}\n\n\n\n\\paragraph{Impact of different degrees of heterogeneity.}\nWe generate different statistical heterogeneity by applying affine shift~\\cite{affine} on OpenImage, then we evaluate \\name with YoGi across different degrees of statistical heterogeneity. \nFigure~\\ref{fig:diff-heter} reports the final test accuracy as well as top 10\\% and worst 10\\% client test accuracy on different degrees of heterogeneity.\nWe observe that \\name can improve model accuracy and mitigate model bias under different degrees of heterogeneity.\nMoreover, similar to the previous experiment, \\name achieves faster time-to-accuracy performance from  $1.2\\times$ to $1.8 \\times$.\n    \n\n \\paragraph{Impact of time to partition. } \n We investigate the impact of different cohort partition time on the model convergence.\nAs mentioned in Section~\\ref{sec:system-tradeoff}, the partition time relates to the trade-off between model generalizability and intra-cohort heterogeneity.\nAs shown in Figure~\\ref{fig:conf}, we choose different partition times with the same cohort composition and report the test accuracy to time performance on FEMNIST. \nWe observe that cohort-based training all outperform the baseline experiment with one cohort.\nHowever, early partition as FlexCFL and IFCA is worse than intermediate partition, because it sacrifices the model generalizability. \nSimilarly, late partition after convergence as CFL does not outperform intermediate partition, because it slows down the model convergence to a smaller heterogeneous population.\n \n\n\n \n\\paragraph{Impact of the number of cohorts.}\nWe investigate the impact of the number of cohorts generated by \\name, which relates to the trade-off between training resources and intra-cohort heterogeneity (\\S\\ref{sec:system-tradeoff}).\nAs shown in Figure~\\ref{fig:impact-cohort}, we observe that the model convergence is negatively affected once the number of cohorts exceeds 4 under the same resource budget.\nBy further comparing the reduce of heterogeneity with different number of cohorts indicated in Figure~\\ref{fig:kmeans}, \nthis result verifies that better model convergence can be achieved as long as the heterogeneity can proportionally compensate the reduced training resources\n\n\n \n   \n   \n  \n \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n \n\n\n\n\n\n\n\\section{IMPLEMENTATION}\n\\label{sec:impl}\n\nWe have implemented \\name as an independent Python library ($1,664$ lines) to serve existing FL frameworks (e.g., TFF~\\cite{tff} and PySyft~\\cite{pysyft}), and integrated it with FedScale~\\cite{fedscale} for evaluations.\n\\name abstracts away the cohort identification and partition so that FL developers can easily try out their FL algorithms or datasets on top of \\name without any modifications. \n\n\n\\name's implementation consists of the three components described in Section~\\ref{sec:overview}: \nThe cohort coordinator manages and spawns cohort processes, which initiate FL training tasks.\nClients continuously submit their training requests based on their availability and affinity records.\nThen, the cohort coordinator takes client training requests as input and forwards the requests to corresponding cohorts.\nEach cohort process conducts conventional FL training with the assigned available clients independently.\nAt the end of each individual round, the \\name clustering algorithm runs within every cohort and reports clustering results to each participant over the network.\nAll training metadata and model weights are checkpointed periodically for fault tolerance.\nMeanwhile, the cohort coordinator continuously monitors the progress of cohorts for resource management and failure recovery. \n\n\n\n\\section{Proof of Lemma~\\ref{lm:res}}\n \\label{sec:proof} \n \n\n \n  We first make precise some definitions that are related to the proof from SCAFFOLD and then see the proof of Lemma~\\ref{lm:res}. \n    \n \\subsection{Additional definitions}\n \n \\paragraph{Assumption 1.}\n $g_i(w)$ is unbiased stochastic gradient of $f_i$ with bounded variance, where $f_i$ represents the loss function on client $i$.\n \n $$\n\\mathbb{E}_{x_i} [ ||\tg_i (w) - \\nabla f_i (w)\t||^2  ] \\leq \\sigma^2, \\forall i,x.\n $$\n\n where $w$ is the aggregated server model.\n  Note that $\\sigma$ only bounds the variance within clients not across clients.\n   \\paragraph{Assumption 2.}\n$\\{ f_i \\} $ are $\\beta$-smooth and satisfy:\n$$\n||\\nabla f_i(w) - \\nabla f_i(v)|| \\leq \\beta ||w-v||, \\forall i, w, v.\n$$\n\n\n\n      \\paragraph{Assumption 3.}\n\t$f_i$ is $\\mu$-convex for $\\mu\\geq0 $ and satisfies:\n   $$\n   \t\\langle  \\nabla f_i(w) , v-w\\rangle \\leq -(\\nabla f_i(w) - \\nabla f_i(v) +\\frac{\\mu}{2}||w-v||^2), \\forall i, w, v.\n   $$ \n   \n\n   \n\n   \\paragraph{Assumption 4.} \n(G, B)-BGD or Bounded Gradient Similarity: there exist constants $G\\geq0$ and $B\\geq1$ such that\n $$\n \\frac{1}{N}\\sum_{i=1}^{N}|| \\nabla f_i(w)||^2 \\leq G^2+B^2 \\nabla f(w) ), \\forall w.\n $$\n   \n \\subsection{Theoretical Results}\n\n \\paragraph{ Lemma 1.}\n If the population and training resources are partitioned into up to $K$ cohorts, to theoretically achieve better model convergence, intra-cohort heterogeneity should  be reduced by $\\sqrt{K}$ times \nwhen the training resource $|\\mathcal{P}|$ is larger than $\\alpha \\sqrt{ \\frac{  |\\mathcal{P}_0| }{J_0^2}}$.\n  $\\alpha$ is a constant setting specified in SCAFFOLD that elaborates the relationship between model convergence and training resources.\n \n \n \\paragraph{ \\textit{Proof.} }\n    \n   We first borrow the proof of convergence analysis on FedAvg (Theorem 1) from SCAFFOLD following the same assumptions mentioned above: \n\n$$\n\\mathbb{E}[ f(w^R)] - f(w^*) \\leq 3||w^0-w^*||^2\\mu e^{-\\frac{\\widetilde{\\eta}}{2} R } \n$$\n\\vspace{-0.4cm}\n$$\n + \\widetilde{\\eta} (\\frac{2\\sigma^2}{kP} (1+\\frac{P}{\\eta^2_g}) +\\frac{8G^2}{P}(1-\\frac{P}{N})  )\n +  \\widetilde{\\eta}^2(36\\beta G^2), \n$$\n\\vspace{-0.2cm} \n$$\n\\forall \\frac{1}{\\mu R}  \\leq \\widetilde{\\eta} \\leq \\frac{1}{8(1+B^2)\\beta}\n$$\n\nwhere P denotes the training resources, \nk is the number local steps, \n $\\eta_l$ is the local step-size, \n $\\eta_g$ is the global step-size \n and $\\widetilde{\\eta} = k \\eta_l \\eta_g$ is the effective step-size\n \n \n Since we only care about the effect of training resources $P$ and heterogeneity $G$ on the convergence analysis, we further simplify the right hand side equation to be \n $$\n h(P, G) =  \\frac{\\theta}{P} + \\gamma \\frac{G^2}{P} + \\rho G^2 +\\xi \n $$\n where $ \\theta, \\gamma, \\rho$ and  $\\xi$ are constant settings.  \n   Since we proportionally partition the population and training resources, we can assume $ (1-\\frac{S}{N})$  to be constant before and after partition.\n   \n In order to have no worse model convergence bound after partitioning, we need $h(P, G)$ to be non-increasing with the reduce of training resources $P$.\n  As proposed in Lemma~\\ref{lm:res}, \\name partitions $K$ cohorts when the intra-cohort heterogeneity can be reduced by $\\sqrt{K}$ times, which approximately give  $\\frac{G^2}{P}$ be constant as the one before partition $\\frac{G_0^2}{P_0}$.\n By substituting this relationship into $h(P, G)$, we can derive the lower bound for the range of training resources required to achieve better convergence bound:\n $$\n P \\geq \\sqrt{ \\frac{\\theta P_0  }{G_0^2\\rho}} \n = \\sqrt{\\frac{\\sigma^2}{18 k  \\widetilde{\\eta}^2\\beta}   \\frac{P_0}{G_0^2}} = \\alpha\n $$\n \n \n \\section{\\name System Design}%\n\\label{sec:system}\n\nIn this section, we discuss how to design a scalable and robust system on top of the clustering algorithm under real-world challenges.\n\n  \n\\subsection{Distributed Implementation of Cohort Clustering}\n\\label{sec:dist} \n\nAs the scale of training grows, the server faces more server challenges for tremendous storage, fault tolerance, and response time in order to maintain the cohort information.\nThus, \\name designs a solution to use a soft-state server that offloads cohort-related information to individual clients to mitigate the challenges.\nIn this subsection, we describe how to implement the proposed clustering algorithm in a distributed fashion, while achieving the same objective. \n\n\nFirstly, we introduce \\emph{affinity message}, which is a lightweight message containing all necessary \nstate information needed to identify cohorts in a distributed fashion.\nAffinity message consists of  two pieces of information between a client and a cohort  to enable efficient state transmission: (\\emph{Reward} $R\\in \\mathbb{R}$, \\emph{Cluster index} $L\\in [0, K)$).\nThe \\emph{reward} implies how well the client fits for this cohort.\nThe \\emph{cluster index} expresses the client's cluster membership within this cohort and is used to indicate its future cohort index. \n\n\\begin{figure}[t!]\n  \\centering\n  \\includegraphics[trim=0 160 0 0,clip,scale=1]{stateless.pdf} \n    \\caption{Scalable Design Overview\n  \\textbf{a.} Cohort affinity feedback.  \\textbf{b.} Client affinity request.  \\textbf{c.}  Cohort coordinator request match.\n    }\n  \\label{fig:stateless}\n\\end{figure}\n\n\nThrough exchanging affinity messages between different components, \\name encourages similar clients to collaborate more in a distributed fashion.\nAs shown in Figure~\\ref{fig:stateless}, we next describe\n\\circled{a} how a cohort informs its relationship with its participants, \n\\circled{b} how clients request for their preferred cohort based on the affinity feedback\nand \\circled{c} how the cohort coordinator matches different requests.\n\n\n\n\n\\paragraph{Affinity Feedback}\n\nAt the end of each round, every cohort computes the affinity feedback to inform participants about their relationship with the cohort.\nThese affinity feedback correspond to the clustering results returned by Algorithm~\\ref{algo:all} Line~\\ref{code:reward} (reward $R$) and Line~\\ref{code:label} (cluster index $L$).\nThese clustering results would be sent back to the participants respectively in the format of affinity messages,\nwhich informs the participant about whether the cohort is a good fit and which sub-cohort to select after partitioning.\n\n\\paragraph{Client Reaction }\n\nAfter receiving the affinity feedback from the cohort, the client would update its affinity records itself based on the equation in Algorithm~\\ref{algo:all} Line~\\ref{code:exploit}-~\\ref{code:explore}\n and copy the cluster index directly.\nFollowing the same decaying $\\epsilon-$greedy selection method (\\S\\ref{sec:cold-start}), clients select the cohort to train by themselves.\nThen, clients ready to participate would submit the corresponding affinity request to the cohort coordinator.\n\n\n\\paragraph{Request Match} \n\nAfter receiving the affinity request,  the cohort coordinator matches each client to the cohort it requests.\nNote that only the leaf cohort in the cohort tree would be returned as it conducts actual FL training inside.\nHowever, sometimes the requested cohort may not be the leaf cohort because some clients may not be aware of the cohort partitioning, which is not yet transparent to all clients. \nThus, the cohort coordinator should assist clients to select their best-fit cohort through finding the closest leaf cohort indicated by the requested cohort and cluster index in the affinity message.  \n\n \nAfter finding a proper cohort, cohort coordinator would forward this affinity request to the corresponding cohort to initiate traditional FL rounds. \nMoreover, these forwarded affinity requests provide each cohort with all necessary input to conduct the clustering algorithms.\nThus, after receiving the gradients from its participants, each cohort is able to run the Algorithm~\\ref{algo:all} independently to compute the aforementioned affinity feedback. \n\n\\subsection{Fault Tolerance}\n\\label{sec:resilience}\n\n\\name enables fast recovery to minimize the impact on the model training.\nUpon a cohort process failure in the server, the cohort coordinator spawns a new cohort process.\nThe new cohort loads the model from the latest checkpoint and restarts the incomplete round.\n\nIf the cohort coordinator fails, cohort processes would continue their current independent FL training and wait until a new cohort coordinator to be re-spawned.\nClients checking in within that recovery period would be ignored.\n\nFinally, \\name is resilient to client failures just like traditional FL by design. \nMost client failure handlers, which are orthogonal to \\name, can be applied directly.\nIn addition, a failed client, who may lose its own affinity records, would restart exploring again.\nWe empirically show that \\name can tolerate a certain amount of such client failures while continuing to benefit the FL training (\\S\\ref{sec:dp}).\n\n\\subsection{Robustness}\n\\label{sec:robustness}\n\nBased on \\name's threat model, \\name can naturally cooperate with some existing privacy-preserving approaches~\\cite{ldp,dprnn,recldp} to address potential threats from both the server and clients.\nTo handle the honest-but-curious server, \\name can be used with local differential privacy (LDP), which is used to provide user-level privacy guarantees.\nSince differential privacy is immune to post-processing~\\cite{dpbook} and \\name's clustering is post-processing, \\name incurs no additional privacy loss.\n\n\nTo handle a small fraction of unreliable clients~\\cite{malicious1,malicious2}, \\name can be used with existing adversary-resilient solutions~\\cite{resilient4,resilient3}.\nFor \\name-specialized adversaries, such as fake affinity requests,\n\\name detects anomalies by comparing its position in the cluster with its claimed affinity  (Algorithm~\\ref{algo:all} Line~\\ref{code:reward}). \nFor example, if a client claims high reward but is actually far away from the cohort center, \\name will detect and blacklist it.\nIn Appendix~\\ref{sec:dp}, we empirically evaluate \\name's robustness under these scenarios.\n\n  \n\\subsection{System  Assessment }\n\\label{sec:dp}\n\n\\begin{figure*}[t!]\n\\begin{minipage}[t]{0.94\\textwidth}\n  \\centering  \\begin{subfigure}[t]{0.31\\textwidth}\n    \\centering\n    \\includegraphics[trim=0 0 0 0,clip,scale=0.3]{differential.pdf}\n\\vspace{-0.1cm}\n    \\caption{Local DP. }%\n    \\label{fig:dp}\n  \\end{subfigure}\n  \\begin{subfigure}[t]{0.31\\textwidth}\n    \\centering\n    \\includegraphics[trim=0 0 0 0,clip,scale=0.3]{malicious.pdf}\n\\vspace{-0.1cm}\n    \\caption{Corrupted client.}%\n    \\label{fig:malicious}\n  \\end{subfigure}\n  \\begin{subfigure}[t]{0.31\\textwidth}\n    \\centering\n    \\includegraphics[scale=0.3]{failure.pdf}\n\\vspace{-0.1cm}\n    \\caption{Client affinity loss.}\n    \\label{fig:client-fail}\n  \\end{subfigure}\n    \\caption{Robustness of \\name under different scenarios. }\n   \\end{minipage}\n\\end{figure*}\n\n\n\\paragraph{Impact of differential privacy.}\n\n\n\\name is robust to local differential privacy (LDP). \nLDP is used to protect user-level privacy by adding Gaussian noise to the client update before sending it to the server, but it hurts model accuracy.\nWe evaluate \\name's performance under LDP for a learning task on the Amazon Review dataset.\nTo achieve ($\\epsilon, \\delta$)-differential privacy, where $\\delta = 10^{-6}$ based on the training scale and $\\epsilon = 2,4,8$, we set the noise scale $\\sigma = 1.0, 0.77, 0.6$. \nAs shown in Figure~\\ref{fig:dp}, \\name can still benefit FL training across different differential privacy guarantees.\n \n\n\n\\paragraph{Impact of malicious attacks.}\n\nWe investigate the robustness of \\name by manually involving corrupted clients. \nFollowing a popular adversarial ML setting that introduces local model poisoning \\cite{poison-fl}, we randomly flip the ground-truth data labels for these corrupted clients. \nAs shown in Figure~\\ref{fig:malicious}, we introduce different percentages of corrupted clients to the OpenImg task.\nWe set the percentage of corruption below 15\\%, which is a practical percentage under the real-world setting~\\cite{poison}.\nWe observe that \\name still improves performance across different degrees of corruption through identifying malicious clients and eliminating their interference.\n\n\n\n\\paragraph{Impact of unstable client.}\n\nFinally, we show \\name is robust with unstable clients who fail to maintain their affinity records, which may result in less accurate clustering results. \nWe consider loss rates from 0\\% to 20\\% and report the corresponding final test accuracy in Figure~\\ref{fig:client-fail}. \nWe notice \\name outperforms the baseline across different affinity loss rates.\n\n\n\n\n\n\n\\section{Additional Experiment Results}\n\\label{sec:addexp}\n\\subsection{\\name End-to-End Performance Plot}\n\\label{sec:adde2e}\nFigure~\\ref{fig:end-to-end} reports the timeline of training to achieve different accuracy, as different cohorts perform FL asynchronously. \nThe shaded portion covers the test accuracy among all cohorts generated by \\name.\n\n\\begin{figure*}[t!]\n  \\centering\n \\begin{subfigure}{1.62in}\n    \\centering\n    \\includegraphics[scale=0.3]{openimg.pdf}\n    \\caption{ShuffleNet (OpenImg) }%\n    \\label{fig:openimg1}\n  \\end{subfigure}\n  \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{mobile-openimg}\n    \\caption{MobileNet (OpenImg)}%\n   \\label{fig:openimg2}\n  \\end{subfigure}\n    \\begin{subfigure}{1.62in}\n    \\centering\n    \\includegraphics[scale=0.3]{easy-shuffle.pdf}\n    \\caption{ShuffleNet (OpenImg-Easy)}%\n    \\label{fig:easy1}\n  \\end{subfigure}\n    \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{easy-mobile.pdf}\n    \\caption{MobileNet (OpenImg-Easy)}%\n    \\label{fig:easy2}\n  \\end{subfigure}\n  \n \\begin{subfigure}{1.62in}\n    \\centering\n    \\includegraphics[scale=0.3]{amazon.pdf}\n    \\caption{Logistic Regression (Amazon) }%\n    \\label{fig:openimg}\n  \\end{subfigure}\n  \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{femnist.pdf}\n    \\caption{ResNet (FEMNIST)}%\n   \\label{fig:femnist}\n  \\end{subfigure}\n    \\begin{subfigure}{1.62in}\n    \\centering\n    \\includegraphics[scale=0.3]{speech.pdf}\n    \\caption{ResNet (Google Speech)}%\n    \\label{fig:speech}\n  \\end{subfigure}\n    \\begin{subfigure}{1.6in}\n    \\centering\n    \\includegraphics[scale=0.3]{reddit.pdf}\n    \\caption{Albert (Reddit)}%\n    \\label{fig:reddit}\n  \\end{subfigure}\n  \\caption{Time-to-Accuracy performance on different dataset. \n  For the language modeling (LM) task, a lower perplexity is better.\n  The solid line reflects the average test accuracy.\n  The shaded portion covers the test accuracy performance among all cohorts generated by \\name.}\n     \\label{fig:end-to-end}\n  \\end{figure*}\n\n\\subsection{\\name Benefit on Model Bias}\n\\label{sec:addbias}\n\nWe show that \\name can also mitigate the model bias, as the model bias is partially raised by the statistical heterogeneity, which is mitigated within cohorts.\n\n\\begin{table}[t]\n\n\\resizebox{\\columnwidth}{!}{\n\\begin{tabular}{c|c|ccc}\nDataset               & \\multicolumn{1}{l|}{Setting} & \\begin{tabular}[c]{@{}c@{}}Worst 10\\% \\\\ (\\%)\\end{tabular} & \\begin{tabular}[c]{@{}c@{}}Best 10\\% \\\\ (\\%)\\end{tabular} & Variance   \\\\ \\hline\n\\rowcolor{Gray}\nOpenImg               & \\name                  & 38                                 & 83                                        & 267   \\\\\n\\multicolumn{1}{l|}{} & Baseline              & 34                                      & 79                                               & 296   \\\\ \\hline\n\\rowcolor{Gray}\nOpenImg               & \\name                  & 38                                    & 88                         & 234    \\\\\n-Easy                 & Baseline              & 33                                           & 84                                    & 273    \\\\ \\hline\n\\rowcolor{Gray}\nReview                & \\name                  & 50                                         & 100                                     & 460   \\\\\n\\multicolumn{1}{l|}{} & Baseline              & 32                               & 100                                      & 995   \\\\ \\hline\n\\rowcolor{Gray}\nFEMNIST               & \\name                  & 63                                        & 97                                      & 171   \\\\\n\\multicolumn{1}{l|}{} & Baseline              & 60                                         & 93                                              & 185   \\\\ \\hline\n\\rowcolor{Gray}\nSpeech                & \\name                  & 57                                   & 100                                      & 479  \\\\\n\\multicolumn{1}{l|}{} & Baseline              & 52                                        & 100                                          & 503  \\\\ \\hline\n\\end{tabular}\n}\n\\caption{Summary of improvements on model bias.} \n\\label{table:bias}\n\\end{table}\n\n\n\\subsection{Clustered FL Comparison}\n\\label{sec:addcfl}\nWe compare \\name with related clustered FL works in terms of time-to-accuracy, resource-to-accuracy, and final accuracy performance using FEMNIST and Amazon dataset.\nAs shown in Figure~\\ref{fig:addcfl}, \\name achieve better time efficiency $1.4\\times-4.8\\times$ and better resource efficiency  $1.3\\times-4.8\\times$ needed to reach the target accuracy.\n\n\n\n \n \n\\begin{figure}[t!]\n  \\centering\n     \\begin{subfigure}{1.6in}\n  \\centering\n   \\includegraphics[scale=0.3]{cfl-femnist-time.pdf} \n     \\caption{Accuracy-Time (FEMNIST)} \n  \\end{subfigure}\n     \\begin{subfigure}{1.6in}  \n   \\centering \n   \\includegraphics[scale=0.3]{cfl-femnist-res.pdf} \n     \\caption{Accuracy-Resource (FEMNIST)} \n     \\end{subfigure} \n    \\caption{Comparison with clustered FL works. }\n \\label{fig:addcfl}\n \\end{figure}\n \n \n \n\n \n \\section{Related Work}\n  \\label{sec:related}\n\n\\paragraph{Distributed Machine Learning}\n\n\nDistributed ML in data centers has been well-studied~\\cite{dml1,dml2,dml3}, where homogeneous data and workers are assumed~\\cite{tiresias}.\nWith the same training goal, FL raises its unique challenges including the data heterogeneity and system heterogeneity.\nAs a result, \\name aims at speeding up the training process through directly reducing the intra-cohort heterogeneity at scale.\n\n\n\\paragraph{Federated Learning}\nFL is a distributed machine learning paradigm~\\cite{tff-paper,flaas} with two key challenges: statistical and system heterogeneity.\nState-of-the-art FL algorithms try to tackle these two challenges and optimize different targets including model convergence~\\cite{yogi,prox,oort,hamed}, fairness~\\cite{ditto,qfedavg}, privacy~\\cite{privacy-pre,mycelium,honeycrisp,orchard}, efficiency~\\cite{communication-eff,wenjun,compression}, and robustness~\\cite{ditto}.\nHowever, they underperform in FL because they do not tackle the root cause of FL challenges but mitigate the negative effect caused by heterogeneity.  \n\n\\paragraph{Federated Analytics}\nThere has been significant work on geo-distributed data analytics~\\cite{gaia-cmu, relay-hotcloud, CLARINET,Iridium}.\n They mainly optimize the execution latency~\\cite{sol-nsdi} and resource efficiency~\\cite{spanstore,fedchain}.\nTo further preserve privacy for distributed data, Orchard~\\cite{orchard} and Honeycrisp~\\cite{honeycrisp} have been proposed to enable large-scale differentially private analytics. \nHelen~\\cite{helen} and Cerebro~\\cite{cerebro} allow multiple parties to securely train models without revealing their data. \n\n \n\n\n\\paragraph{Traditional Clustering Algorithms}\nClustering algorithms~\\cite{cluster-survey1,cluster-survey2} are used in popular data mining techniques, which usually assume access to all data.\nHowever, under FL setting, it is non-trivial to design a clustering algorithm because of the unavailability of data.\n\\name proposes a clustering algorithm that can be applicable to the FL settings.\n\n\n\n\\paragraph{FL Client Clustering}\n In order to leverage the nature of clusters in real-world FL dataset, many algorithms have been proposed to identify the clusters among FL clients.\n However, existing clustered FL solutions~\\cite{cfl,ifca,hc+fl,flexcfl}  mainly suffer from scalability and practicality, which are hard to adapt to large-scale, low-participation, and resource-constraint FL training.\nConsidering all real-world constraints, \\name build a practical system to identify cohorts and benefit FL training.\n\n\n\n\n\n\n\n\n","meta":{"redpajama_set_name":"RedPajamaArXiv"}}
+{"text":"\\section{Introduction}\nVarious schemes have investigated fingerprinting commercial-off-the-shelf (COTS) devices to build security applications: verifying the provenance of integrated circuits (IC) to guarding against counterfeiting by fingerprinting IC packages~\\cite{251596}; identifying unlawful 3D printed products by fingerprinting unique textures resulting from 3D printers~\\cite{li2018printracker}; authenticating smartphones by fingerprinting the Photo-Response Non-Uniformity of a camera image sensor~\\cite{ba2018abc}; identifying commodity mobile devices by fingerprinting on-board sensors~\\cite{bojinov2014mobile,zhang2019sensorid}.\n\nCompared with fingerprinting methods for on-board sensors and other components like CPUs~\\cite{bojinov2014mobile,son2018gyrosfinger,kim2018c,ba2018abc,willers2016mems,zhang2019sensorid,ba2019cim,quiring2019security,cheng2019demicpu,251596}, fingerprinting embedded memories---including static random access memory (SRAM)~\\cite{guajardo2007fpga,holcomb2009power,van2015lightweight}, dynamic random access memory (DRAM)~\\cite{schaller2018decay}, Flash memory~\\cite{wang2012flash,guo2017ffd} and electrically erasable programmable read-only memory (EEPROM)---pervasively embedded in COTS devices is a highly desirable proposition for provisioning security functions, especially in the absence of crytographic modules. Because: i) memory cells are intrinsic to computing platforms and available in large volumes to obtain many independent fingerprints or secret keys; ii)~memory biometrics are a physically source of true randomness; iii) removes the need for a protected non-volatile memory for secrets---root keys can be generated on-demand and ``\\textit{forgotten}'' after usage; and iv) imparts no extra hardware costs to {\\it existing COTS} device such as medical devices, wireless sensors, credit cards, wearable devices and other plethora of low-end Internet of Thing (IoT) devices that are projected to grow to 75.44 billion worldwide by 2025~\\cite{IoTNumberPrediction}.\n\n\\vspace{0.2cm}\n\\subsection{The Challenge} \nWhenever a fingerprint is generated from the same device, the digitized fingerprint should be exact for its use in security functions. However, fingerprints generated at different time instances are susceptible to unpredictable noise such as thermal noise, supply voltage fluctuations, device aging and, consequently, differ in some bits. First, the positions of flipped raw bits vary. Second, the exact number of flipped raw bits varies from time to time. Thus, it is challenging to determine reliable raw bits and existing memory fingerprinting schemes cannot naturally tolerate noise in the raw noisy fingerprint space. Hence, it is usually infeasible to regenerate a fingerprint identical to a reference template that is stored, for example, in a secure server for building security functions between servers and devices as illustrated in Fig.~\\ref{fig:ECClessF1a}.\n\n\\begin{figure}[t]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=.70\\linewidth]{ECClessF1a.pdf}\n\t\\caption{Conventional schemes extract \\textit{raw} fingerprints from individual memory cells, such as from the random power-up state of each SRAM cell. However, raw fingerprints $\\ff^\\prime_i$ regenerated at different time instances from the same device can mismatch a reference raw fingerprint template $\\ff$ due to native bit errors introduced by noise $e_i$. Red curves in the {\\it fingerprint symbol} depict errors resulting from noise.\n\t}\n\t\\label{fig:ECClessF1a}\n\\end{figure}\n\n\\textit{Until now}, using approximate and noisy renditions of biometric fingerprint templates in security functions is demonstrated to be possible with fuzzy extractors~\\cite{boyen2004reusable,dodis2004fuzzy}. The fuzzy extractor employs: i) a generation function to transform ``fuzzy'' biometrics into private secrets together with helper data used in; ii) a subsequent reproduction function to reconcile errors and derive the exact private secret from an approximately close template of the original biometric~\\cite{bosch2008efficient,maes2012pufky,delvaux2016efficient}. Employing a fuzzy extractor on-device leads to two fundamental problems: i)~the computation overhead introduced on-device by fuzzy extractor logic is high \\cite{gao2018lightweight}; and ii)~the associated helper data can be actively manipulated, in helper data manipulation (HDM) attacks, to weaken or even compromise the security of the derived fingerprint or private secret~\\cite{delvaux2014helper,becker2017robust}. A generic countermeasure against HDM attacks remains an open challenge~\\cite{becker2017robust}. \n\\vspace{-3mm}\n\\begin{center}\n\\textit{Hence, there remains a significant leap between the desire for re-purposing ubiquitously available memory for security functions and the practicability of exploiting memory fingerprints for security.}\n\\end{center}\n\\vspace{-2mm}\nWhile the notion of exploiting tiny hardware fabrication variations to generate memory fingerprints is not new, we challenge the traditional method of reliable fingerprint provisioning and pose the following research questions (RQs):\n\\vspace{-2mm}\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\t\\textbf{RQ1:} How can we extract \\textbf{\\textit{intrinsically reliable fingerprints}} from device memories? \n\\end{mdframed}\n\\vspace{-3mm}\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\t\\textbf{RQ2:}  If an approach does exist, is the method \\textbf{\\textit{pragmatic}} and \\textbf{\\textit{usable}} for fingerprinting memory resources on pervasive commodity computing devices?\n\\end{mdframed}\n\\vspace{-3mm}\n\n\\subsection{Our NoisFre Concept}\nCurrent memory fingerprinting schemes extract a fingerprint bit from each memory cell. Fingerprinting under this scheme is susceptible to noise. To the best of our knowledge, for commodity memories, existing techniques fail to accurately capture the noise-tolerance degree of each raw bit to formally determine those extremely reliable bits for direct key usage without the problematic error reconciliation.\n\nWe recognize that device memories are a cost-free and abundant source of entropy. Attributing to the ever-decreasing fabrication costs, the size of memory pervasively embedded within devices have become increasingly large, for example, hundreds of Kibibytes (KiB), even in low-end devices, are common (see the devices we tested in Table~\\ref{tab:chipSpec}). Consequently, we envision that entropy of extracted information may be sacrificed for improved reliability. Therefore, we propose the concept of transforming the raw fingerprint space of high information density into a lower  dimensional space with the attribute of being largely invariant to noise---bit flips---observed in the digitized raw fingerprint space or memory biometrics. We refer to this  noise-tolerant memory fingerprinting concept as \\textbf{NoisFre}.\n\n\n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=1\\linewidth]{ECClessF1b.pdf}\n\t\\caption{We transform the raw fingerprint into a lower-dimensional space, notably $m<n$, we refer to as the noise-tolerant fingerprint space. Under this noise-tolerant space, as long as the noise $e_i$ is less than a bound $\\theta$, the regenerated and transformed fingerprint $\\digamma^\\prime$ can be correctly projected to the reference transformed fingerprint template $\\digamma$. Red curves in the {\\it fingerprint symbol} depict errors resulting from noise.}\n\t\\label{fig:ECClessF1b}\n\\end{figure}\n\nWe illustrate our concept in Fig.~\\ref{fig:ECClessF1b}. Building upon a raw memory biometric source that is {\\it a noisy fingerprint space}, we propose extracting new fingerprints $\\digamma$ {\\it in the deliberately transformed noise-tolerant fingerprint space}, which is able to tolerate a desirable noise bound $\\theta$. Here, as long as the noise $e$ induced number of raw fingerprint bit errors is less than $\\theta$, the regenerated transformed fingerprint $\\digamma'$ is guaranteed to be {\\it projected} to its reference counterpart $\\digamma$. More generally, the regenerated and transformed fingerprint $\\digamma'$ is insensitive to bit errors (resulting from noise) in the raw fingerprint space. \n\n\\vspace{1mm}\n\\noindent{\\it Significantly, we recognize that it is not always the best strategy to extract memory fingerprint bits directly from the raw, noisy fingerprint space. For example, directly treating the power-up state of a {\\it single cell} in SRAM memory as a fingerprint bit, virtually the foundation for {\\it all current} memory fingerprinting schemes. We argue for exploiting the freely available and abundant entropy of memories; we focus not on the individual raw fingerprint bits, but seek to find an invariant property of a group of raw bits to measure, so we can be less concerned about the complexity of the process generating those bits.} \n\n\\subsection{Contributions and Results}\n\\vspace{2pt}\\noindent$\\bullet$ We {\\it exploit the freely available and abundant} entropy from memories to propose a \\textit{new concept}---NoisFre---for highly reliable fingerprinting of commodity device memories. The principle of our method is based on transforming the noisy raw fingerprint space into a low dimensional, noise-tolerant, fingerprint space capable of reconciling noise inherent across multiple measurements of the same raw fingerprint (\\textbf{RQ1}).  \n\n\\vspace{2pt}\\noindent$\\bullet$ To corroborate the proposed NoisFre concept, we have developed two specific transformation methods: i)~S-Norm; ii)~D-Norm (\\textbf{RQ1}). \n\n\\vspace{2pt}\\noindent$\\bullet$ We formulate analytical models with the expressive power to support the design of security functions and evaluate the transformation methods. We express:~i)~an upper bound for the unreliability of the transformed bits $\\digamma$ with respect to the transform function parameters and; ii)~the expected fingerprint extraction efficiency---the number of transformed bits that can be extracted from a given memory size (\\textbf{RQ2}).\n\n\\vspace{2pt}\\noindent$\\bullet$ We extensively test: \\textbf{\\textit{i)}} 69,206,016 SRAM cells from 29 low-end COTS microcontrollers from  4 different manufacturers to experimentally validate NoisFre performance. We focus on SRAM memories because it is the most common embedded memory technology, especially for low-cost IoT devices. Further, we employ: \\textbf{\\textit{ii)}} 7 Flash memories (3,902,976 cells); and \\textbf{\\textit{iii)}} 2 EEPROM memories (32,768 cells) for validating the generalizability of NoisFre. We validate our formalization of unreliability and extraction efficiency, and demonstrate that NoisFre fingerprints with an unreliability of $<10^{-10}$ can be easily extracted from the tested memories. Our formal models are confirmed to be worst-case bounds in practice (\\textbf{RQ2}).\n\n\\vspace{2pt}\\noindent$\\bullet$ To demonstrate the expressive power of our formalization, \nwe investigate the derivation of a root key---the foundation for realizing various security functions. We demonstrate that a root key with failure rate $<10^{-6}$ (1 error in million repeated measurements) can always be {\\it directly} obtained by transformed fingerprints from each tested chip; obviating the need for noise reconciliation. Significantly, a fingerprint snap-shot or single measurement is sufficient during enrollment, which we follow in all our experiments (\\textbf{RQ2}). \n\n\\vspace{2pt}\\noindent$\\bullet$ As a case study, we implement a security function on a low-end wearable Bluetooth inertial sensor.\nWe extract a root key directly from native SRAM fingerprints transformed into $\\digamma$ for remote attestation primitives. By fundamentally obviating the state-of-the-art method necessary for reconciling noisy key bits, we demonstrate significant overhead reduction and enhanced security entitled by NoisFre. By utilizing the power isolation features, we also demonstrate the realization of {\\it run-time and on-demand generation of robust SRAM fingerprints} $\\digamma$ on this low-end device. Video demo is at \\href{https:\/\/youtu.be\/O5NWZw-swpw}{\\underline{https:\/\/youtu.be\/O5NWZw-swpw}} (\\textbf{RQ2}). \n\n\\vspace{2pt}\\noindent$\\bullet$ We release the SRAM and EEPROM memory fingerprint datasets we collected as well as open source code artifacts to facilitate future research~\\footnote{They will be released upon the publication of this work.}.\nNotably, to the best of our knowledge, we are unaware of other public EEPROM fingerprint datasets.\n\n\\section{Background}\\label{Sec:background}\nWe concisely describe the well known methods of fingerprinting memories. Then we briefly introduce the commonly accepted (reverse) fuzzy extractor to reconstitute a ``fuzzy'' secret into cryptogrpahic secretes for security functions.\n\n\\subsection{Fingerprinting Device Memories}\\label{sec:SRAMBackground}\nWe consider the widely used, specifically in low-end devices, SRAM, FLASH and EEPROM memory fingerprinting.\nAs for the SRAM memory, when SRAM is powered up, each cell exhibits a \\textit{favored power-up state}; such an initial state varies from cell to cell, and chip to chip. Therefore, each SRAM cell's power-up state is treated as a fingerprint bit. Fingerprinting SRAM is closely related to the SRAM physical unclonable functions~\\cite{guajardo2007fpga,holcomb2009power}.\n\n\n\nTo extract fingerprints from Flash memory~\\cite{wang2012flash,guo2017ffd}, all Flash cells in the same page are first reset to \\textit{eg.} `0'. Then partial programming is applied. As a result of tiny fabrication variations, some cells will remain in state `0' while others flip to `1'. Which cell remains or flips is dominated by the fabrication process variations. One can treat whether a cell flips as the fingerprint bit---a flip as logic `1', otherwise `0'. The partial programming period is pre-determined to ensure a balanced `1'\/`0' bits in practice. We follow the same procedure to fingerprint EEPROM.\n\n\n\n\\subsection{Reliable Secrets with Fuzzy Extractors}\n\nTo turn noisy hardware fingerprint bits (key material) into usable cryptographic keys, a widely accepted method is a fuzzy extractor (FE)~\\cite{boyen2004reusable,dodis2004fuzzy}. In general, the FE consists of two procedures: i) a secure sketch; and ii) an entropy extraction. The former reconciles errors in the regenerated bits. The later compresses the bits into a uniformly distributed cryptographic key with full bit-entropy. \n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=0.35\\textwidth]{FE.pdf}\n\t\\caption{(Reverse) fuzzy extractor. \n\tIn a reverse fuzzy extractor, (a) is embedded in a device and (b) is offload to the server.}\n\t\\label{fig:keyGen}\n\\end{figure}\n\nThe secure sketch construction has a pair of operations as shown in Fig.~\\ref{fig:keyGen}: encoding and decoding. Typically, in the FE setting, the encoding is executed by the server during the fingerprint template enrollment phase to compute helper data $p$ (redundant information). The decoding is performed on the in-field device to recover a reliable fingerprint $sk$. By recognizing that the encoding function's computational burden is significantly higher than decoding, it is feasible to place the encoding on the device side while leaving the computationally complex decoding to the resource-rich server; this method is termed as reverse fuzzy extractor (RFE) or reusable fuzzy extractor~\\cite{boyen2004reusable,van2012reverse,canetti2016reusable}.\n\n\\section{NoisFre Transformation}\\label{Sec:method}\n\nWe provide the impetus for developing NoisFre fingerprinting and its key insights, followed by two specific and \\textit{practical} NoisFre transformation methods.\n\n\\subsection{Our Pragmatic Approach} \n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=\\linewidth]{SNorm_Concept.pdf}\n\t\\caption{NoisFre transformation concept. \n\tA group of raw bit vectors exhibiting errors measured at different times can be transformed into the same NoisFre fingerprint $\\digamma$, e.g., `0' attributing to the \\textit{invariance of the transform} patterns to:~i)~\\textit{permuations} of raw bit vectors (such as at $t=0$ and $t=1$); and ii)~vectors with different \\textit{combinations} of raw bits (such as at $t=2$ and $t=3$)}\n\t\\label{fig:NoisFreeConcept}\n\\end{figure}\n\n\nIn contrast to extracting a single fingerprint bit from each memory cell, we propose a many-to-1 transformation possessing a \\textit{property of invariance} to underlying raw bit patterns; more generally, invariant to the unpredictable, complex and dynamic processes generating the raw fingerprint bits. The concept is illustrated in Fig.~\\ref{fig:NoisFreeConcept}. Now: i)~permutations of raw bits; and ii)~multiple combinations of bits are projected to the {\\it exact} same transformed bit $\\digamma \\in \\{0,1\\}^1$. In general, we can express the NoisFre transformation $\\mathcal{T}(\\ff)$, where $\\ff \\in \\{0,1\\}^n$ is an $n$-bit raw fingerprint, as follows:\n\\vspace{-0.2cm}\n\\begin{equation}\\label{eqn:FingerprintingGeneral}\n    \\digamma \\leftarrow \\mathcal{T}(\\ff)\n\\end{equation}\n\nThe concept we propose is surprisingly simple but efficient and practical because of the {\\it important but inadvertent} reality of large memory volumes intrinsic to devices. From a practical consideration, our critical insight is that memory embedded within current electronics are large and {\\it provides abundant entropy} to be exploited without additional costs for security functions. This fact is the foundation for our NoisFre transformation method; \\textit{trade-off entropy for reliability}. \n\n\nThis work proposes two specific NoisFre transformation methods: Single $\\ell 1$-Norm (S-Norm) and Differential $\\ell 1$-Norm (D-Norm). The $\\ell 1$-Norm facliates the capture of bit-specific noise-tolerance level of the $\\digamma$. The $\\ell 1$-Norm of a vector is the distance of the vector from an all-zero vector---or the Hamming distance of a vector.%\n\n\\vspace{-2mm}\n\\begin{definition}[\\textbf{$\\ell 1$-Norm}]\\label{def:l1-norm}\nLet \\f be a raw noisy fingerprint binary vector of length $n$, then $\\ell 1$-Norm is defined as:\n\\vspace{-0.3cm}\n\\begin{equation}\n    \\|{\\rm {\\bf f}}\\|_1 \\leftarrow \\sum_{j = 1}^{n} f_j.\n\\end{equation}\n\\end{definition}\n\n\n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=\\linewidth]{SNorm_full.pdf}\n\t\\caption{NoisFre transformation via S-Norm; the transformed bit $\\digamma$ is extracted based on the $\\ell 1$-Norm of a group of raw bits (here $n=7$ raw bits, $\\theta=1$). .\n\t}\n\n\t\\label{fig:NoisFreeFull}\n\\end{figure}\n\n\n\\subsection{Single $\\ell 1$-Norm based Transformation (S-Norm)}\n\\label{sec:noiseTolerantFingerprinting}\n\nStraightforwardly, the new bit $\\digamma$ can be determined by the single $\\ell 1$-Norm---$\\|\\ff\\|_1$. One example is provided in Fig.~\\ref{fig:NoisFreeFull}. When $\\|\\ff\\|_1 > \\frac{n}{2}$---$n$ is an odd integer, the $\\digamma$ is 1, otherwise 0. Though the $\\digamma$ is insensitive to permutation errors in raw bits, it could still be sensitive to different raw bit error combinations. To address the later concern, we further \nwinnow the raw fingerprints based on $\\ell 1$-Norm and generalize the method based on a noise tolerance parameter $\\theta$. \n\n\\begin{definition}[\\textbf{S-Norm based Selection}]\\label{def:s-norm-sel} \nLet $\\theta \\in \\mathbb{N}^0$ and the $i$-th raw fingerprint bit vector of $n$ bits extracted at time $t$ be ${\\rm {\\bf f}}_i^{t}$. Then an extracted raw fingerprint vector $i$ is selected if~$\\forall i\\in\\{1,\\dots,|\\mathbb{N}|\\}$ at time $t=0$:\n\\begin{align}\\label{eqn:s-norm-selection}\n        \\|{\\rm {\\bf f}}_i^{0}\\|_1 \\leq \\floor{\\frac{n}{2}} - \\theta~~~\\text{or}~~~\\|{\\rm {\\bf f}}_i^{0}\\|_1 \\geq \\ceil{\\frac{n}{2}} + \\theta\n\\end{align}\n\n\\end{definition}\n\nIn Fig.~\\ref{fig:NoisFreeFull}, by \\textit{eg.} setting $\\theta = 1$, we can ensure that the transformation, across times, to be invariant to two different combinations of bit patterns; that at $t=0$ and $t=1$ to that at $t=2$ for $\\digamma=$ `0'--the $\\|\\ff\\|_1$ changes beyond the permutation changes. \n\nTo further understand and demonstrate the significance of the role of the noise tolerance parameter $\\theta$ in the mitigation of raw bit error combinations, we consider the distribution of $\\|\\ff^0\\|_1$. We used an experimental dataset obtained from Nordic Semiconductor chips---detailed in Table~\\ref{tab:chipSpec}. Fig.~\\ref{fig:reliabilityDist_HW} illustrates the resulting distribution of enrolling measurement (at $t=0$) for two cases of a small and a large $\\theta$ for $n=15$-bit $\\bf f$. As expected, the distribution of $\\|\\ff^0\\|_1$ approximates a bell curve. \n\nConsider the groups of $\\ff^0$ fingerprint bit vectors (green bar) at the boundary of the selection criteria in~\\eqref{eqn:s-norm-selection} where $\\|\\ff_i^0\\|_1=\\ceil{\\frac{n}{2}} + \\theta$ for the two cases of a small and large $\\theta$. These combined raw bits represent that closest to decision boundary, $\\|f^0\\|_1=\\ceil{\\frac{n}{2}}$ (green line); consequently, representing those most likely to lead to a bit error in a transformed bit $\\digamma$ when raw bit errors changes $\\|\\ff\\|_1$. When $\\theta$ is small ($\\theta=1$), at least two raw fingerprint bit changes in a given pattern is necessary to reduce $\\|\\ff\\|_1$ in order to cross the decision boundary of $\\frac{n}{2}$ and result in a noise tolerant fingerprint $\\digamma$ bit flip in a subsequent raw fingerprint extraction. \n\n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=\\linewidth]{HWDist.pdf}\n\t\\caption{The $\\ell 1$-Norm distribution of raw noisy fingerprints. It follows a normal distribution. \n\tA larger $\\theta$ ensures the transformed $\\digamma$ bits can tolerate a higher degree of noise.} \n\t\\label{fig:reliabilityDist_HW}\n\\end{figure}\n\nIn contrast, when $\\theta$ is large---set to 4, $\\|\\ff^0\\|_1$ is further away from the decision boundary. Consequently, at least 5 bit changes are required to affect  a $\\digamma$ bit flip in a subsequent fingerprint evaluation---such a chance is smaller than the single bit flip worse case resulting in raw fingerprint bit vectors selected with $\\theta=1$. So we can expect the new bits $\\digamma$ selected upon a larger $\\theta$ to be more reliable. \n\n\nOur study thus far leads to following observations:\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\t\\noindent\\textbf{Observation 1:} The S-Norm $\\|\\ff\\|_1$ yields a representation analogous to the reliability of the new bit $\\digamma$. \n\t\n\t\\noindent\\textbf{Observation 2:} The S-Norm transformed bit is invariant to permutations and select combinations of raw bits patterns. Further,  $\\theta$ provides a desirable lower bound on raw bit error patterns, in particular the combination of raw bit errors, tolerated by the transform.\n\t\n\t\\noindent\\textbf{Observation 3:} There is an expected trade-off evident in Fig~\\ref{fig:reliabilityDist_HW}. Whist increasing $\\theta$ increases the noise tolerance of the transform $\\mathcal{T}_{\\rm SNorm}$, it reduces the number of noise tolerant fingerprint bits that can be extracted.\t\n\\end{mdframed}\n\n\\subsection{Differential $\\ell 1$-Norm based Transformation (D-Norm)} Considering \\textit{Observation 3} and the distribution in Fig.~\\ref{fig:reliabilityDist_HW}, we recognize that \\textit{a distance measure capable of presenting a bimodal distribution could provide an intrinsic separation of groups of underlying raw fingerprint bits}, thus offering more new bits with high degree of noise tolerance. We hypothesize that a differential distance measure may afford such a desirable distribution and propose the D-Norm transform based on a differential distance measure.\n\\vspace{-3mm}\n\\begin{definition}[\\textbf{D-Norm}]\\label{def:d-norm} \nLet the lowest and highest $\\ell 1$-Norm of $m$ groups (each group is an $n$-bit vector) be $l$ and $h$, respectively. Where: \n\\begin{align}\\label{eqn:lAndh1}\n    h \\triangleq \\aggregate{arg~max}{\\textrm{f}_i|i\\in \\{1,..,m\\}} (\\|\\ff_i\\|_1)\\\\% = \\{\\ff_i|f_i\\in \\{0,1\\}^n \\wedge \\forall f_j\\in \\{0,1\\}^n : \\|\\ff_j\\|_1 \\leq \\|\\ff_i\\|_1\\}\\\\\n    l \\triangleq \\aggregate{arg~min}{\\textrm{f}_i|i\\in \\{1,..,m\\}} (\\|\\ff_i\\|_1) \\label{eqn:lAndh2\n\\end{align}\n\n\\noindent Now, following the general definition in \\eqref{eqn:FingerprintingGeneral}, the D-Norm transform is defined as: \n\\begin{equation}\\label{eq:DTrasform}\n    \\digamma \\leftarrow \\mathcal{T}_{\\rm DNorm}(S) = \\left\\{\\begin{matrix}\n 1, ~~h - l\\geq 0~~~\\text{and}~~~[h] < [l]\\\\\n 0, ~~l - h < 0~~~\\text{and}~~~[h] > [l]\n\\end{matrix}\\right.\n\\end{equation}\nHere, we denote the the spatial index $i$ (memory address, in practice) of the the vector $\\ff_i$ chosen for $h$ based on \\eqref{eqn:lAndh1} or $l$ based on \\eqref{eqn:lAndh2} using a square bracket, ``$[~]$''.\n\n\\end{definition}\n\n\n\n\\begin{figure}[!hb]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=\\linewidth]{DNorm_full.pdf}\n\t\\caption{D-Norm based NoisFre transformation. The new bit $\\digamma$ is a transformation from a block of raw bits with $m=3$ groups where each group is an $n=8$ bit vector. \n\t}\n\t\\label{fig:DNormFull}\n\\end{figure}\n\n\n\nThe D-Norm transformation is illustrated in Figure.~\\ref{fig:DNormFull}. Similar to S-Norm, the D-Norm so far still cannot always mitigate the combination raw bit errors, though it can avoid permutation of raw bit errors induced $\\digamma$ flip. Consequently, we winnow the raw fingerprints based on $|h-l|$ differential distances and, once again, generalize the method based on the noise tolerance parameter $\\theta$. We define D-Norm based selection as follows.\n\\vspace{-2mm}\n\\begin{definition}[\\textbf{D-Norm based Selection}]\\label{def:s-norm-sel} \nFrom a block of $m$ different $n$-bit raw noisy fingerprint vectors $\\ff_{i}^{0}$ for $i \\in \\{1,\\dots,m\\}$ extracted at $t=0$, the block is selected for fingerprinting the device using D-Norm if $h$ and $l$ as defined in~\\eqref{eqn:lAndh1} and~\\eqref{eqn:lAndh2} satisfy: \n\\begin{align}\\label{eqn:d-norm-selection}\n    |h - l|~\\geq~\\theta.\n\\end{align}\n\n\\end{definition}\n\n\\begin{figure}[!hb]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=\\linewidth]{DHWDist.pdf}\n\t\\caption{The differential $\\ell 1$-Norm distribution---the difference between the $h$ and $l$---of noise-tolerant fingerprints $\\digamma$ based on D-Norm; the distribution of differences provides a bimodal distribution. In this plot, $n=16$ and $m=32$---$m\\times n$ raw bits are transformed into a 1-bit $\\digamma$. Here, if $[h]$ has lower memory address than $[l]$, the D-Norm would be $h - l$ which is positive and plotted on the right half of the x-axis; otherwise, left. Reliability of $\\digamma$ increases when the $\\ell 1$-norm difference between selected groups is away from 0.  {\\it Significantly, the proportion of $\\digamma$ that tolerates a chosen noise tolerance $\\theta$ is greatly increased under D-Norm in comparison with the S-Norm}. For example, the uncovered selected area of D-Norm is much larger than that of S-Norm, see Fig.~\\ref{fig:reliabilityDist_HW}, when the same $\\theta$ is applied.}\n\t\\label{fig:reliabilityDist_DHW_Merge}\n\\end{figure}\n\n\nAgain, to understand the significance of D-Norm transformation and the role of the noise tolerance parameter $\\theta$, we used the same Nordic Semiconductor chip fingerprint dataset to S-Norm as in Fig.~\\ref{fig:reliabilityDist_HW}. The resulting distribution of enrolling measurements (at $t=0$) for two cases of a small and a large $\\theta$ for $n=16$ bit raw fingerprint vectors is shown in Fig.~\\ref{fig:reliabilityDist_HW}. Interestingly, the distribution of $|h-l|$ approximates a bimodal distribution; each mode representing those vectors mapping to $\\digamma$ = `1' and `0', respectively.  \\textit{Importantly, the two clear groupings of $m\\times n$ bit blocks based on the D-Norm distance measure results in an intrinsic separation}. \n\nNow, consider the groups of $h-1$ fingerprint bit vectors (green bar) in blocks at the boundary of the selection criteria in~\\eqref{eqn:d-norm-selection} where $|h-1|~\\geq~\\theta$ for the two cases of a small and large $\\theta$. These blocks of bits represent those most likely to lead to a bit error in a transformed bit $\\digamma$. When $\\theta$ is small ($\\theta=2$), at least three raw bits change is required to cross the decision boundary, `0', defined in~\\eqref{eq:DTrasform}. thus flipping the $\\digamma$ bit in a subsequent measurement. In contrast, when $\\theta$ is large---set to 5, at least 6 raw bits change are required to flip the $\\digamma$ in a subsequent evaluation. So the new bits $\\digamma$ selected upon a larger $\\theta$ is more reliable. \n\nThe D-Norm seems to sacrifice more available entropy ($m\\times n$ raw bits are transformed into 1-bit $\\digamma$) than S-Norm. But, as we demonstrate in following sections, the differential distance measure $h-l$ is bimodal and, thus, \\textit{D-Norm yields a significantly higher number of noise-tolerant} $\\digamma$ bits.\n\n\n\n\\section{Formalizing Performance Measures}\n\\label{sec:PerforMetrics}\n\nWe now formulate and derive analytical models to: i) provide an upper bound for the unreliability of noise tolerant fingerprint bits; and ii) evaluate the expected number of noise tolerant fingerprint bits that can be extracted from each of the transform methods---the \\textit{extraction efficiency}. In what follows we mainly summarize the derivations from our formulations and we defer the details to \\textbf{Appendix} due to page limitation. \n\n\\subsection{Reliability}\\label{sec:BER_F}\nWe employ the well known measure of bit error rate (BER) to quantify the reliability of transformed bits $\\digamma$: \n\\begin{equation}\n{\\rm BER}_\\digamma=\\textsf{FHD}({\\digamma},{\\digamma}^{\\prime}),\n\\end{equation} \nwhere $\\digamma$ and ${\\digamma}^{\\prime}$ are two fingerprint measurements at distinct times from the same physical memory. The function \\textsf{FHD}() is the fractional Hamming distance between the (binary) vectors  $\\digamma$ and ${\\digamma}^{\\prime}$. Commonly, $\\digamma$ is a reference fingerprint template measured at $t=0$ and ${\\digamma}^{\\prime}$ is the reevaluation under a potentially different device operating condition such as temperature and therefore subject to noise. A lower ${\\rm BER}_\\digamma$ indicates a higher tolerance to noise introduced from the raw fingerprints. \n\n\\vspace{1mm}\n\\noindent{\\bf S-Norm.} The ${\\rm BER}_\\digamma$ for bits extracted from the S-Norm transformation is formulated in~\\eqref{eqn:HWBER}---we defer details of the derivation to {\\bf Appendix~\\ref{app:SnormBER}}. \n\n\\begin{dmath}\n\\label{eqn:HWBER}\n    {\\rm BER}_{\\digamma} = \\sum_{i=0}^{\\floor{\\frac{n}{2}}-\\theta} \\big( (1 - \\textsf{binocdf}(\\theta + i,\\ceil{\\frac{n}{2}}+\\theta,{\\rm BER}_{\\textrm{f}})) \\times \\textsf{binopdf}(i,\\floor{\\frac{n}{2}}-\\theta,{\\rm BER}_{\\textrm{f}}) \\big) \n\\end{dmath}\n\nHere, \\textsf{binopdf} and \\textsf{binocdf} are density and cumulative density functions of a binomial distribution, respectively.  The ${\\rm BER}_\\digamma$ is a function of both selection criterion $\\theta$, $n$ and the ${\\rm BER}_{\\textrm{f}}$ of the raw noisy fingerprint bits. If we select the worse case ${\\rm BER}_{\\textrm{f}}$ of any memory chip, Equation~\\eqref{eqn:HWBER} provides a worst-case (upper-bound) assessment of ${\\rm BER}_\\digamma$.\n\n\\vspace{0.1cm}\n\\noindent{\\bf D-Norm.}\nA D-Norm transform, employs a block of $m$ groups---each group with $n$ raw fingerprint bits---to be transformed into a 1-bit $\\digamma$. \n \nThe ${\\rm BER}_\\digamma$ of D-Norm is expressed in~\\eqref{eqn:DHW_failure_rate}---we defer the derivation of the formula to {\\bf Appendix~\\ref{app:DnormBER}}. \n\\vspace{-0.3cm}\n\\begin{dmath}\n\\label{eqn:DHW_failure_rate}\n    {\\rm BER}_{\\digamma} = \\sum_{i=0}^{n-\\theta} \\big( (1 - \\textsf{binocdf}(\\theta + i-1,n+\\theta,{\\rm BER}_{\\textrm{f}})) \\times \\textsf{binopdf}(i,n-\\theta,{\\rm BER}_{\\textrm{f}}) \\big) \n\\end{dmath}\nWe can observe the reliability of transformed bits from the D-Norm to be related to the selection criterion $\\theta$, $n$ and BER$_{\\textrm{f}}$. Again, Equation~\\eqref{eqn:DHW_failure_rate} provides an upper-bound estimation when the worst case BER$_{\\textrm{f}}$ is assumed. Notably, the ${\\rm BER}_{\\digamma}$ is independent on the number of groups $m$ within the block.\n\n\\begin{table*}\n\t\\centering \n\t\\caption{Memory Datasets.}\n\t\t\t\\resizebox{\\textwidth}{!}{\n\t\\begin{tabular}{c|| c || c || c || c || c || c || c || c || c || c || c }\n\t\t\\toprule\n\t\t\\toprule\n\t\t\t\t\n\t\tManufacturer\/Model$^1$ & Abbr & \\begin{tabular}{@{}c@{}} Tech \\\\ Node \\end{tabular} & \\begin{tabular}{@{}c@{}} Memory \\\\ Type \\end{tabular} & \\begin{tabular}{@{}c@{}} Memory \\\\ Size \\end{tabular} & Quantity &  \\begin{tabular}{@{}c@{}} Repeat \\\\ Times \\end{tabular} & \\begin{tabular}{@{}c@{}} Operating \\\\ Range$^2$ \\end{tabular} & \\begin{tabular}{@{}c@{}} Enrolling \\\\ Condition \\end{tabular} & \\begin{tabular}{@{}c@{}} Worst \\\\ Condition \\end{tabular} & Worst ${\\rm BER}_{\\textrm{f}}$ & \\begin{tabular}{@{}c@{}} Exemplified Commodity Devices \\\\ (Detailed in \\textbf{Fig.~\\ref{fig:device_show} in Appendix}) \\end{tabular} \\\\\n\t\t\\hline\n\t\t\n\t\t \\begin{tabular}{@{}c@{}} Nordic Semiconductor \\\\ nRF52832 \\end{tabular} & NORDIC & 55nm & SRAM & 64 KiB & 12 & 100 & $-15$-$80\\celsius$ & $25\\celsius$ & $80\\celsius$ & 6.09\\% & \\begin{tabular}{@{}c@{}} Logitech \\\\ mouse \\end{tabular}  \\Includegraphics[height=0.4in]{Mouse_ext.png} \\hspace{10pt} \\begin{tabular}{@{}c@{}} Mbientlab \\\\ wearable \\\\ sensor tag \\end{tabular} \\Includegraphics[height=0.4in]{mbient.png} \\\\\t\\hline\t\n\t\t \n\t\t\\begin{tabular}{@{}c@{}} ISSI \\\\ IS61WV25616BLL  \\end{tabular} & ISSI & 110nm & SRAM & 256 KiB & 4 & 30 & $25$-$80\\celsius$ & $25\\celsius$ & $80\\celsius$ & 5.87\\% & \\begin{tabular}{@{}c@{}} Intel \\\\ SSD \\end{tabular} \\hspace{10pt} \\Includegraphics[height=0.4in]{SSD_ext.png} \\\\  \\hline\n\n\t\t \\begin{tabular}{@{}c@{}} IDT \\\\ IDT71V416S  \\end{tabular} & IDT & 130nm & SRAM & 512 KiB & 6 & 50 & $25$-$80\\celsius$ & $25\\celsius$ & $80\\celsius$ & 5.42\\% & \\begin{tabular}{@{}c@{}} Dell \\\\ console \\\\ switch \\end{tabular} \\Includegraphics[height=0.4in]{DellSwitch.png} \\\\\\hline\n\n\t\t \\begin{tabular}{@{}c@{}} Cypress \\\\ CY62146EV30  \\end{tabular} & CY & 90nm & SRAM & 512 KiB & 7 & 50 & $25$-$80\\celsius$ & $25\\celsius$ & $80\\celsius$ & 6.88\\% & \\begin{tabular}{@{}c@{}} Microsoft \\\\ band \\end{tabular} \\Includegraphics[height=0.4in]{Band_ext.png} \\\\ \\hline\n\t\t \n\t\t \\begin{tabular}{@{}c@{}} Winbond \\\\ W29N02GV  \\end{tabular} & Flash & 46nm & FLASH & \\begin{tabular}{@{}c@{}} 69,696 Bytes\/\\\\256 MiB$^3$  \\end{tabular}  & 7 & 99 & \\begin{tabular}{@{}c@{}} 0-100,000 \\\\ P\/E Cycles  \\end{tabular}\n\t\t   & \\begin{tabular}{@{}c@{}} 0th P\/E \\\\ Cycle  \\end{tabular} & \\begin{tabular}{@{}c@{}} after 100,000th  \\\\ P\/E Cycles$^4$ \\end{tabular} & 16.26\\% & \\begin{tabular}{@{}c@{}} Microsoft \\\\ XBOX \\end{tabular} \\Includegraphics[height=0.4in]{XBOX_ext.jpg}\\\\\n\t\t   \\hline\n\n\t\t \\begin{tabular}{@{}c@{}} Microchip \\\\ 24LC256  \\end{tabular} & EEPROM & 350nm & EEPROM & \\begin{tabular}{@{}c@{}} 2 KiB\/\\\\32 KiB$^5$ \\end{tabular}  & 2 & 100 & $14$-$80\\celsius$ & $14\\celsius$ & $80\\celsius$ & 16.37\\% & \\begin{tabular}{@{}c@{}} Lenovo \\\\ All-in-one \\end{tabular} \\Includegraphics[height=0.4in]{Lenovo.png} \\\\ \\hline\n\t\t \n\t\t\\bottomrule\n\t\\end{tabular}\n\t\t\t}\n\t\\label{tab:chipSpec}\n\t\t\\begin{tablenotes}\n\t\t\\footnotesize\n\t\t\\item{$^1$ The NORDIC and EEPROM datasets collected by us will be released, while the rest public datasets are from \\url{https:\/\/www.trust-hub.org\/data}.}\n\t\t\n\t\t\\item{$^2$ Noting these public datasets concern on room temperature and high temperature---collected for other purposes. Other operating corners are incomplete.}\n\t\t\n\t\t\\item $^3$ The tested Flash memory size in the public dataset is 69,696 Bytes, while the total memory size is 256 MiB.\n\t\t\n\t\t\\item $^4$ It is experimentally shown that the ${\\rm BER}_{\\textrm{f}}$ of the Flash memory is negligibly affected by voltage and temperature, but mainly affected by the programming\/erase (P\/E) cycles~\\cite{guo2017ffd}, equal to wear-out or aging. Notably, the maximum endurance is 100,000 according to the chip datasheet. \n\t\t\n\t\t\\item $^5$ The EEPROM chip has 32 KiB capacity, while the first 2 KiB memory is evaluated.\t\n\t\t\n\t  \n\t    \\end{tablenotes}\n\\end{table*}\n\n\\subsection{Extraction Efficiency}\nWe define the extraction efficiency $\\eta$ as the number of obtainable transformed bits $ \\digamma$ \\textit{subject to a given noise tolerant parameter} $\\theta$ \nfrom the total number of available raw memory bits expressed in Kibibytes (KiB). Our formulation of \\textit{reliability} allows a security practitioner to evaluate, for a given transform, suitable transform parameters---e.g., number of bits $n$ to employ in a raw fingerprint vector \\f and noise tolerance parameter $\\theta$---for extracting new bits $\\digamma$. The extracted $\\digamma$ will have an expected worse-case error bound given by ${\\rm BER}_\\digamma$. Then, the $\\eta$ yields the total number of such noise tolerant bits ${\\rm BER}_\\digamma$ that can be extracted from a given memory size. \n\\vspace{0.1cm}\n\\noindent{\\bf S-Norm.~}The extraction efficiency of S-Norm is expressed as below; the detailed derivation is deferred to \\textbf{Appendix~\\ref{app:SnormEf}}:\n\\vspace{-0.3cm}\n\\begin{dmath}\n    \\label{eqn:HW_SR}\n    {\\eta}_{\\rm SNorm} = \\frac{1}{n} \\times \\big(1 - \\textsf{binocdf}(\\floor{\\frac{n}{2}}+\\theta,n,0.5) + \\textsf{binocdf}(\\ceil{\\frac{n}{2}} - \\theta - 1,n,0.5)\\big)\\times (1024 \\times 8)\n\\end{dmath}\n\n\nHere, the term $1-\\textsf{binocdf}(\\floor{\\frac{n}{2}}+\\theta,n,0.5)$ expresses the case when the $\\ell 1 $-Norm of an $n$-bit \\textbf{f} is larger than the selection threshold $\\floor{\\frac{n}{2}}+\\theta$, assuming that the probability of each bit being `1'\/`0' is 50\\%. While the term $\\textsf{binocdf}(\\ceil{\\frac{n}{2}} - \\theta - 1,n,0.5)$ formulates the alternative case when the $\\ell 1 $-Norm of a $n$-bit \\textbf{f} is less than or equal to $\\ceil{\\frac{n}{2}} - \\theta - 1$. Both of these cases comprise of vectors that satisfy the selection criterion in \\eqref{eqn:s-norm-selection}. We can see that the overall extraction efficiency should be the sum of above two cases divided by $n$---recall $n$ raw bits transform into a 1-bit $\\digamma$ bit. The $1024 \\times 8$ term expresses the extraction efficiency as bit\/KiB---number of selected reliable bits $ \\digamma$ out of 1 KiB memory.\n\n\n\\vspace{1mm}\n\\noindent{\\bf D-Norm.}\nA D-Norm transform obtains a 1-bit $\\digamma$ from a block of $m$, $n$-bit raw fingerprint vectors. \nWe define the probability that a given block will meet the selection criterion ($|~h - l ~|\\ge \\theta$) in \\eqref{eqn:d-norm-selection} as $P_{\\rm DNorm}^{\\rm select}$ (recall that we refer to the lowest $\\ell 1$-Norm as $l$, and the highest $\\ell 1$-Norm as $h$, out of all $m$ groups within a block). The direct derivation of $P_{\\rm DNorm}^{\\rm select}$ is non-trivial, we instead solve it through a different but equivalent problem and deffer the details to \\textbf{Appendix~\\ref{app:DnormEf}}. We formulate the extraction efficiency of D-Norm as:\n\\vspace{-0.3cm}\n\n\\begin{equation}\\label{eqn:DHW_SR}\n    {\\eta}_{\\rm DNorm} = \\frac{1}{n \\times m} \\times P_{\\rm DNorm}^{\\rm select} \\times (1024 \\times 8)\n\\end{equation}\n\nHere, the term of $\\frac{1}{n\\times m}$ expresses $n\\times m$ raw bits producing a single $\\digamma$ bit, while the $1024\\times 8$ constant facilities expressing the result in terms of bits\/KiB of memory. Given the complexity of formulating ${\\eta}_{\\rm DNorm}$, the fitness of the formalized expression is further validated through running extensive numerical experiments (defined in Section~\\ref{Sec:validation}) with results detailed in  Fig.~\\ref{fig:DHWn32} in {\\bf Appendix}.\n\n\\section{Experimental Validations}\\label{Sec:validation}\nWe take 29 commodity chips having: i) SRAM memories from 4 different manufacturers for comprehensively evaluating NoisFre. The size of the SRAM chips ranges from 64 KiB to 512 KiB; we also evaluate on: ii) Flash; and iii) EEPROM memories to corroborate the generalization of NoisFre. These three memory types are pervasive, especially in low-end IoT devices. COTS devices with the evaluated memories are exemplified in Fig.~\\ref{fig:device_show} in the~\\textbf{Appendix}. We consider three evaluation settings: \\\\\n\\vspace{2pt}\\noindent$\\bullet$ {\\bf Prediction}: Uses numerical calculations based on formalized models in Section~\\ref{sec:PerforMetrics}.\\\\\n\\vspace{2pt}\\noindent$\\bullet$ {\\bf Simulation}: Uses fingerprints extracted from an ideal memory chip model (detailed in \\textbf{Appendix~\\ref{sec:apx_Random_chip}}) with the same \\textit{capacity} of the physical SRAM chip---e.g., we simulate 64 KiB memory volume if the physical SRAM chip is with 64 KiB memory size. The ideal chip model assumes each bit has binomial probability of a bit flip across repeated measurements based on employing the worse-case BER (see \\autoref{tab:chipSpec}) measured from the physical SRAM chip as the parameter $p$. \\\\\n\\vspace{2pt}\\noindent$\\bullet$ {\\bf Measurement (Chips)}: Uses raw fingerprint bits measured from physical chips. The data we employed is described in Section~\\ref{sec:mem-dataset}.\n\n\n\\subsection{Memory Datasets}\\label{sec:mem-dataset}\n\nSpecifications of: i) four SRAM; ii) one Flash memory; and iii) one EEPROM datasets are summarized in Table~\\ref{tab:chipSpec}: each dataset is obtained from chips from a \\textit{different manufacturer}. Overall, the total number of raw SRAM bits evaluated is 69,206,016, while the evaluated number of Flash bits and EEPROM bits are 3,902,972 and 32,786, respectively. Furthermore, the datasets describe multiple repeated measurements of raw fingerprint bits under {\\it each} operating condition---described by the Operating Range in Table~\\ref{tab:chipSpec}.\n\nWe use the NORDIC dataset to extensively validate the reliability of ${\\rm BER}_{\\digamma}$ and extraction efficiency $\\eta$ metrics of both the S-Norm and D-Norm transformations, considering the fact that it is collected with the broadest operating range and highest number of repeated measurements (100 repeated measurements). In addition, we employ the remaining datasets to corroborate the generality of our approaches. When we evaluate the BER of transformed bits, ${\\rm BER}_\\digamma$, we report the average of from repeated evaluations. Notably, the enrolled reference template is only based on the first \\textit{single measurement}.\n\nBelow briefly describes the collected NORDIC dataset while details of the public datasets are in~\\cite{guo2017scare,rahman2017systematic,guo2017ffd}. Our method for collecting EEPROM data is similar to that employed for Flash in~\\cite{wang2012flash}.\n\n\\vspace{0.1cm}\n\\noindent{\\bf NORDIC.} We collected 12 nRF52832 chips (see one such chip in Fig.~\\ref{fig:Overview}). The nRF52832 is a popular RF-enabled MCU, and supports various protocols including Bluetooth 5, Bluetooth mesh, ANT, and NFC. This chip has a 64 KiB SRAM memory. It is worth to mention that the NORDIC chips is typical of a low-cost IoT device MCU. Three temperature corners \\{$-15\\celsius$, $25\\celsius$, $80\\celsius$\\} are evaluated to measure the reliability of raw bits using 100 repeated measurements taken under each operating corner. The worst-case ${\\rm BER}_{\\textrm{f}}$ of 6.09\\% occurs under $80\\celsius$ when the reference template is collected at $25\\celsius$.\n\n\\subsection{S-Norm Validation on NORDIC Chips}\\label{Sec:HWMethod}\nWe concatenate all 12 chips to gain a large memory chip: the concatenated size is $12\\times 64$ KiB = 768 KiB. The evaluation results from S-Norm are detailed in Fig.~\\ref{fig:Eq1A3Times20_V2} under various $n$ and $\\theta$ settings. \n\n\\vspace{0.1cm}\n\\noindent{\\bf Reliability.} We can confirm that the formalization of Equation~\\eqref{eqn:HWBER} provides a conservative estimation of the selected new bits $\\digamma$, which is validated as the chip measurement\\footnote{Simulation and Measurement data are\naveraged over 1 reference and 99 repeated measurements.} is always smaller than the prediction. Notably, as indicated by the arrow \\circled{1}\\footnote{There should be no 0 appearing in the y-axis in this log scale. We use this to solely indicate zero error under empirical test settings: both for Simulation and Measurement evaluations.}, we find no error for the chip test and simulation that are both {\\it empirical} tests. This is due to the fact that the number of repeated measurements are finite (100) and inadequate to demonstrate any empirical errors when the expected ${\\rm BER}_{\\digamma}$ considerably small.\n\\begin{figure*}[!h]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=0.75\\linewidth]{Eq1A3Times20_V2.pdf}\n\t\\caption{S-Norm validation on NORDIC dataset. ${\\rm BER}_\\digamma$ of selected noise-tolerant bits ${ \\digamma}$ and corresponding extraction efficiency $\\eta_{\\rm SNorm}$ under different $n$ ($n$ raw bits transform into a 1 $\\digamma$ bit) and noise-tolerance parameter $\\theta$ ($\\theta$ ranges from $0$ to $n\/2$). \n\tNote \\circled{1}:\n\tthe number of repeated measurements are are finite (100) and inadequate to demonstrate any errors when the expected ${\\rm BER}_{\\digamma}$ considerably less than $10^{-2}$. Hence, the regenerated ${\\digamma}$ bits exhibits no errors. Further, as $\\theta$ is increased, it is no longer possible to select bits from our finite sized Simulation and Measurement chips.} \n\t\\label{fig:Eq1A3Times20_V2}\n\\end{figure*}\n\n\\vspace{0.1cm}\n\\noindent{\\bf Extraction Efficiency.}\nThe Simulation and Prediction--Equation~\\eqref{eqn:HW_SR}--are in good agreement but the extraction efficiency of the chip measurement is higher. The reason is due to the existence of local spatial bias among physical adjacent raw memory bits~\\cite{delvaux2016efficient}, while Prediction and Simulation evaluations were based on the ideal memory model that assumed ideal independence across all individual raw bits. Effectively, the tested chips affords more `1'\/`0' raw bits in nearby locations to facilitate the transformed bit $\\digamma$ to meet the S-Norm selection described in~\\eqref{eqn:s-norm-selection}. In other words, the local spatial bias has a positive effect on the extraction efficiency $\\eta_{\\rm SNorm}$.\n\n\\subsection{D-Norm Validation on NORDIC Chips}\\label{Sec:DHWMethod} \n\nThe validation results of D-Norm are shown in Fig.~\\ref{fig:DHWtimes100_V1}.\n\n\\vspace{0.1cm}\n\\noindent{\\bf Reliability.} As expected, the reliability is substantially increased as the noise-tolerance parameter $\\theta$ is increased. Again, we can confirm that the formalized ${\\rm BER}_\\digamma$ is a conservative estimation because it is always shown to be higher than both the Simulation and chip Measurement results. \n\n\\begin{figure*}[!h]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=0.75\\linewidth]{DHWtimes100_V2.pdf}\n\t\\caption{D-Norm validation on the NORDIC dataset. ${\\rm BER}_\\digamma$ of reliable bits ${ \\digamma}$ and corresponding extraction efficiency $\\eta_{\\rm DNorm}$ under different $n$ and noise-tolerance parameter $\\theta$ ($\\theta$ ranges from $0$ to $n$). Here, $m$ is fixed to 4 and $m\\times n$ raw bits transform into a 1-bit $\\digamma$ bit.\n\t}\n\t\\label{fig:DHWtimes100_V1}\n\\end{figure*}\n\n\\vspace{0.1cm}\n\\noindent{\\bf Extraction Efficiency.} The Simulation and Prediction---Equation~\\eqref{eqn:DHW_SR}---agree well, whereas the extraction efficiency of chip measurement is higher than the predicted result. The higher chip measurement can again be attributed to the fact that any local spatial bias among raw bits in the physical chip will facilitate more raw bit vectors $\\ff$ to meet the imposed D-Norm selection criterion. In contrast, in formulation of the model used in the Prediction evaluations, each raw bit is assumed to be independent under an ideal memory model.\n\n\\subsection{Generalizability}\nThree public rest SRAM datasets: ISSI, CY, and IDT; one Flash dataset; and  one EEPROM dataset are further utilized to validate generality. Results of S-Norm and D-Norm validated on these 5 datasets are detailed in Fig.~\\ref{fig:HWthreeDataset} and Fig.~\\ref{fig:DHWthreeDataset}, respectively. We can confirm the same observations discussed in our extensive analysis with the NORDIC dataset.\n\n\\textit{Based on our comprehensive experimental validations on SRAM memories from four different manufacturers, Flash memories and EEPROM memories, we can now conclude that our formalization of the unreliability ${\\rm BER}_{\\digamma}$ and extraction efficiency $\\eta$ in Section~\\ref{sec:PerforMetrics} are indeed reliable measures. Most importantly, the formalized models serve as an upper bound in practice.}\n\\begin{figure*}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=0.75\\textwidth]{HWfourDataset.pdf}\n\t\\caption{S-Norm validation on datasets from three types of SRAM memories (ISSI, IDT, CY), one type of Flash memory and one type of EEPROM memory---from left to right. Here $n=39$.}\n\t\\label{fig:HWthreeDataset}\n\\end{figure*}\n\n\\begin{figure*}[!ht]\n\t\\centering\n\t\\includegraphics[trim=0 0 0 0,clip,width=0.75\\textwidth]{DHWfourDataset.pdf}\n\t\\caption{D-Norm validation on datasets from three types of SRAM memories (ISSI, IDT, CY), one type of Flash memory and one type of EEPROM memory---from left to right. Here, $n=32$ and $m=4$.}\n\t\\label{fig:DHWthreeDataset}\n\\end{figure*}\n\n\n\n\n\\section{Cryptograhic Keys for Security Functions}\\label{Sec:keyDerivation}\n\nWe demonstrate the \\textit{expressive power of our formalization} by investigating the derivation of root keys from commodity memory chips. The dynamic and direct generation of cryptographic keys from memory fingerprint transformations into noise-tolerant bits is a basis for building security functions because: i) memory biometrics are a true source of randomness; and ii) removes the need for a protected non-volatile memory---keys can be generated on-demand and ``\\textit{forgotten}\" after usage. Here, we compare the formal model analysis with fingerprint measurements from chips under test; we begin our systematic investigate with the following question.\n\\vspace{-0.2cm}\n\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\n\tWhat is the reliability of a $k$-bit NoisFre fingerprint?\n\\end{mdframed}\n\\vspace{-0.3cm}\n\nTransformed bits $ \\digamma$ can be directly utilized as a cryptographic key because they are invariant to a desirably high number of noise-induced bit error patterns---these  $\\digamma$ bits exhibit a high noise-tolerance. The overall failure rate $P_{\\rm key}^{\\rm fail}$ of a $k$-bit noise-tolerant key  can be expressed as: \n\\begin{equation}\n    \\label{eqn:key_failure_rate}\n    P_{\\rm key}^{\\rm fail} = 1-(1-{\\rm BER}_\\digamma)^k\n\\end{equation}\n\nRecall the formalized ${\\rm BER}_\\digamma$ in Section~\\ref{sec:BER_F} is conservative. Therefore, the $P_{\\rm key}^{\\rm fail}$ in Equation~\\eqref{eqn:key_failure_rate} will also yield a conservative estimation. We expect a key failure rate in practice to be lower than our prediction here, this hypothesis is validated with an extensive simulation based on a large Simulated chip with up to \\textit{1 billion} repeated noise tolerant key bit extraction as illustrated in Fig.~\\ref{fig:PKF_validation}.\n\nNext, considering a practitioner's desire of $P_{\\rm key}^{\\rm fail} < 10^{-6}$ for typical industrial applications~\\cite{maes2015secure}, we investigate the following question.\n\\vspace{-2mm}\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\tWhat is the most efficient transformation method presenting the highest extraction efficiency while ensuring sufficient reliable $\\digamma$ to be {\\it directly} served as a cryptographic key with a failure rate lower than $10^{-6}$?\n\\end{mdframed}\n\\vspace{-2mm}\n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[width=\\linewidth]{PKFSmall.pdf}\n\t\\caption{Validation of Equation \\eqref{eqn:key_failure_rate}. The simulated chips are based on the worst-case BER=6.09\\% from the NORDIC chip set. Based on TABLE.~\\ref{tab:MMRTable}, we selected $n = 32$, $m = 16$, and varied D-norm parameter $\\theta$ from $1,\\dots,17$. We conducted 10 \\textit{million} re-evaluations of a 128-bit noise tolerant fingerprint for each value of $\\theta=1,\\dots,16$ and 1 \\textit{billion} evaluations for $\\theta = 17$. Our results corroborates Equation~\\eqref{eqn:key_failure_rate} as an upper bound on failure rate of a NoisFre fingerprint employed as a cryptogrpahic key.}\n\t\\label{fig:PKF_validation}\n\\end{figure}\n\nWe employ NORDIC SRAM fingerprints---the largest memory biometric dataset under test with 69,206,016 bits---to perform extensive evaluations to address the question. The evaluation process is described below: \n\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 1.$ Evaluate the the minimum $\\theta$ for the required ${\\rm BER}_\\digamma$ (Equation~\\eqref{eqn:HWBER} for S-Norm and \\eqref{eqn:DHW_failure_rate} for D-Norm) to guarantee $P_{\\rm key}^{\\rm fail}< 10^{-6}$ with Equation~\\eqref{eqn:key_failure_rate} for a selected: i)~$n$ in S-Norm; or ii)~$n$ and $m$ parameters in D-Norm. Specifically, a value for $\\theta$ is sought by gradual increments of 1 from zero.\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 2.$ Use the parameters $n$, $m$ and minimum $\\theta$ to extract noise tolerant bits $ \\digamma$ from the physical chips. The number of extracted $ \\digamma$ bits is counted to report \\textit{extraction efficiency} $\\eta$.\n    \n\\vspace{2pt}\\noindent$\\bullet \\bf 3.$ Uniformity reports the proportion of `1' bits in the $\\digamma$ obtained from the physical chips.\n\n\\begin{table}[!ht]\n\t\\centering \n\t\\caption{Investigating the extraction efficiency $\\eta$ (bit\/KiB) of $ \\digamma$ when $\\mystrut P_{\\rm key}^{\\rm fail}<10^{-6}$ is just met for a 128-bit key. NORDIC SRAM dataset is used.}\n\t\t\t\\resizebox{\\linewidth}{!}{\n\t\\begin{tabular}{c| c | c | c | c | c | c }\n\t\t\\toprule\n\t\t\\toprule\n\t\t\t\t\n\t\t\\multirow{ 2}{*}{Method} & \\multirow{ 2}{*}{$n$} & \\multirow{ 2}{*}{$m^1$} & \\multirow{ 2}{*}{$\\theta$}  & \\multicolumn{2}{c|}{ $\\eta$ (bit\/KiB)$^2$}& \\multirow{ 2}{*}{Uniformity} \\\\\n\t\t& & & & Measurement & Prediction & \\\\\n\t\n\t\t\\midrule\n\t    \\hline\n\t    \\multirow{1}*{S-Norm} &  \\multirow{1}*{15}& \\multirow{1}*{N\/A}& \\xmark    & \\xmark   & \\xmark & \\xmark \\\\\n        \\hline\n\n\t    \\multirow{1}*{S-Norm} &  \\multirow{1}*{31} & \\multirow{1}*{N\/A} & 12    & 0.599 & 0.0012 (Equation~\\ref{eqn:HW_SR}) & \\xmark \\\\\n        \\hline\n        \n\t    \\multirow{1}*{S-Norm} &  \\multirow{1}*{39} & \\multirow{1}*{N\/A}& 13      & 0.0742 & 0.0029 (Equation~\\ref{eqn:HW_SR})& \\xmark \\\\\n        \\hline\n\n\t    \\multirow{1}*{S-Norm}&  \\multirow{1}*{47} & \\multirow{1}*{N\/A} & 14   & 0.0247 & 0.0043 (Equation~\\ref{eqn:HW_SR})& \\xmark \\\\\n        \\hline\n        \\hline\n\n\t    \\multirow{1}*{D-Norm} &  \\multirow{1}*{16} & \\multirow{1}*{64}& 13   & 1.053 & 0.0370 (Equation~\\ref{eqn:DHW_SR}) & 55.74\\% \\\\\n        \\hline\n        \n\t    \\multirow{1}*{D-Norm}  &  \\multirow{1}*{16} & \\multirow{1}*{128}& 13    & 1.008 & 0.0645 (Equation~\\ref{eqn:DHW_SR})  & 53.10\\% \\\\\n        \\hline \n        \n\t    \\multirow{1}*{D-Norm} &  \\multirow{1}*{16} & \\multirow{1}*{256}& 13   & 0.799 & 0.1055 (Equation~\\ref{eqn:DHW_SR}) & 52.20\\% \\\\\n        \\hline        \n        \n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{{\\bf 32}}\n\t                & \\multirow{1}*{{\\bf 16}}\n                        & {\\bf 16}    & {\\bf 5.583} & 0.1242 (Equation~\\ref{eqn:DHW_SR}) & 54.94\\% \\\\\n        \\hline  \n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{32}\n                        & 16    & 4.013 & 0.2234 (Equation~\\ref{eqn:DHW_SR}) & 52.08\\%  \\\\\n        \\hline\n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{64}\n                        & 16    & 2.600 & 0.3529 (Equation~\\ref{eqn:DHW_SR}) & 50.45\\% \\\\\n        \\hline\n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{128}\n                        & 16    & 1.560 & 0.4719 (Equation~\\ref{eqn:DHW_SR})  & 49.92\\% \\\\\n        \\hline\n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{256}\n                        & 16   & 0.9091 & 0.5170 (Equation~\\ref{eqn:DHW_SR}) & 47.83\\%  \\\\\n        \\hline\n        \n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{32}\n                        & 21    & 0.4922 & 0.3036 (Equation~\\ref{eqn:DHW_SR}) & 44.97\\%  \\\\\n        \\hline \n\n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{64}\n                        & 21    & 0.5807 & 0.4291 (Equation~\\ref{eqn:DHW_SR}) & 47.09\\%   \\\\\n        \\hline  \n        \n\t    \\multirow{1}*{D-Norm} \n\t        &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{128}\n                        & 21  & 0.5794 & 0.4841 (Equation~\\ref{eqn:DHW_SR}) & 50.56\\%   \\\\\n        \\hline  \n        \n\t\t\\bottomrule\n\t\\end{tabular}\n\t\t\t}\n\t \\begin{tablenotes}\n      \\footnotesize\n      \\item {\\bf bold} depicts the best results among the tested parameter settings.\n      \\item $^1$ For the S-Norm, the $m$ setting is not applicable---N\/A.\n      \\item $^2$ Extraction efficiency $\\eta$, the number Measurement is measured from the physical chip, and the $\\eta$ Prediction is based on formalized equations, which is conservative and essentially smaller than that of measurement test.\n      \\item \\xmark. Under such a specific setting, it is difficult to meet $P_{\\rm key}^{\\rm fail}<10^{-6}$. For uniformity, since the number of selected $\\digamma$ becomes too small, it has large variance and thus, invalid.\n     \n    \\end{tablenotes}\n\t\\label{tab:comparison}\n\\end{table}\n\nFrom the results summarized in Table~\\ref{tab:comparison}, we can conclude that the D-Norm affords significantly higher extraction efficiencies conditioned on the $P_{\\rm key}^{\\rm fail}<10^{-6}$ constraint. {\\it Therefore, in following discussions, we focus on the D-Norm.}\n\n\nGiven: i) different sizes of memories embedded within various COTS electronics; and ii) ${\\rm BER}_{\\textrm{f}}$ characteristics of noisy fingerprints from different memory technologies, \n\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\n\tWhat is the \\textit{lowest failure rate} achievable for a 128-bit key from \\textit{each} memory technology and manufacturer? \n\\end{mdframed}\n\n\n\\begin{table}[!ht]\n\t\\centering \n\t\\caption{The lowest key failure rate achievable for obtaining a 128-bit key for each investigated memory chip. The D-Norm is applied.} \n\t\t\t\\resizebox{\\linewidth}{!}{\n\t\\begin{tabular}{ c | c| c |c | c | c | c | c | c}\n\t\t\\toprule\n\t\t\\toprule\n\t\t\t\t\n\t\tType & Manufacturer & ${\\rm BER}_{\\textrm{f}}$ & \\begin{tabular}{@{}c@{}} Memory \\\\ size \\end{tabular} & n & \\begin{tabular}{@{}c@{}} m \\end{tabular} &  $\\theta$ & \\begin{tabular}{@{}c@{}}  $P_{\\rm key}^{\\rm fail}$ $^1$\\\\ (Equation~\\ref{eqn:key_failure_rate}) \\end{tabular}&  \\begin{tabular}{@{}c@{}} Num. of selected \\\\ noise-tolerant bits \\end{tabular} \\\\\n\t\t\\midrule\n\t    \\hline\n\t    \\multirow{4}*{\\begin{tabular}{@{}c@{}}  ~\\\\~\\\\ SRAM \\end{tabular}} &\n\t    \\multirow{1}*{NORDIC} \n\t       &\\multirow{1}*{6.09\\%} \n\t        &  \\multirow{1}*{64 KiB} \n\t            &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{16}\n                        & 18    & $\\mystrut 3.486\\times 10^{-13}$\n                        & 148 $>$ 128 \\\\ \\cline{2-9}\n\n\t    & \\multirow{1}*{ISSI}\n\t       &\\multirow{1}*{5.87\\%} \t    \n\t        &  \\multirow{1}*{256 KiB}\n\t            &  \\multirow{1}*{128}\n\t                & \\multirow{1}*{32}\n                        & 44    & $\\mystrut8.830\\times 10^{-17}$ \n                        & 149 $>$ 128 \\\\ \\cline{2-9}\n        \n\t    & \\multirow{1}*{IDT} \n\t       &\\multirow{1}*{5.42\\%} \t    \n\t        &  \\multirow{1}*{512 KiB}\n\t            &  \\multirow{1}*{128}\n\t                & \\multirow{1}*{32}\n                        & 42    & $\\mystrut1.180\\times 10^{-16}$ \n                        & 354 $>$ 128 \\\\ \\cline{2-9}\n        \n\t    & \\multirow{1}*{CY} \n\t       &\\multirow{1}*{6.88\\%} \t    \n\t        &  \\multirow{1}*{512 KiB}\n\t            &  \\multirow{1}*{128}\n\t                & \\multirow{1}*{128}\n                        & 36    & $\\mystrut4.540 \\times 10^{-10}$ \n                        & 141 $>$ 128 \\\\ \\cline{1-9}\n        Flash &\n\t    \\multirow{1}*{Winbond} \n\t       &\\multirow{1}*{16.26\\%} \t    \n\t        &  \\multirow{1}*{256 MiB}\n\t            &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{64}\n                        & 36    & $\\mystrut6.580 \\times 10^{-6}$ \n                        & 3827$ ^2$ $>$ 128 \\\\ \\cline{1-9}\n\n        EEPROM &\n        \\multirow{1}*{Microchip} \n\t       &\\multirow{1}*{16.37\\%}         \n\t        &  \\multirow{1}*{32 KiB}\n\t            &  \\multirow{1}*{16}\n\t                & \\multirow{1}*{128}\n                        & 20    & $\\mystrut1.468 \\times 10^{-2}$ \n                        & 133$^2$ $>$ 128 \\\\ \\cline{1-9}\n\n\t\t\\bottomrule\n\t\\end{tabular}\n\t\t\t}\n\t \\begin{tablenotes}\n      \\footnotesize\n      \\item $^1$ The empirical measurements are finite---no more than 100 times for all datasets, which eventually exhibits ${\\rm BER}_{\\digamma} = 0$, thus $P_{\\rm key}^{\\rm fail}=0$. Herein, the estimated and reported $P_{\\rm key}^{\\rm fail}$ is based on ${\\rm BER}_{\\digamma}$ formulated in \\eqref{eqn:DHW_SR}.\n      \n      \\item $^2$ Recall that the tested size of Flash and EEPROM memory are 69 KiB and 2 KiB. The number of selected noise-tolerant bits is scaled up by assuming the entire 256 MiB Flash memory and 32 KiB EEPROM memory are available.\n\n    \\end{tablenotes}\n\t\\label{tab:PkeySingleChip} \n\\end{table}\nThis scenario resembles a practical application setting where the available memory is given (determined by the computing platform or micro-controller unit) and the inherent (worst case) ${\\rm BER}_{\\textrm{f}}$ of raw fingerprints are known (i.e., published measurement studies on memory technologies). Thus, to assess the practicability of deriving a robust key by adopting the NoisFre, we test our suite of memory technologies using the following approach:\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 1.$ For each manufacturer listed in Table~\\ref{tab:PkeySingleChip}, we conduct a parameter search using possible combinations of parameter values based where $n,m \\in \\{8,16,32,64,128\\}$ and $\\theta \\in [1,n]$. This process identifies the ($n$, $m$, $\\theta$) combination exhibiting the lowest $P_{\\rm key}^{\\rm fail}$ while still providing a $\\digamma$ with at least 128 bits.\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 2.$ We employ the formulated Equation~\\eqref{eqn:DHW_failure_rate} to obtain the ${\\rm BER}_\\digamma$ of the extracted $ \\digamma$ bits using the identified $m$, $n$, $\\theta$ and the already characterized ${\\rm BER}_{\\textrm{f}}$. \n\n\\vspace{2pt}\\noindent$\\bullet \\bf 3.$ We use ${\\rm BER}_\\digamma$ substituted in Equation~\\eqref{eqn:key_failure_rate} to determine the best $P_{\\rm key}^{\\rm fail}$ of the selected transformed  $\\digamma$ bits with at least 128 bits.\n   \n\n\nOur results are summarized in Table~\\ref{tab:PkeySingleChip}. Given a key length requirement of 128 bits, the best $P_{\\rm key}^{\\rm fail}$ can be extremely low for SRAM memory technologies even under a worst case ${\\rm BER}_{\\textrm{f}}$ ranging from 6.88\\% to 5.42\\% for extracting a key, which is directly from the transformed space with highly noise tolerant $\\digamma$ bits by the virtues of the transformation.\n\nIn practice, it is desirable to have prior determinations of which memory chips can adopt NoisFre to directly provide a root key. So the following question is interested.\n\\begin{mdframed}[backgroundcolor=black!10,rightline=false,leftline=false,topline=false,bottomline=false,roundcorner=2mm]\n\n\tWhat is the minimum memory size required (MMR) to obtain a 128-bit key with a key failure rate below $P_{\\rm key}^{\\rm fail} < 10^{-6}$ conditioned on the inherent ${\\rm BER}_{\\textrm{f}}$ of raw fingerprints for each memory technology?\n\\end{mdframed}\n\\vspace{-0.2cm}\nTo answer this, we test all types of chips by below steps:\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 1.$ First, perform an search for the largest possible number of $\\digamma$ bits while keeping $P_{\\rm key}^{\\rm fail}$ below $10^{-6}$.\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 2.$ Second, measure the extraction efficiency $\\eta$, by dividing number of yield $\\digamma$ bits over the total memory size.\n\n\\vspace{2pt}\\noindent$\\bullet \\bf 3.$ Finally, the MMR can be calculated by dividing the desired key length, e.g. 128 bits, by the $\\eta$.\n\nResults are summarized in Table~\\ref{tab:MMRTable}. This is a practical guide to asses whether the NoisFre can immediately be mounted on the given memory technology and manufacturer. Whenever the memory size is larger than MMR, which tends to be more likely the case considering ever-increased memory volumes, even in low-end IoT devices, NoisFre is a practical option for providing a usable root-key for commodity computing devices. Notably, we can explore some optimization techniques discussed in Section~\\ref{Sec:discussion} to, potentially, reduce the MMR further. \n\\begin{table}[!ht]\n\t\\centering \n\t\\caption{The minimal memory size requirement (MMR) to provide a 128-bit key with $P_{\\rm key}^{\\rm fail}<10^{-6}$ conditioned on the inherent ${\\rm BER}_{\\textrm{f}}$ of raw memory technology. The D-Norm is applied.} \n\t\t\t\\resizebox{\\linewidth}{!}{\n\t\\begin{tabular}{c | c | c |c | c | c | c | | c | c | c}\n\t\t\\toprule\n\t\t\\toprule\n\t\t\t\t\n\t\t \\multirow{2}*{Type} & \\multirow{2}*{Manufacturer} & \\multirow{2}*{${\\rm BER}_{\\textrm{f}}$} & \\multirow{2}*{n} & \\multirow{2}*{ m } & \\multirow{2}*{$\\theta$} & \\multirow{2}*{${\\rm BER}_{\\digamma}$} & \\multirow{2}*{$P_{\\rm key}^{\\rm fail}$}& \\multicolumn{2}{c}{ MMR $^1$ (KiB)}\\\\\n\t\t & & & & & & & & Measurement & \\begin{tabular}{@{}c@{}} prediction \\\\ (Equation~\\ref{eqn:DHW_SR}) \\end{tabular}  \\\\\n\t\t\\midrule\n\t    \\hline\n\t    \\multirow{4}*{\\begin{tabular}{@{}c@{}}  ~\\\\~\\\\ SRAM \\end{tabular}} &\t    \n\t    \\multirow{1}*{NORDIC} \n\t        &  \\multirow{1}*{6.09\\%} \n\t            &  \\multirow{1}*{32}\n\t                & \\multirow{1}*{16}\n                        & 16 & $\\mystrut 5.09\\times 10^{-9}$  & $\\mystrut 6.52\\times 10^{-7}$ & 23.95\n                        & 382.6\n                       \\\\ \\cline{2-10}\n\n\t    & \\multirow{1}*{ISSI}\n\t        &  \\multirow{1}*{5.87\\%}\n\t            &  \\multirow{1}*{128}\n\t                & \\multirow{1}*{16}\n                        & 28  & $\\mystrut 2.30\\times 10^{-9}$  & $\\mystrut 2.95\\times 10^{-7}$ & 22.32\n                        & 640\n                        \\\\ \\cline{2-10}\n        \n\t    & \\multirow{1}*{IDT} \n\t        &  \\multirow{1}*{5.42\\%}\n\t            &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{32}\n                        & 21  & $\\mystrut 4.84\\times 10^{-9}$  & $\\mystrut 6.19\\times 10^{-7}$ & 14.32\n                        & 49.56\n                        \\\\ \\cline{2-10}\n        \n\t   &  \\multirow{1}*{CY} \n\t        &  \\multirow{1}*{6.88\\%}\n\t            &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{32}\n                        & 22  & $\\mystrut 5.51\\times 10^{-9}$  & $\\mystrut 7.05\\times 10^{-7}$ & 106.91\n                        & 767.4\n                         \\\\ \n        \\hline\n                         \n\t    \\multirow{1}*{Flash} &        \n\t    \\multirow{1}*{Winbond} \n\t        &  \\multirow{1}*{16.26\\%}\n\t            &  \\multirow{1}*{64}\n\t                & \\multirow{1}*{64}\n                        & 36  & $\\mystrut 5.17\\times 10^{-9}$  & $\\mystrut 6.61\\times 10^{-7}$ & --$^2$ \n                        & $1.15\\times 10^{9}$ \n                       \n                         \\\\ \n        \\hline   \n        \\multirow{1}*{EEPROM} &        \n        \\multirow{1}*{Microchip} \n\t        &  \\multirow{1}*{16.22\\%}\n\t            &  \\multirow{1}*{128}\n\t                & \\multirow{1}*{32}\n                        & 30 & $\\mystrut 4.83\\times 10^{-9}$ & $\\mystrut 6.19\\times 10^{-7}$ &  --$^2$\n                        & $1.15\\times 10^{9}$ \n                        \\\\\n        \\hline\n\t\t\\bottomrule\n\t\\end{tabular}\n\t\t\t}\n\t \\begin{tablenotes}\n      \\footnotesize\n      \\item $^1$ Under listed $n$, $m$, $\\theta$ settings, the number of extracted $\\digamma$ may more than 128 bits, \\textit{e.g.} for NORDIC, up to 439 $\\digamma$ bits are available, the MMR is scaled down to truncate the first $\\digamma$ 128 bits.\n      \\item $^2$ Given that, up to 16\\% ${\\rm BER}_{\\textrm{f}}$ for both Flash and EEPROM, the {\\it tested size} of Flash and Flash (69 KiB for Flash Winband, and 2 KiB for Microchip) is hard to provide a 128-bit key subject to $P_{\\rm key}^{\\rm fail} < 10^{-6}$, which is under expectation. Thus, the MMR under measurement is not reported. Also, note that MMR required in practice is magnitudes smaller than the one from prediction as the later is a very conservative bound.\n    \\end{tablenotes}\n\t\\label{tab:MMRTable} \n\\end{table}\n\n\\begin{figure}[!ht]\n\t\\centering\n\t\\includegraphics[width=\\linewidth]{SystemOverview.pdf}\n\t\\caption{(a) System overview, (b) Experiment setup: Verifier consists of \\circled{1} a laptop as the cloud Server and \\circled{2} a smartphone as the Gateway; Prover is \\circled{3} a commercial widely used nRF52832 Bluetooth-LE sensor. See the demo video for more details \\href{https:\/\/youtu.be\/O5NWZw-swpw}{\\underline{https:\/\/youtu.be\/O5NWZw-swpw}}.}\n\t\\label{fig:Overview}\n\\end{figure}\n\n\n\\section{Security Function Implementation Comparison}\\label{Sec:CaseStudy}\n\nRemote attestation allows one party to establish trust in another. Building upon $\\digamma$ bits that naturally tolerate a high degree of noise, we use it to attest the firmware integrity of deployed IoT devices during boot-up by a verifier~\\cite{dinu2019sia} in a demonstrable case study to evaluate the practicability of noise tolerant memory fingerprints and compare the overhead of the NoisFre with the conventional (reverse) fuzzy extractor. Notably, we experimentally show that SRAM fingerprints can be accessed on-demand and at \\textit{run-time} by exploiting the MCU's memory power control features. \n\n\\subsection{System Overview}\nThe entities, a Verifier and a Prover, involved in this case study are illustrated in \\autoref{fig:Overview} (a). The Verifier consists of a server and a wireless network gateway (smartphone), the Prover refers to a wireless sensor node (Bluetooth chip). In this setup, the server serves as a coordinator, holds the enrolled Provers information in the database, and issues command to instruct the Prover to perform remote attestation\u2014the gateway bridges the communication between the server and the Prover. The traffic between the server and the gateway is assumed secure by applying standard security protection mechanism\\footnote{This standard security protection is out the scope of this work.}. The Prover is wirelessly deployed in the (insecure) environment. Details of the corresponding attestation protocol are provided below. {\\it Our case study is on carrying out lightweight remote attestation upon the Prover with constrained resource by following~\\cite{dinu2019sia}}.\n\n \\begin{figure}[!ht]\n\\centering\n\\resizebox{\\linewidth}{!}\n    \\fbox{$\n        \\Huge\n        \\begin{array}{ccc}\n        \\mc{\\text{Verifier}} & & \\mc{\\text{Prover}} \\\\\n        {\\bf DB} =  \\{(\\text{ID}_0,\\digamma_0'),\\ldots,(\\text{ID}_n,\\digamma_n')\\} & & \\text{ID}_i,\\text{Memory}\\\\\n        \\text{App = },(bin',{\\rm addr},{\\rm leng}) & & mask_i\\\\\n        \\text{FingerPrint = }({\\rm fprt},{\\rm addr}_{\\ff},{\\rm leng}_{\\ff})\\\\\n        \n        \n        \\cmidrule{1-3}\n        \\rowcolor{LightCyan}\n        \\multicolumn{3}{c}{\\textbf{Enrollment} ~ \\textsf{(one-time task under secure environment)}} \\\\\n        \\cmidrule{1-3}\n        & {\\rm addr}_{\\ff},{\\rm leng}_{\\ff} & \\\\\n        & \\xrightarrow{~~~~~~~~~~~~~~~~~~~~} & {\\rm fprt}_i \\leftarrow \\textsf{Memory}({\\rm addr}_{\\ff},{\\rm leng}_{\\ff})\\\\\n        & {\\rm ID}_i,{\\rm fprt}_i & \\\\\n        \\mc{\\{mask_i,\\digamma_i\\} \\leftarrow \\textsf{FingerPrint}({\\rm fprt}_i)} & \\xleftarrow{~~~~~~~~~~~~~~~~~~~~} & \\\\\n        \\mc{\\text{Insert } ({\\rm ID}_i,\\digamma_i) \\text{ into } \\textbf{DB}} & mask_i & \\\\\n        & \\xrightarrow{~~~~~~~~~~~~~~~~~~~~} & \\text{Store } mask_i \\text{ into}\\\\\n        & & \\text{non-volatile memory}\\\\\n        \n        \\cmidrule{1-3}\n        \\rowcolor{LightCyan}\n        \\multicolumn{3}{c}{\\textbf{Attestation} ~ \\textsf{(whenever requested after deploy)}} \\\\\n        \\cmidrule{1-3}\n        & \\text{hello} & \\\\\n        & \\xrightarrow{~~~~~~~~~~} &\\\\\n        & {\\rm ID} &\\\\\n        \\text{if } {\\rm ID} \\in {\\bf DB} \\text{ continue} & \\xleftarrow{~~~~~~~~~~} & \\\\\n        \\text{otherwise abort}\\\\\n        & \\text{prepare attestation} & \\\\\n        & \\xrightarrow{~~~~~~~~~~~~~~~~~~~~~~~~~} & \\text{Power cycling }\\\\\n        & & \\text{FingerPrint memory zone}\\\\\n        & \\text{ready for attestation} &\\\\\n        & \\xleftarrow{~~~~~~~~~~~~~~~~~~~~~~~~~} & \\digamma_i \\leftarrow \\textsf{FingerPrint}(mask_i)\\\\\n        chal \\leftarrow \\textsf{RNG}() & chal, {\\rm addr}, {\\rm leng} & \\\\\n        \\digamma_i' \\leftarrow \\textsf{DB}(\\text{ID}) & \\xrightarrow{~~~~~~~~~~~~~~~~~~~~~~~~~} & bin \\leftarrow \\textsf{Memory}({\\rm addr},{\\rm leng})\\\\\n        resp' \\leftarrow \\textsf{CMAC}_{\\digamma_i'}(bin',chal) &  & resp \\leftarrow \\textsf{CMAC}_{\\digamma_i}(bin,chal)\\\\\n        & resp & \\\\\n        \\text{if } resp' == resp & \\xleftarrow{~~~~~~~~~~} & \\\\\n        \\text{attestation accepted}\\\\\n        \\text{otherwise reject}\\\\\n\\end{array}\n    $\n\n\\caption{Remote attestation protocol.}\n\\label{fig:Protocol}\n\\end{figure}\n\n\\noindent{\\bf Protocol.} The protocol overview of remote attestation on the NoisFre is illustrated in Fig.~\\ref{fig:Protocol}. It has two phases: enrollment (one-time task) and attestation (requested multiple times).\n\n{\\it Enrollment:} The enrollment executes one-time-only, under a secure environment by the Verifier. Fingerprints of dedicated SRAM section (coined as FingerPrint zone)\\footnote{A small SRAM fraction should be preserved for program variables.} specified by a starting address $\\rm addf_{\\ff}$ and length $\\rm leng_{\\ff}$ is read out from the Prover, termed as $\\rm fprt_i$. Prover's immutable identification number ${\\rm ID}_i$ and the $\\rm fprt_i$ are then stored in Verifier's database (DB). In this case study, the D-Norm\\footnote{The setting is: $n=32$ and $m=16$, which is the best parameter as in Table~\\ref{tab:comparison}.} (Section~\\ref{Sec:DHWMethod}) is applied to extract highly noise-tolerant bits ${ \\digamma}_i$ and the corresponding $ {\\rm mask}_i$ (mask points to the position of ${ \\digamma}_i$, detailed in \\textbf{Appendix~\\ref{app:fingMask}}). Both ${ \\digamma}_i$ and ${\\rm mask}_i$ are stored in the Verifier's DB. The $ {\\rm mask}_i$ is then stored on Prover's readable but non-writable memory, which is realized by instantiating an immutable bootloader~\\cite{kohnhauser2016secure}. After then, the Prover is deployed and only wirelessly accessible.\n\n{\\it Attestation:} The remote attestation can be requested anytime. First, the Verifier scans for visible Provers by sending the message ``hello\". Once there is a Prover in the horizon responding with its ${\\rm ID}_i$. The Verifier fetches Prover's information from the DB by indexing the ${\\rm ID}_i$. Second, if the received ${\\rm ID}_i$ matches one of that stored in the Verifier's DB, the Verifier instructs the Prover to perform attestation. In this context, the Prover performs a power cycling for memory banks {\\it solely} corresponding to the FingerPrint zone\\footnote{Each memory bank can be individually powered off by exploiting particular power control register---thus, enabling SRAM run-time fingerprinting.} to regenerate $\\digamma_i$ under the enrolled ${\\rm mask}_i$ on {\\it run-time}. After confirming ready acknowledge from the Prover, the Verifier randomly generates a challenge\/nonce ${\\rm chal}$, and sends it to the Prover along with the address ${\\rm addr}_{\\ff}$ and the length ${\\rm leng}_{\\ff}$ of the target App code $\\rm bin$ in Prover's memory. Meanwhile, the Verifier also loads the enrolled ${ \\digamma'}_i$ from the DB. The Prover's response $ \\rm resp$ is generated using Cipher-based Message Authentication Code (CMAC) through the noise-tolerant fingerprint ${ \\digamma}_i$, detailed in Fig.~\\ref{fig:dataFlow} in \\textbf{Appendix}. The Verifier compares the received response $ \\rm resp$ with locally calculated reference response $ {\\rm resp}'$. The remote attestation is accepted if $ \\rm resp$ and $ {\\rm resp}'$ match, otherwise rejected.\n\n\\subsection{Implementation Overhead Comparison}\\label{sec:overheadCompare}\n\n\\noindent{\\bf Implementation Details.} Detailed complete remote attestation system implementation is referred to the \\textbf{Appendix~\\ref{app:remAtt}} due to page limitation, while the end-to-end video demo is at \\href{https:\/\/youtu.be\/O5NWZw-swpw}{\\underline{https:\/\/youtu.be\/O5NWZw-swpw}}.\n\n\\noindent{\\bf Performance Comparison.}\\label{Sec:EndtoEnd}\nThe overhead is mainly measured by the number of clock cycles used by the MCU. Overall, in terms of obtaining 128 bits reliable $ \\digamma$, the implementation of D-Norm based NoisFre takes 44,082 clock cycles. In contrast, to achieve 128 bits of reliable $ \\digamma$ via error correction, it costs greatly higher overhead. Specifically, as evaluated in Table~\\ref{tab:FEandRFE}, using FE (only counting decoding overhead) and RFE (only counting encoding overhead) cost 553,278 and 166,296 clock cycles, respectively. Therefore, NoisFre reduces clock overhead by 73.50\\% even in comparison with the state-of-the-art {\\it RFE} case. As for the {\\it complete remote attestation} (including the key derivation and following operations such as CMAC), NoisFre reduces clock cycles (91,518) by 84.76\\% and 57.18\\% in comparison with using FE (600,714) and RFE (213,732). \n \nNotably, we have compared NoisFre with (R)FE under a relaxed setting: giving a key with $P_{\\rm key}^{\\rm fail}<10^{-6}$, while the NoisFre can provide a key with much lower $P_{\\rm key}^{\\rm fail}$ \\textit{eg.,} $10^{-13}$, given abundant \\textit{free} memory size. Suppose such small $P_{\\rm key}^{\\rm fail}$ achievable by the NoisFre is asked using (R)FE, a much higher computational overhead will be incurred using (R)FE. \n\n\n\\section{Discussions}\\label{Sec:discussion}\n\n\\vspace{0.1cm}\n\\noindent{\\bf Generality of NoisFre.}\nAlthough this work focuses on the SRAM memory considering its {\\it ubiquity in low-end IoT devices}, the presented NoisFre fingerprinting is applicable for other memories, including Flash and EEPROM memories validated. Besides, in principle, it can be applied to any other hardware fingerprints~\\cite{pappu2002physical,ruhrmair2010applications} given that the raw digital fingerprint bits space is abundant.\n\n\\vspace{0.1cm}\n\\noindent{\\bf Comparison with (Reverse) Fuzzy Extractor.}\nNoisFre fundamentally obviates computational-heavy on-device ECC logic to be lightweight. It is thus immune to the helper data manipulation (HDM) attack~\\cite{delvaux2014helper,becker2017robust} that strategically tamper the helper data \\textit{associated with the ECC} to weaken or compromise the key extracted via the (R)FE. \nThe vulnerability is induced by the usage of {\\it error correction codes}. Various error correction codes are examined and shown to be vulnerable to HDM attacks~\\cite{becker2017robust}. A generic countermeasure against HDM attacks does not yet exist, appears to be an open challenge. The NoisFre scheme has ultimately abandoned the necessity of helper data associated with ECC, thus avoids the HDM attack that exploits ECC helper data~\\cite{becker2017robust}. \nIn our implementation, we have put the position mask (provision of the mask is detailed in \\textbf{Appendix~\\ref{app:fingMask}}) into the immutable bootloader, thus, prevent tampering. A MAC can be produced over the transformed bits derived key for later mask integrity checking to defeat any tampering when the mask is stored in a writable memory. \n\n\\vspace{0.1cm}\n\\noindent{\\bf Provisioning Fingerprints at Run-time}\nThe Flash and EEPROM memory fingerprints can be accessed during run-time. As for SRAM fingerprinting, the most common way is utilizing its initialization pattern as fingerprint, although there are other means~\\cite{xu2015reliable} \\textit{eg.} using data retention voltage~\\cite{xu2015reliable} or intentionally put SRAM cell under a meta-stable state. However, those methods usually require customized peripheral circuitry that tends to be unavailable in COTS devices. Thus, SRAM fingerprinting generally requires power cycling to read the start-up values. As a matter of fact, some low-end microcontrollers allow direct control to the power of individual SRAM bank~\\cite{semiconductor2016nrf52832}; for example, the low-end nRF52832 studied in this work. Consequently, by leveraging such feature, SRAM fingerprint based root-keys can be requested during {\\it run-time}. \n\n\\section{Related Work}\\label{Sec:relatedwork}\nBesides memories, various on-board sensors such as camera, accelerometer, gyroscope, magnetometer, and other components such as CPU magnetic radiations are utilized to provide fingerprints~\\cite{bojinov2014mobile,son2018gyrosfinger,kim2018c,ba2018abc,willers2016mems,zhang2019sensorid,ba2019cim,quiring2019security,cheng2019demicpu}. Other recent works also explore commodity scanners to fingerprint 3D objects in order to track them~\\cite{li2018printracker} and exploit the package variations as fingerprints for anti-counterfeiting~\\cite{251596}. However, to obtain hardware fingerprints, those fingerprint extractions are relatively complicated in comparison with the memory (especially SRAM) enabled fingerprints. Moreover, only a limited number of raw bits can be extracted---applying fingerprint space transformation as NoisFre does on them is prohibitive. Therefore, subsequent computational-heavy error correction has to be mounted. Most importantly, in comparison with the memory, these accessories are less pervasive in IoT devices. \n\nHardware fingerprinting is closely related to the notion of physical unclonable function (PUF)~\\cite{chang2017retrospective,herder2014physical,ruhrmair2013pufs}. Commodity memory fingerprinting, such as SRAM PUF and Flash PUF, is not new. However, mounting them on low-end IoT devices to derive a usable key for security functions rely on post-error correction to reconcile bits errors, which is cumbersome in terms of both overhead and security in practice. Our simple yet efficient NoisFre memory-fingerprinting addresses this gap.\n\n\\section{Conclusion}\\label{Sec:conclusion}\nBy exploiting ubiquitously embedded memory within commodity computing devices, the proposed NoisFre constructively extracts transformed memory fingerprints that are with natural tolerance on a high noise degree. With a simple single fingerprint enrollment measurement, the NoisFre is now able to judiciously identify highly reliable transformed fingerprints serving as hardware root key to directly support various security functions that are lightweight and practical for a wide range of COTS electronics. Besides formalization of two specific disclosed S-Norm and D-Norm fingerprint transformation methods and extensive empirical validations on SRAM, Flash, and EEPROM memories using 38 real chips in total, we have case-studied an end-to-end remote attestation employing NoisFre fingerprints to significantly reduce the overhead more than half in comparison with the state-of-the-art. We also show that SRAM fingerprints can be provided {\\rm run-time} by utilizing individual memory-bank power control features. Overall, the presented NoisFre offers a {\\it simple but practical} security function, especially for {\\it existing low-end commodity electronics}.\n\n\\Urlmuskip=0mu plus 1mu\\relax\n","meta":{"redpajama_set_name":"RedPajamaArXiv"}}